RV64IMACFDArchSpecificImp.cpp

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#include <vector>
 
#include "RV64IMACFDArch.h"
#include "RV64IMACFDArchSpecificImp.h"
#include "RV64IMACFDFuncs.h"
 
etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
{
        RV64IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause);
        cpu->instructionPointer = cpu->nextPc;
        return 0;
}
etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu) {…}
 
void RV64IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const
{
 
    {
     /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */
     std::string cfgPar = "";
     cfgPar = etiss::cfg().get<std::string>("jit.external_headers", ";");
     etiss::cfg().set<std::string>("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h");
 
     cfgPar = etiss::cfg().get<std::string>("jit.external_libs", ";");
     etiss::cfg().set<std::string>("jit.external_libs", cfgPar + "softfloat");
 
     cfgPar = etiss::cfg().get<std::string>("jit.external_header_paths", ";");
     etiss::cfg().set<std::string>("jit.external_header_paths", cfgPar + "/etiss/jit");
 
     cfgPar = etiss::cfg().get<std::string>("jit.external_lib_paths", ";");
     etiss::cfg().set<std::string>("jit.external_lib_paths", cfgPar + "/etiss/jit");
 
    }
 
    if (false) {
        // Pre-compilation of instruction set to view instruction tree. Could be disabled.
        etiss::instr::ModedInstructionSet iset("RV64IMACFDISA");
                bool ok = true;
                RV64IMACFDISA.addTo(iset,ok);
 
                iset.compile();
 
                std::cout << iset.print() << std::endl;
        }
 
        bool ok = true;
        RV64IMACFDISA.addTo(mis,ok);
        if (!ok)
                etiss::log(etiss::FATALERROR,"Failed to add instructions for RV64IMACFDISA");
 
        etiss::instr::VariableInstructionSet *vis = mis.get(1);
 
        using namespace etiss;
        using namespace etiss::instr;
 
        vis->get(32)->getInvalid().addCallback(
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint32 error_code = 0;
static BitArrayRange R_error_code_0(31, 0);
error_code += R_error_code_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//trap_entry 32\n");
 
// -----------------------------------------------------------------------------
{ // procedure
cp.code() += "{ // procedure\n";
cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
cp.code() += "} // procedure\n";
} // procedure
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
        {
                CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
                cp.code() = std::string("//trap_entry 32\n");
 
// -----------------------------------------------------------------------------
cp.code() += "return cpu->exception;\n";
// -----------------------------------------------------------------------------
        }
 
                return true;
        },
        0
        );
 
        vis->get(16)->getInvalid().addCallback(
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint32 error_code = 0;
static BitArrayRange R_error_code_0(31, 0);
error_code += R_error_code_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//trap_entry 16\n");
 
// -----------------------------------------------------------------------------
{ // procedure
cp.code() += "{ // procedure\n";
cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
cp.code() += "} // procedure\n";
} // procedure
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
        {
                CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
                cp.code() = std::string("//trap_entry 16\n");
 
// -----------------------------------------------------------------------------
cp.code() += "return cpu->exception;\n";
// -----------------------------------------------------------------------------
        }
 
                return true;
        },
        0
        );
 
    vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
        std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRV64IMACFDInstrLength =
            [](InstructionContext &ic, etiss_uint32 opRd) {
                ic.instr_width_fully_evaluated_ = true;
                ic.is_not_default_width_ = true;
                if (opRd == 0x3f)
                    ic.instr_width_ = 64;
                else if ((opRd & 0x3f) == 0x1f)
                    ic.instr_width_ = 48;
                else if (((opRd & 0x1f) >= 0x3) && ((opRd & 0x1f) < 0x1f))
                    ic.instr_width_ = 32;
                else if(opRd == 0x7f) /* P-Extension instructions */
                    ic.instr_width_ = 32;
                else if ((opRd & 0x3) != 0x3)
                    ic.instr_width_ = 16;
                else
                    // This might happen when code is followed by data.
                    ic.is_not_default_width_ = false;
            };
 
        BitArrayRange op(6, 0);
        etiss_uint32 opRd = op.read(ba);
 
        /*BitArrayRange fullOp(ba.byteCount()*8-1,0);
        etiss_uint32 fullOpRd = fullOp.read(ba);
 
        std::stringstream ss;
        ss << "Byte count: " << ba.byteCount()<< std::endl;
        ss << "opcode: 0x" <<std::hex<< fullOpRd << std::endl;
        ss << "Current PC: 0x" <<std::hex<< ic.current_address_ << std::endl;
        std::cout << ss.str() << std::endl;*/
 
        switch (ba.byteCount())
        {
        case 2:
            if (((opRd & 0x3) != 0x3) || (opRd == 0))
            {
                ic.is_not_default_width_ = false;
                break;
            }
            else
            {
                updateRV64IMACFDInstrLength(ic, opRd);
                break;
            }
        case 4:
            if ((((opRd & 0x1f) >= 0x3) || ((opRd & 0x1f) < 0x1f)) || (opRd == 0))
            {
                ic.is_not_default_width_ = false;
                break;
            }
            else if(opRd == 0x7f) /* P-Extension instructions */
            {
                updateRV64IMACFDInstrLength(ic, opRd);
                break;
            }
            else
            {
                updateRV64IMACFDInstrLength(ic, opRd);
                break;
            }
        case 6:
            if (((opRd & 0x3f) == 0x1f) || (opRd == 0))
            {
                ic.is_not_default_width_ = false;
                break;
            }
            else
            {
                updateRV64IMACFDInstrLength(ic, opRd);
                break;
            }
        case 8:
            if ((opRd == 0x3f) || (opRd == 0))
            {
                ic.is_not_default_width_ = false;
                break;
            }
            else
            {
                updateRV64IMACFDInstrLength(ic, opRd);
                break;
            }
        default:
            // This might happen when code is followed by data.
            ic.is_not_default_width_ = false;
        }
    };
 
}
void RV64IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const {…}
 
void RV64IMACFDArch::compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const
{
        /**************************************************************************
        *                               Endianess compensation                            *
        ***************************************************************************/
}
void RV64IMACFDArch::compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const {…}
 
std::shared_ptr<etiss::VirtualStruct> RV64IMACFDArch::getVirtualStruct(ETISS_CPU * cpu)
{
        auto ret = etiss::VirtualStruct::allocate(
                cpu,
                [] (etiss::VirtualStruct::Field*f) {
                        delete f;
                }
        );
 
        for (uint32_t i = 0; i < 32; ++i){
                ret->addField(new RegField_RV64IMACFD(*ret,i));
        }
 
        ret->addField(new pcField_RV64IMACFD(*ret));
        return ret;
}
std::shared_ptr<etiss::VirtualStruct> RV64IMACFDArch::getVirtualStruct(ETISS_CPU * cpu) {…}
 
etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
{
        if (cpu == 0)
                return 0;
 
        std::vector<etiss::uint64 *> vec;
        std::vector<etiss::uint64 *> mask;
 
        vec.push_back(&((RV64IMACFD*)cpu)->MIP);
        mask.push_back(&((RV64IMACFD*)cpu)->MIE);
 
        return new etiss::MappedInterruptVector<etiss::uint64>(vec, mask);
}
etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu) {…}
 
void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu)
{
        delete vec;
}
void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu) {…}
 
etiss::InterruptEnable* RV64IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {
        return new etiss::MappedInterruptEnable<etiss::uint64>(&((RV64IMACFD*)cpu)->MSTATUS, 15);
}
etiss::InterruptEnable* RV64IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) {…}
 
void RV64IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {
        delete en;
}
void RV64IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) {…}