ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFDFuncs.c
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1 
7 #include "RV64IMACFDFuncs.h"
8 
9 etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
10 {
11 etiss_coverage_count(1, 80);
12 { // block
13 etiss_coverage_count(1, 257);
14 etiss_coverage_count(1, 256);
15 return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
16 etiss_coverage_count(9, 255, 252, 247, 250, 248, 249, 251, 253, 254);
17 } // block
18 }
19 
20 etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
21 {
22 etiss_coverage_count(1, 87);
23 { // block
24 etiss_coverage_count(1, 277);
25 etiss_coverage_count(1, 258);
26 if (rm == 7ULL) { // conditional
27 etiss_coverage_count(3, 261, 259, 260);
28 rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7ULL)) & 0x7;
29 etiss_coverage_count(6, 267, 262, 266, 263, 264, 265);
30 } // conditional
31 etiss_coverage_count(1, 268);
32 if (rm > 4ULL) { // conditional
33 etiss_coverage_count(3, 271, 269, 270);
34 RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);
35 etiss_coverage_count(2, 274, 272);
36 } // conditional
37 etiss_coverage_count(1, 276);
38 return rm;
39 etiss_coverage_count(1, 275);
40 } // block
41 }
42 
43 etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
44 {
45 etiss_coverage_count(1, 149);
46 { // block
47 etiss_coverage_count(1, 350);
48 etiss_uint64 mask = 0LL;
49 etiss_coverage_count(2, 280, 279);
50 etiss_coverage_count(1, 281);
51 if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
52 etiss_coverage_count(2, 283, 282);
53 { // block
54 etiss_coverage_count(1, 347);
55 mask = mask | 5767458ULL;
56 etiss_coverage_count(2, 299, 284);
57 etiss_coverage_count(1, 300);
58 if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
59 etiss_coverage_count(2, 302, 301);
60 mask = mask | 1536LL;
61 etiss_coverage_count(2, 305, 303);
62 } // conditional
63 etiss_coverage_count(1, 306);
64 if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
65 etiss_coverage_count(2, 308, 307);
66 mask = mask | 24576LL;
67 etiss_coverage_count(2, 311, 309);
68 } // conditional
69 etiss_coverage_count(1, 312);
70 if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
71 etiss_coverage_count(2, 314, 313);
72 mask = mask | 98304LL;
73 etiss_coverage_count(2, 317, 315);
74 } // conditional
75 etiss_coverage_count(1, 318);
76 if ((RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
77 etiss_coverage_count(3, 340, 336, 342);
78 mask = mask | 262144LL;
79 etiss_coverage_count(2, 346, 344);
80 } // conditional
81 } // block
82 } // conditional
83 etiss_coverage_count(1, 349);
84 return mask;
85 etiss_coverage_count(1, 348);
86 } // block
87 }
88 
89 etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
90 {
91 etiss_coverage_count(1, 150);
92 { // block
93 etiss_coverage_count(1, 365);
94 etiss_uint64 mask = 6280ULL;
95 etiss_coverage_count(1, 360);
96 etiss_coverage_count(1, 364);
97 return mask | RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
98 etiss_coverage_count(3, 363, 361, 362);
99 } // block
100 }
101 
102 etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
103 {
104 etiss_coverage_count(1, 151);
105 { // block
106 etiss_coverage_count(1, 483);
107 etiss_coverage_count(1, 366);
108 if (csr == 1LL) { // conditional
109 etiss_coverage_count(2, 369, 367);
110 etiss_coverage_count(1, 375);
111 return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
112 etiss_coverage_count(3, 374, 372, 373);
113 } // conditional
114 etiss_coverage_count(1, 376);
115 if (csr == 2LL) { // conditional
116 etiss_coverage_count(2, 379, 377);
117 etiss_coverage_count(1, 388);
118 return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
119 etiss_coverage_count(6, 387, 384, 382, 383, 385, 386);
120 } // conditional
121 etiss_coverage_count(1, 389);
122 if (csr == 3072LL) { // conditional
123 etiss_coverage_count(2, 392, 390);
124 etiss_coverage_count(1, 394);
125 return etiss_get_cycles(cpu, system, plugin_pointers);
126 etiss_coverage_count(1, 393);
127 } // conditional
128 etiss_coverage_count(1, 395);
129 if (csr == 3200LL) { // conditional
130 etiss_coverage_count(2, 398, 396);
131 etiss_coverage_count(1, 402);
132 return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
133 etiss_coverage_count(3, 401, 399, 400);
134 } // conditional
135 etiss_coverage_count(1, 403);
136 if (csr == 3073LL) { // conditional
137 etiss_coverage_count(2, 406, 404);
138 etiss_coverage_count(1, 408);
139 return etiss_get_time();
140 etiss_coverage_count(1, 407);
141 } // conditional
142 etiss_coverage_count(1, 409);
143 if (csr == 3201LL) { // conditional
144 etiss_coverage_count(2, 412, 410);
145 etiss_coverage_count(1, 416);
146 return etiss_get_time() >> 32ULL;
147 etiss_coverage_count(3, 415, 413, 414);
148 } // conditional
149 etiss_coverage_count(1, 417);
150 if (csr == 3074LL) { // conditional
151 etiss_coverage_count(2, 420, 418);
152 etiss_coverage_count(1, 422);
153 return etiss_get_instret(cpu, system, plugin_pointers);
154 etiss_coverage_count(1, 421);
155 } // conditional
156 etiss_coverage_count(1, 423);
157 if (csr == 3202LL) { // conditional
158 etiss_coverage_count(2, 426, 424);
159 etiss_coverage_count(1, 430);
160 return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
161 etiss_coverage_count(3, 429, 427, 428);
162 } // conditional
163 etiss_coverage_count(1, 431);
164 if (csr == 768LL || csr == 256LL) { // conditional
165 etiss_coverage_count(5, 438, 434, 432, 437, 435);
166 etiss_coverage_count(1, 458);
167 return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
168 etiss_coverage_count(3, 457, 449, 441);
169 } // conditional
170 etiss_coverage_count(1, 459);
171 if (csr == 769LL) { // conditional
172 etiss_coverage_count(2, 462, 460);
173 etiss_coverage_count(1, 478);
174 return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0LL)) & 4611686018427387903ULL)));
175 etiss_coverage_count(4, 477, 476, 471, 475);
176 } // conditional
177 etiss_coverage_count(1, 482);
178 return *((RV64IMACFD*)cpu)->CSR[csr];
179 etiss_coverage_count(2, 481, 480);
180 } // block
181 }
182 
183 void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
184 {
185 etiss_coverage_count(1, 152);
186 { // block
187 etiss_coverage_count(1, 565);
188 etiss_coverage_count(1, 484);
189 if (csr == 1LL) { // conditional
190 etiss_coverage_count(2, 487, 485);
191 *((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
192 etiss_coverage_count(10, 520, 505, 519, 513, 508, 514, 517, 515, 516, 518);
193 } // conditional
194  else if (csr == 2LL) { // conditional
195 etiss_coverage_count(2, 490, 488);
196 *((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
197 etiss_coverage_count(14, 538, 523, 537, 529, 526, 524, 525, 527, 528, 530, 535, 533, 534, 536);
198 } // conditional
199  else if (csr == 3LL) { // conditional
200 etiss_coverage_count(2, 493, 491);
201 *((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
202 etiss_coverage_count(5, 545, 541, 544, 542, 543);
203 } // conditional
204  else if (csr == 768LL) { // conditional
205 etiss_coverage_count(2, 496, 494);
206 *((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_mstatus_mask(cpu, system, plugin_pointers);
207 etiss_coverage_count(5, 552, 548, 551, 549, 550);
208 } // conditional
209  else if (csr == 256LL) { // conditional
210 etiss_coverage_count(2, 499, 497);
211 *((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
212 etiss_coverage_count(5, 559, 555, 558, 556, 557);
213 } // conditional
214  else if (csr != 769LL) { // conditional
215 etiss_coverage_count(2, 502, 500);
216 *((RV64IMACFD*)cpu)->CSR[csr] = val;
217 etiss_coverage_count(4, 564, 562, 561, 563);
218 } // conditional
219 } // block
220 }
221 
222 etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
223 {
224 etiss_coverage_count(1, 159);
225 { // block
226 etiss_coverage_count(1, 585);
227 etiss_coverage_count(1, 566);
228 if (!(mask)) { // conditional
229 etiss_coverage_count(2, 568, 567);
230 etiss_coverage_count(1, 570);
231 return 0LL;
232 etiss_coverage_count(1, 569);
233 } // conditional
234 etiss_coverage_count(1, 584);
235 return (reg & mask) / (mask & ~((mask << 1ULL)));
236 etiss_coverage_count(13, 583, 573, 571, 572, 574, 581, 575, 580, 578, 576, 577, 579, 582);
237 } // block
238 }
239 
240 etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
241 {
242 etiss_coverage_count(1, 160);
243 { // block
244 etiss_coverage_count(1, 608);
245 etiss_coverage_count(1, 607);
246 return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
247 etiss_coverage_count(21, 605, 589, 586, 588, 587, 590, 603, 600, 591, 598, 592, 597, 595, 593, 594, 596, 599, 601, 602, 604, 606);
248 } // block
249 }
250 
251 etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val)
252 {
253 etiss_coverage_count(1, 161);
254 { // block
255 etiss_coverage_count(1, 703);
256 etiss_coverage_count(1, 609);
257 if (!(val)) { // conditional
258 etiss_coverage_count(2, 611, 610);
259 etiss_coverage_count(1, 613);
260 return 0LL;
261 etiss_coverage_count(1, 612);
262 } // conditional
263 etiss_uint8 res = 0LL;
264 etiss_coverage_count(2, 616, 615);
265 etiss_coverage_count(1, 617);
266 if ((val << 32ULL) == 0LL) { // conditional
267 etiss_coverage_count(6, 623, 620, 618, 619, 621, 622);
268 { // block
269 etiss_coverage_count(1, 630);
270 res = res + 32ULL;
271 etiss_coverage_count(3, 626, 624, 625);
272 val = val >> 32ULL;
273 etiss_coverage_count(3, 629, 627, 628);
274 } // block
275 } // conditional
276 etiss_coverage_count(1, 631);
277 if ((val << 48ULL) == 0LL) { // conditional
278 etiss_coverage_count(6, 637, 634, 632, 633, 635, 636);
279 { // block
280 etiss_coverage_count(1, 644);
281 res = res + 16ULL;
282 etiss_coverage_count(3, 640, 638, 639);
283 val = val >> 16ULL;
284 etiss_coverage_count(3, 643, 641, 642);
285 } // block
286 } // conditional
287 etiss_coverage_count(1, 645);
288 if ((val << 56ULL) == 0LL) { // conditional
289 etiss_coverage_count(6, 651, 648, 646, 647, 649, 650);
290 { // block
291 etiss_coverage_count(1, 658);
292 res = res + 8ULL;
293 etiss_coverage_count(3, 654, 652, 653);
294 val = val >> 8ULL;
295 etiss_coverage_count(3, 657, 655, 656);
296 } // block
297 } // conditional
298 etiss_coverage_count(1, 659);
299 if ((val << 60ULL) == 0LL) { // conditional
300 etiss_coverage_count(6, 665, 662, 660, 661, 663, 664);
301 { // block
302 etiss_coverage_count(1, 672);
303 res = res + 4ULL;
304 etiss_coverage_count(3, 668, 666, 667);
305 val = val >> 4ULL;
306 etiss_coverage_count(3, 671, 669, 670);
307 } // block
308 } // conditional
309 etiss_coverage_count(1, 673);
310 if ((val << 62ULL) == 0LL) { // conditional
311 etiss_coverage_count(6, 679, 676, 674, 675, 677, 678);
312 { // block
313 etiss_coverage_count(1, 686);
314 res = res + 2ULL;
315 etiss_coverage_count(3, 682, 680, 681);
316 val = val >> 2ULL;
317 etiss_coverage_count(3, 685, 683, 684);
318 } // block
319 } // conditional
320 etiss_coverage_count(1, 687);
321 if ((val << 63ULL) == 0LL) { // conditional
322 etiss_coverage_count(6, 693, 690, 688, 689, 691, 692);
323 { // block
324 etiss_coverage_count(1, 700);
325 res = res + 1ULL;
326 etiss_coverage_count(3, 696, 694, 695);
327 val = val >> 1ULL;
328 etiss_coverage_count(3, 699, 697, 698);
329 } // block
330 } // conditional
331 etiss_coverage_count(1, 702);
332 return res;
333 etiss_coverage_count(1, 701);
334 } // block
335 }
336 
337 void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
338 {
339 cpu->return_pending = 1;
340 cpu->exception = 0;
341 etiss_coverage_count(1, 162);
342 { // block
343 etiss_coverage_count(1, 916);
344 etiss_uint64 epc = cpu->instructionPointer;
345 etiss_coverage_count(2, 706, 705);
346 etiss_uint64 deleg = 0LL;
347 etiss_coverage_count(1, 708);
348 etiss_uint64 vector = 0LL;
349 etiss_coverage_count(1, 709);
350 etiss_uint64 bit = mcause;
351 etiss_coverage_count(2, 711, 710);
352 etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0LL;
353 etiss_coverage_count(6, 727, 726, 723, 713, 724, 725);
354 etiss_coverage_count(1, 728);
355 if (irq2) { // conditional
356 etiss_coverage_count(1, 729);
357 { // block
358 etiss_coverage_count(1, 754);
359 deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0LL);
360 etiss_coverage_count(8, 740, 730, 739, 733, 731, 734, 737, 738);
361 bit = bit & 9223372036854775807ULL;
362 etiss_coverage_count(2, 753, 741);
363 } // block
364 } // conditional
365 else { // conditional
366 { // block
367 etiss_coverage_count(1, 766);
368 deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0LL);
369 etiss_coverage_count(8, 765, 755, 764, 758, 756, 759, 762, 763);
370 } // block
371 } // conditional
372 etiss_coverage_count(1, 767);
373 if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
374 etiss_coverage_count(9, 777, 770, 768, 776, 773, 771, 772, 774, 775);
375 { // block
376 etiss_coverage_count(1, 846);
377 vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
378 etiss_coverage_count(13, 792, 778, 791, 786, 783, 781, 782, 784, 785, 789, 787, 788, 790);
379 cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
380 etiss_coverage_count(7, 805, 793, 804, 801, 796, 802, 803);
381 *((RV64IMACFD*)cpu)->CSR[321LL] = epc;
382 etiss_coverage_count(3, 810, 808, 809);
383 *((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
384 etiss_coverage_count(3, 815, 813, 814);
385 etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
386 etiss_coverage_count(2, 819, 818);
387 s = RV64IMACFD_set_field(s, 32LL, RV64IMACFD_get_field(s, 2LL));
388 etiss_coverage_count(6, 827, 820, 826, 821, 825, 823);
389 s = RV64IMACFD_set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
390 etiss_coverage_count(5, 833, 828, 832, 829, 831);
391 s = RV64IMACFD_set_field(s, 2LL, 0LL);
392 etiss_coverage_count(5, 839, 834, 838, 835, 837);
393 RV64IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
394 etiss_coverage_count(2, 842, 841);
395 ((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
396 etiss_coverage_count(2, 845, 843);
397 } // block
398 } // conditional
399 else { // conditional
400 { // block
401 etiss_coverage_count(1, 915);
402 vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
403 etiss_coverage_count(13, 861, 847, 860, 855, 852, 850, 851, 853, 854, 858, 856, 857, 859);
404 cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
405 etiss_coverage_count(7, 874, 862, 873, 870, 865, 871, 872);
406 *((RV64IMACFD*)cpu)->CSR[833LL] = epc;
407 etiss_coverage_count(3, 879, 877, 878);
408 *((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
409 etiss_coverage_count(3, 884, 882, 883);
410 etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
411 etiss_coverage_count(2, 888, 887);
412 s = RV64IMACFD_set_field(s, 128LL, RV64IMACFD_get_field(s, 8LL));
413 etiss_coverage_count(6, 896, 889, 895, 890, 894, 892);
414 s = RV64IMACFD_set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
415 etiss_coverage_count(5, 902, 897, 901, 898, 900);
416 s = RV64IMACFD_set_field(s, 8LL, 0LL);
417 etiss_coverage_count(5, 908, 903, 907, 904, 906);
418 RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
419 etiss_coverage_count(2, 911, 910);
420 ((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
421 etiss_coverage_count(2, 914, 912);
422 } // block
423 } // conditional
424 } // block
425 }
426 
427 void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
428 {
429 etiss_coverage_count(1, 163);
430 { // block
431 etiss_coverage_count(1, 973);
432 etiss_uint64 code = 0LL;
433 etiss_coverage_count(2, 920, 919);
434 etiss_coverage_count(1, 921);
435 if (cause == -2147483648LL) { // conditional
436 etiss_coverage_count(2, 924, 922);
437 etiss_coverage_count(1, 943);
438 return;
439 } // conditional
440  else if (cause == -5LL) { // conditional
441 etiss_coverage_count(2, 927, 925);
442 code = 5LL;
443 etiss_coverage_count(2, 946, 944);
444 } // conditional
445  else if (cause == -14LL) { // conditional
446 etiss_coverage_count(2, 930, 928);
447 code = 13LL;
448 etiss_coverage_count(2, 949, 947);
449 } // conditional
450  else if (cause == -6LL) { // conditional
451 etiss_coverage_count(2, 933, 931);
452 code = 7LL;
453 etiss_coverage_count(2, 952, 950);
454 } // conditional
455  else if (cause == -15LL) { // conditional
456 etiss_coverage_count(2, 936, 934);
457 code = 15LL;
458 etiss_coverage_count(2, 955, 953);
459 } // conditional
460  else if (cause == -7LL) { // conditional
461 etiss_coverage_count(2, 939, 937);
462 code = 1LL;
463 etiss_coverage_count(2, 958, 956);
464 } // conditional
465  else if (cause == -9LL) { // conditional
466 etiss_coverage_count(2, 942, 940);
467 { // block
468 etiss_coverage_count(1, 966);
469 code = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
470 etiss_coverage_count(3, 961, 959, 960);
471 etiss_coverage_count(1, 962);
472 if (!(code)) { // conditional
473 etiss_coverage_count(2, 964, 963);
474 etiss_coverage_count(1, 965);
475 return;
476 } // conditional
477 } // block
478 } // conditional
479 else { // conditional
480 code = 2LL;
481 etiss_coverage_count(2, 969, 967);
482 } // conditional
483 RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, code);
484 etiss_coverage_count(3, 972, 970, 971);
485 } // block
486 }
487 
488 etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
489 {
490 etiss_coverage_count(1, 164);
491 { // block
492 etiss_coverage_count(1, 1154);
493 etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
494 etiss_coverage_count(4, 982, 981, 977, 980);
495 etiss_coverage_count(1, 983);
496 if (!(pending_interrupts)) { // conditional
497 etiss_coverage_count(2, 985, 984);
498 etiss_coverage_count(1, 987);
499 return 0LL;
500 etiss_coverage_count(1, 986);
501 } // conditional
502 etiss_uint64 mie = RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
503 etiss_coverage_count(3, 994, 993, 991);
504 etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
505 etiss_coverage_count(9, 1006, 1005, 998, 996, 1003, 1001, 999, 1002, 1004);
506 etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
507 etiss_coverage_count(8, 1017, 1016, 1013, 1008, 1012, 1011, 1015, 1014);
508 etiss_coverage_count(1, 1018);
509 if (enabled_interrupts == 0LL) { // conditional
510 etiss_coverage_count(3, 1021, 1019, 1020);
511 { // block
512 etiss_coverage_count(1, 1053);
513 etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
514 etiss_coverage_count(2, 1026, 1025);
515 etiss_uint64 sie = RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
516 etiss_coverage_count(3, 1032, 1031, 1029);
517 etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
518 etiss_coverage_count(9, 1044, 1043, 1036, 1034, 1041, 1039, 1037, 1040, 1042);
519 enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
520 etiss_coverage_count(8, 1052, 1045, 1051, 1048, 1046, 1047, 1050, 1049);
521 } // block
522 } // conditional
523 etiss_coverage_count(1, 1054);
524 if (enabled_interrupts) { // conditional
525 etiss_coverage_count(1, 1055);
526 { // block
527 etiss_coverage_count(1, 1151);
528 etiss_coverage_count(1, 1056);
529 if (enabled_interrupts >> 12ULL) { // conditional
530 etiss_coverage_count(2, 1062, 1057);
531 enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
532 etiss_coverage_count(5, 1105, 1093, 1104, 1099, 1094);
533 } // conditional
534  else if (enabled_interrupts & 2048LL) { // conditional
535 etiss_coverage_count(2, 1065, 1063);
536 enabled_interrupts = 2048LL;
537 etiss_coverage_count(2, 1108, 1106);
538 } // conditional
539  else if (enabled_interrupts & 8LL) { // conditional
540 etiss_coverage_count(2, 1068, 1066);
541 enabled_interrupts = 8LL;
542 etiss_coverage_count(2, 1111, 1109);
543 } // conditional
544  else if (enabled_interrupts & 128LL) { // conditional
545 etiss_coverage_count(2, 1071, 1069);
546 enabled_interrupts = 128LL;
547 etiss_coverage_count(2, 1114, 1112);
548 } // conditional
549  else if (enabled_interrupts & 512LL) { // conditional
550 etiss_coverage_count(2, 1074, 1072);
551 enabled_interrupts = 512LL;
552 etiss_coverage_count(2, 1117, 1115);
553 } // conditional
554  else if (enabled_interrupts & 2LL) { // conditional
555 etiss_coverage_count(2, 1077, 1075);
556 enabled_interrupts = 2LL;
557 etiss_coverage_count(2, 1120, 1118);
558 } // conditional
559  else if (enabled_interrupts & 32LL) { // conditional
560 etiss_coverage_count(2, 1080, 1078);
561 enabled_interrupts = 32LL;
562 etiss_coverage_count(2, 1123, 1121);
563 } // conditional
564  else if (enabled_interrupts & 8192LL) { // conditional
565 etiss_coverage_count(2, 1083, 1081);
566 enabled_interrupts = 8192LL;
567 etiss_coverage_count(2, 1126, 1124);
568 } // conditional
569  else if (enabled_interrupts & 1024LL) { // conditional
570 etiss_coverage_count(2, 1086, 1084);
571 enabled_interrupts = 1024LL;
572 etiss_coverage_count(2, 1129, 1127);
573 } // conditional
574  else if (enabled_interrupts & 4LL) { // conditional
575 etiss_coverage_count(2, 1089, 1087);
576 enabled_interrupts = 4LL;
577 etiss_coverage_count(2, 1132, 1130);
578 } // conditional
579  else if (enabled_interrupts & 64LL) { // conditional
580 etiss_coverage_count(2, 1092, 1090);
581 enabled_interrupts = 64LL;
582 etiss_coverage_count(2, 1135, 1133);
583 } // conditional
584 else { // conditional
585 etiss_coverage_count(1, 1137);
586 return 0LL;
587 etiss_coverage_count(1, 1136);
588 } // conditional
589 etiss_coverage_count(1, 1150);
590 return 9223372036854775808ULL | RV64IMACFD_ctz(enabled_interrupts);
591 etiss_coverage_count(3, 1149, 1148, 1147);
592 } // block
593 } // conditional
594 etiss_coverage_count(1, 1153);
595 return 0LL;
596 etiss_coverage_count(1, 1152);
597 } // block
598 }
599 
600 void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
601 {
602 etiss_coverage_count(1, 165);
603 { // block
604 etiss_coverage_count(1, 1163);
605 etiss_uint64 irq_mcause = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
606 etiss_coverage_count(2, 1157, 1156);
607 etiss_coverage_count(1, 1158);
608 if (irq_mcause) { // conditional
609 etiss_coverage_count(1, 1159);
610 RV64IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
611 etiss_coverage_count(3, 1162, 1160, 1161);
612 } // conditional
613 } // block
614 }
615 
616 etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y)
617 {
618 etiss_coverage_count(1, 237);
619 { // block
620 etiss_coverage_count(1, 6907);
621 etiss_int128 res = (etiss_int128)(x) * (etiss_int128)(y);
622 etiss_coverage_count(6, 6899, 6898, 6894, 6892, 6897, 6895);
623 etiss_coverage_count(1, 6906);
624 return (etiss_int64)((res >> 64ULL));
625 etiss_coverage_count(4, 6905, 6902, 6900, 6903);
626 } // block
627 }
628 
629 etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y)
630 {
631 etiss_coverage_count(1, 238);
632 { // block
633 etiss_coverage_count(1, 6924);
634 etiss_int128 res = (etiss_int128)(x) * (etiss_uint128)(y);
635 etiss_coverage_count(6, 6916, 6915, 6911, 6909, 6914, 6912);
636 etiss_coverage_count(1, 6923);
637 return (etiss_int64)((res >> 64ULL));
638 etiss_coverage_count(4, 6922, 6919, 6917, 6920);
639 } // block
640 }
641 
642 etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y)
643 {
644 etiss_coverage_count(1, 239);
645 { // block
646 etiss_coverage_count(1, 6941);
647 etiss_uint128 res = (etiss_uint128)(x) * (etiss_uint128)(y);
648 etiss_coverage_count(6, 6933, 6932, 6928, 6926, 6931, 6929);
649 etiss_coverage_count(1, 6940);
650 return (etiss_uint64)((res >> 64ULL));
651 etiss_coverage_count(4, 6939, 6936, 6934, 6937);
652 } // block
653 }
RV64IMACFD_sstatus_mask
etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: RV64IMACFDFuncs.c:43
RV64IMACFD_set_field
etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
Definition: RV64IMACFDFuncs.c:240
RV64IMACFD_translate_exc_code
void RV64IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
Definition: RV64IMACFDFuncs.c:427
RV64IMACFD_mulhu
etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y)
Definition: RV64IMACFDFuncs.c:642
RV64IMACFD_csr_read
etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr)
Definition: RV64IMACFDFuncs.c:102
RV64IMACFD_calc_irq_mcause
etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: RV64IMACFDFuncs.c:488
RV64IMACFD_mstatus_mask
etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: RV64IMACFDFuncs.c:89
RV64IMACFD_csr_write
void RV64IMACFD_csr_write(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
Definition: RV64IMACFDFuncs.c:183
RV64IMACFD_get_field
etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
Definition: RV64IMACFDFuncs.c:222
RV64IMACFD_extension_enabled
etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int8 extension)
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
Definition: RV64IMACFDFuncs.c:9
RV64IMACFD_check_irq
void RV64IMACFD_check_irq(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: RV64IMACFDFuncs.c:600
RV64IMACFD_mulhsu
etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y)
Definition: RV64IMACFDFuncs.c:629
RV64IMACFD_mulh
etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y)
Definition: RV64IMACFDFuncs.c:616
RV64IMACFD_ctz
etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val)
Definition: RV64IMACFDFuncs.c:251
RV64IMACFD_raise
void RV64IMACFD_raise(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
Definition: RV64IMACFDFuncs.c:337
RV64IMACFD_get_rm
etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint8 rm)
Definition: RV64IMACFDFuncs.c:20
s
__device__ __2f16 float bool s
Definition: __clang_hip_libdevice_declares.h:298
etiss_coverage_count
#define etiss_coverage_count(...)
Definition: Coverage.h:12
etiss_get_instret
etiss_uint64 etiss_get_instret(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: CSRCounters.cpp:26
etiss_get_time
etiss_uint64 etiss_get_time()
Definition: CSRCounters.cpp:18
etiss_get_cycles
etiss_uint64 etiss_get_cycles(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: CSRCounters.cpp:13
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_int64
int64_t etiss_int64
Definition: types.h:95
etiss_int8
int8_t etiss_int8
Definition: types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition: CPU.h:92
ETISS_CPU::exception
etiss_uint32 exception
Definition: CPU.h:111
ETISS_CPU::return_pending
etiss_uint32 return_pending
Definition: CPU.h:112
ETISS_System
memory access and time synchronization functions.
Definition: System.h:78
RV64IMACFD
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
Definition: RV64IMACFD.h:16
Generated on Thu Oct 24 2024 09:40:11 for ETISS 0.8.0 by doxygen 1.9.1