ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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etiss
include
etiss
ClassDefs.h
Go to the documentation of this file.
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// This file is part of ETISS. It is licensed under the BSD 3-Clause License; you may not use this file except in
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// compliance with the License. You should have received a copy of the license along with this project. If not, see the
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// LICENSE file.
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#ifndef ETISS_INCLUDE_CLASSDEFS_H_
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#define ETISS_INCLUDE_CLASSDEFS_H_
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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struct
ETISS_CPU
;
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struct
ETISS_System
;
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#ifdef __cplusplus
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}
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#endif
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namespace
etiss
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{
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class
BlockLink;
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class
CodeBlock;
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class
CodePart;
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class
CodeSet;
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class
CoroutinePlugin;
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class
CPUArch;
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class
CPUCore;
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class
CPUArchRegListenerInterface;
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class
InterruptEnable;
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class
InterruptListenerPlugin;
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class
InterruptVector;
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class
JIT;
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class
LibraryInterface;
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class
MemSegment;
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class
SimpleMemSystem;
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class
Plugin;
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class
RegisterDevicePlugin;
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class
System;
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class
SimpleSystem;
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class
SystemWrapperPlugin;
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class
Translation;
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class
TranslationPlugin;
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class
VirtualStruct;
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namespace
instr
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{
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class
Buffer
;
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class
BitArray
;
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class
BitArrayRange
;
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class
Instruction
;
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class
InstructionClass
;
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class
InstructionContext
;
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class
InstructionDefinition
;
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class
InstructionGroup
;
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class
InstructionSet
;
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class
OPCode
;
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class
ModedInstructionSet
;
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class
VariableInstructionSet
;
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}
// namespace instr
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namespace
interfaces
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{
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class
Delegate
;
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}
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namespace
mm
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{
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class
DMMUWrapper
;
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class
MMU
;
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}
// namespace mm
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namespace
fault
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{
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class
Trigger
;
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class
Fault
;
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class
Action
;
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}
// namespace fault
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namespace
plugin
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{
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namespace
gdb
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{
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class
Connection
;
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class
PacketProtocol
;
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}
// namespace gdb
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}
// namespace plugin
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}
// namespace etiss
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#endif
etiss::fault::Action
Definition
Action.h:46
etiss::fault::Fault
Definition
Fault.h:46
etiss::fault::Trigger
Definition
Trigger.h:50
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition
Instruction.h:162
etiss::instr::BitArray
stores a bit vector
Definition
Instruction.h:114
etiss::instr::Buffer
Buffer for reading data from memory while instructions are being fetched.
Definition
Instruction.h:46
etiss::instr::InstructionClass
maps to VariableInstructionSet
Definition
Instruction.h:593
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition
Instruction.h:290
etiss::instr::InstructionDefinition
maps to Instruction
Definition
Instruction.h:663
etiss::instr::InstructionGroup
maps to InstructionSet
Definition
Instruction.h:632
etiss::instr::InstructionSet
holds etiss::instr::Instruction instances and handles automatic instruction tree creation.
Definition
Instruction.h:397
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition
Instruction.h:346
etiss::instr::ModedInstructionSet
holds etiss::instr::VariableInstructionSet instances for different modes.
Definition
Instruction.h:517
etiss::instr::OPCode
defines the relevant bits and their value to identify an instruction.
Definition
Instruction.h:225
etiss::instr::VariableInstructionSet
holds etiss::instr::InstructionSet instances with different bit widths.
Definition
Instruction.h:455
etiss::interfaces::Delegate
Definition
Delegate.h:38
etiss::mm::DMMUWrapper
Definition
DMMUWrapper.h:28
etiss::mm::MMU
Definition
MMU.h:38
etiss::plugin::gdb::Connection
interface for gdb connections.
Definition
GDBConnection.h:64
etiss::plugin::gdb::PacketProtocol
implements gdb's packet protocol
Definition
GDBConnection.h:38
etiss
forwards: include/jit/*
Definition
Benchmark.h:17
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition
CPU.h:51
ETISS_System
memory access and time synchronization functions.
Definition
System.h:40
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