ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD.h
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1 
7 #ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
8 #define ETISS_RV64IMACFDArch_RV64IMACFD_H_
9 #include <stdio.h>
10 #include "etiss/jit/CPU.h"
11 
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15 #pragma pack(push, 1)
16 struct RV64IMACFD {
17  ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
60  etiss_uint64 *CSR[4096];
64 };
65 
66 #pragma pack(pop) // undo changes
67 typedef struct RV64IMACFD RV64IMACFD; // convenient use of X instead of struct X in generated C code
68 #ifdef __cplusplus
69 } // extern "C"
70 #endif
71 #endif
uint64_t etiss_uint64
Definition: types.h:96
uint8_t etiss_uint8
Definition: types.h:87
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
Generated on Wed, 08 May 2024 17:36:07 +0200.
Definition: RV64IMACFD.h:16
etiss_uint64 S8
Definition: RV64IMACFD.h:42
etiss_uint64 A6
Definition: RV64IMACFD.h:34
ETISS_CPU cpu
Definition: RV64IMACFD.h:17
etiss_uint64 A1
Definition: RV64IMACFD.h:29
etiss_uint64 T1
Definition: RV64IMACFD.h:24
etiss_uint64 S2
Definition: RV64IMACFD.h:36
etiss_uint64 FENCE[8]
Definition: RV64IMACFD.h:52
etiss_uint64 RES_ADDR
Definition: RV64IMACFD.h:63
etiss_uint64 A5
Definition: RV64IMACFD.h:33
etiss_uint64 MIP
Definition: RV64IMACFD.h:59
etiss_uint64 ins_X[32]
Definition: RV64IMACFD.h:51
etiss_uint8 PRIV
Definition: RV64IMACFD.h:54
etiss_uint64 S1
Definition: RV64IMACFD.h:27
etiss_uint64 MIE
Definition: RV64IMACFD.h:58
etiss_uint64 ins_CSR[4096]
Definition: RV64IMACFD.h:61
etiss_uint64 T2
Definition: RV64IMACFD.h:25
etiss_uint64 S10
Definition: RV64IMACFD.h:44
etiss_uint64 * CSR[4096]
Definition: RV64IMACFD.h:60
etiss_uint64 RA
Definition: RV64IMACFD.h:19
etiss_uint64 S6
Definition: RV64IMACFD.h:40
etiss_uint64 S0
Definition: RV64IMACFD.h:26
etiss_uint64 S4
Definition: RV64IMACFD.h:38
etiss_uint64 T3
Definition: RV64IMACFD.h:46
etiss_uint64 FCSR
Definition: RV64IMACFD.h:56
etiss_uint64 S7
Definition: RV64IMACFD.h:41
etiss_uint64 SP
Definition: RV64IMACFD.h:20
etiss_uint64 A7
Definition: RV64IMACFD.h:35
etiss_uint64 * X[32]
Definition: RV64IMACFD.h:50
etiss_uint64 S3
Definition: RV64IMACFD.h:37
etiss_uint64 A0
Definition: RV64IMACFD.h:28
etiss_uint64 T6
Definition: RV64IMACFD.h:49
etiss_uint64 ZERO
Definition: RV64IMACFD.h:18
etiss_uint8 RES[8]
Definition: RV64IMACFD.h:53
etiss_uint64 TP
Definition: RV64IMACFD.h:22
etiss_uint64 T0
Definition: RV64IMACFD.h:23
etiss_uint64 A3
Definition: RV64IMACFD.h:31
etiss_uint64 S5
Definition: RV64IMACFD.h:39
etiss_uint64 F[32]
Definition: RV64IMACFD.h:62
etiss_uint64 A2
Definition: RV64IMACFD.h:30
etiss_uint64 T5
Definition: RV64IMACFD.h:48
etiss_uint64 GP
Definition: RV64IMACFD.h:21
etiss_uint64 MSTATUS
Definition: RV64IMACFD.h:57
etiss_uint64 A4
Definition: RV64IMACFD.h:32
etiss_uint64 S9
Definition: RV64IMACFD.h:43
etiss_uint64 S11
Definition: RV64IMACFD.h:45
etiss_uint64 T4
Definition: RV64IMACFD.h:47
etiss_uint64 DPC
Definition: RV64IMACFD.h:55