ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
include
jit
Arch
RV64IMACFD
RV64IMACFD.h
Go to the documentation of this file.
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#ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
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#define ETISS_RV64IMACFDArch_RV64IMACFD_H_
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#include <stdio.h>
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#include "etiss/jit/CPU.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#pragma pack(push, 1)
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struct
RV64IMACFD
{
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ETISS_CPU
cpu
;
// original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
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etiss_uint64
ZERO
;
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etiss_uint64
RA
;
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etiss_uint64
SP
;
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etiss_uint64
GP
;
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etiss_uint64
TP
;
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etiss_uint64
T0
;
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etiss_uint64
T1
;
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etiss_uint64
T2
;
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etiss_uint64
S0
;
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etiss_uint64
S1
;
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etiss_uint64
A0
;
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etiss_uint64
A1
;
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etiss_uint64
A2
;
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etiss_uint64
A3
;
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etiss_uint64
A4
;
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etiss_uint64
A5
;
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etiss_uint64
A6
;
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etiss_uint64
A7
;
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etiss_uint64
S2
;
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etiss_uint64
S3
;
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etiss_uint64
S4
;
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etiss_uint64
S5
;
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etiss_uint64
S6
;
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etiss_uint64
S7
;
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etiss_uint64
S8
;
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etiss_uint64
S9
;
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etiss_uint64
S10
;
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etiss_uint64
S11
;
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etiss_uint64
T3
;
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etiss_uint64
T4
;
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etiss_uint64
T5
;
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etiss_uint64
T6
;
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etiss_uint64
*
X
[32];
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etiss_uint64
ins_X
[32];
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etiss_uint64
FENCE
[8];
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etiss_uint8
RES
[8];
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etiss_uint8
PRIV
;
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etiss_uint64
DPC
;
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etiss_uint64
FCSR
;
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etiss_uint64
MSTATUS
;
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etiss_uint64
MIE
;
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etiss_uint64
MIP
;
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etiss_uint64
*
CSR
[4096];
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etiss_uint64
ins_CSR
[4096];
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etiss_uint64
F
[32];
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etiss_uint64
RES_ADDR
;
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};
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#pragma pack(pop)
// undo changes
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typedef
struct
RV64IMACFD
RV64IMACFD
;
// convenient use of X instead of struct X in generated C code
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#ifdef __cplusplus
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}
// extern "C"
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#endif
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#endif
etiss_uint64
uint64_t etiss_uint64
Definition:
types.h:96
etiss_uint8
uint8_t etiss_uint8
Definition:
types.h:87
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition:
CPU.h:89
RV64IMACFD
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
Definition:
RV64IMACFD.h:16
RV64IMACFD::S8
etiss_uint64 S8
Definition:
RV64IMACFD.h:42
RV64IMACFD::A6
etiss_uint64 A6
Definition:
RV64IMACFD.h:34
RV64IMACFD::cpu
ETISS_CPU cpu
Definition:
RV64IMACFD.h:17
RV64IMACFD::A1
etiss_uint64 A1
Definition:
RV64IMACFD.h:29
RV64IMACFD::T1
etiss_uint64 T1
Definition:
RV64IMACFD.h:24
RV64IMACFD::S2
etiss_uint64 S2
Definition:
RV64IMACFD.h:36
RV64IMACFD::FENCE
etiss_uint64 FENCE[8]
Definition:
RV64IMACFD.h:52
RV64IMACFD::RES_ADDR
etiss_uint64 RES_ADDR
Definition:
RV64IMACFD.h:63
RV64IMACFD::A5
etiss_uint64 A5
Definition:
RV64IMACFD.h:33
RV64IMACFD::MIP
etiss_uint64 MIP
Definition:
RV64IMACFD.h:59
RV64IMACFD::ins_X
etiss_uint64 ins_X[32]
Definition:
RV64IMACFD.h:51
RV64IMACFD::PRIV
etiss_uint8 PRIV
Definition:
RV64IMACFD.h:54
RV64IMACFD::S1
etiss_uint64 S1
Definition:
RV64IMACFD.h:27
RV64IMACFD::MIE
etiss_uint64 MIE
Definition:
RV64IMACFD.h:58
RV64IMACFD::ins_CSR
etiss_uint64 ins_CSR[4096]
Definition:
RV64IMACFD.h:61
RV64IMACFD::T2
etiss_uint64 T2
Definition:
RV64IMACFD.h:25
RV64IMACFD::S10
etiss_uint64 S10
Definition:
RV64IMACFD.h:44
RV64IMACFD::CSR
etiss_uint64 * CSR[4096]
Definition:
RV64IMACFD.h:60
RV64IMACFD::RA
etiss_uint64 RA
Definition:
RV64IMACFD.h:19
RV64IMACFD::S6
etiss_uint64 S6
Definition:
RV64IMACFD.h:40
RV64IMACFD::S0
etiss_uint64 S0
Definition:
RV64IMACFD.h:26
RV64IMACFD::S4
etiss_uint64 S4
Definition:
RV64IMACFD.h:38
RV64IMACFD::T3
etiss_uint64 T3
Definition:
RV64IMACFD.h:46
RV64IMACFD::FCSR
etiss_uint64 FCSR
Definition:
RV64IMACFD.h:56
RV64IMACFD::S7
etiss_uint64 S7
Definition:
RV64IMACFD.h:41
RV64IMACFD::SP
etiss_uint64 SP
Definition:
RV64IMACFD.h:20
RV64IMACFD::A7
etiss_uint64 A7
Definition:
RV64IMACFD.h:35
RV64IMACFD::X
etiss_uint64 * X[32]
Definition:
RV64IMACFD.h:50
RV64IMACFD::S3
etiss_uint64 S3
Definition:
RV64IMACFD.h:37
RV64IMACFD::A0
etiss_uint64 A0
Definition:
RV64IMACFD.h:28
RV64IMACFD::T6
etiss_uint64 T6
Definition:
RV64IMACFD.h:49
RV64IMACFD::ZERO
etiss_uint64 ZERO
Definition:
RV64IMACFD.h:18
RV64IMACFD::RES
etiss_uint8 RES[8]
Definition:
RV64IMACFD.h:53
RV64IMACFD::TP
etiss_uint64 TP
Definition:
RV64IMACFD.h:22
RV64IMACFD::T0
etiss_uint64 T0
Definition:
RV64IMACFD.h:23
RV64IMACFD::A3
etiss_uint64 A3
Definition:
RV64IMACFD.h:31
RV64IMACFD::S5
etiss_uint64 S5
Definition:
RV64IMACFD.h:39
RV64IMACFD::F
etiss_uint64 F[32]
Definition:
RV64IMACFD.h:62
RV64IMACFD::A2
etiss_uint64 A2
Definition:
RV64IMACFD.h:30
RV64IMACFD::T5
etiss_uint64 T5
Definition:
RV64IMACFD.h:48
RV64IMACFD::GP
etiss_uint64 GP
Definition:
RV64IMACFD.h:21
RV64IMACFD::MSTATUS
etiss_uint64 MSTATUS
Definition:
RV64IMACFD.h:57
RV64IMACFD::A4
etiss_uint64 A4
Definition:
RV64IMACFD.h:32
RV64IMACFD::S9
etiss_uint64 S9
Definition:
RV64IMACFD.h:43
RV64IMACFD::S11
etiss_uint64 S11
Definition:
RV64IMACFD.h:45
RV64IMACFD::T4
etiss_uint64 T4
Definition:
RV64IMACFD.h:47
RV64IMACFD::DPC
etiss_uint64 DPC
Definition:
RV64IMACFD.h:55
Generated on Thu Oct 24 2024 09:39:43 for ETISS 0.8.0 by
1.9.1