ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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include
jit
Arch
RV64IMACFD
RV64IMACFD.h
Go to the documentation of this file.
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#ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
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#define ETISS_RV64IMACFDArch_RV64IMACFD_H_
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#include <stdio.h>
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#include "etiss/jit/CPU.h"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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#pragma pack(push, 1)
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struct
RV64IMACFD
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{
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ETISS_CPU
cpu
;
// original cpu struct must be defined as the first field of the new structure.
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// This allows to cast X * to ETISS_CPU * and vice versa
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etiss_uint64
ZERO
;
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etiss_uint64
RA
;
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etiss_uint64
SP
;
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etiss_uint64
GP
;
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etiss_uint64
TP
;
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etiss_uint64
T0
;
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etiss_uint64
T1
;
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etiss_uint64
T2
;
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etiss_uint64
S0
;
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etiss_uint64
S1
;
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etiss_uint64
A0
;
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etiss_uint64
A1
;
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etiss_uint64
A2
;
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etiss_uint64
A3
;
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etiss_uint64
A4
;
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etiss_uint64
A5
;
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etiss_uint64
A6
;
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etiss_uint64
A7
;
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etiss_uint64
S2
;
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etiss_uint64
S3
;
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etiss_uint64
S4
;
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etiss_uint64
S5
;
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etiss_uint64
S6
;
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etiss_uint64
S7
;
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etiss_uint64
S8
;
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etiss_uint64
S9
;
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etiss_uint64
S10
;
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etiss_uint64
S11
;
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etiss_uint64
T3
;
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etiss_uint64
T4
;
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etiss_uint64
T5
;
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etiss_uint64
T6
;
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etiss_uint64
*
X
[32];
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etiss_uint64
ins_X
[32];
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etiss_uint64
FENCE
[8];
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etiss_uint8
RES
[8];
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etiss_uint8
PRIV
;
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etiss_uint64
DPC
;
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etiss_uint64
FCSR
;
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etiss_uint64
FFLAGS
;
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etiss_uint64
FRM
;
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etiss_uint64
MSTATUS
;
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etiss_uint64
MIE
;
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etiss_uint64
MIP
;
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etiss_uint64
CYCLE
;
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etiss_uint64
CYCLEH
;
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etiss_uint64
MCYCLE
;
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etiss_uint64
MCYCLEH
;
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etiss_uint64
TIME
;
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etiss_uint64
TIMEH
;
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etiss_uint64
INSTRET
;
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etiss_uint64
INSTRETH
;
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etiss_uint64
MINSTRET
;
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etiss_uint64
MINSTRETH
;
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etiss_uint64
MVENDORID
;
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etiss_uint64
MARCHID
;
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etiss_uint64
MIMPID
;
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etiss_uint64
MHARTID
;
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etiss_uint64
MISA
;
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etiss_uint64
MEDELEG
;
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etiss_uint64
MIDELEG
;
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etiss_uint64
MTVEC
;
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etiss_uint64
MCOUNTEREN
;
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etiss_uint64
MSCRATCH
;
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etiss_uint64
MEPC
;
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etiss_uint64
MCAUSE
;
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etiss_uint64
MTVAL
;
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etiss_uint64
*
CSR
[4096];
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etiss_uint64
ins_CSR
[4096];
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etiss_uint64
FT0
;
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etiss_uint64
FT1
;
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etiss_uint64
FT2
;
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etiss_uint64
FT3
;
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etiss_uint64
FT4
;
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etiss_uint64
FT5
;
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etiss_uint64
FT6
;
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etiss_uint64
FT7
;
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etiss_uint64
FS0
;
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etiss_uint64
FS1
;
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etiss_uint64
FA0
;
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etiss_uint64
FA1
;
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etiss_uint64
FA2
;
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etiss_uint64
FA3
;
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etiss_uint64
FA4
;
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etiss_uint64
FA5
;
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etiss_uint64
FA6
;
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etiss_uint64
FA7
;
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etiss_uint64
FS2
;
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etiss_uint64
FS3
;
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etiss_uint64
FS4
;
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etiss_uint64
FS5
;
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etiss_uint64
FS6
;
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etiss_uint64
FS7
;
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etiss_uint64
FS8
;
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etiss_uint64
FS9
;
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etiss_uint64
FS10
;
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etiss_uint64
FS11
;
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etiss_uint64
FT8
;
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etiss_uint64
FT9
;
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etiss_uint64
FT10
;
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etiss_uint64
FT11
;
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etiss_uint64
*
F
[32];
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etiss_uint64
ins_F
[32];
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etiss_uint64
RES_ADDR
;
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};
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#pragma pack(pop)
// undo changes
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// convenient use of X instead of struct X in generated C code
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typedef
struct
RV64IMACFD
RV64IMACFD
;
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#ifdef __cplusplus
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}
// extern "C"
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#endif
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#endif
etiss_uint64
uint64_t etiss_uint64
Definition
types.h:58
etiss_uint8
uint8_t etiss_uint8
Definition
types.h:49
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition
CPU.h:51
RV64IMACFD
Generated on Mon, 15 Jun 2026 06:54:17 +0000.
Definition
RV64IMACFD.h:18
RV64IMACFD::CYCLE
etiss_uint64 CYCLE
Definition
RV64IMACFD.h:65
RV64IMACFD::FRM
etiss_uint64 FRM
Definition
RV64IMACFD.h:61
RV64IMACFD::S8
etiss_uint64 S8
Definition
RV64IMACFD.h:45
RV64IMACFD::FA6
etiss_uint64 FA6
Definition
RV64IMACFD.h:106
RV64IMACFD::A6
etiss_uint64 A6
Definition
RV64IMACFD.h:37
RV64IMACFD::cpu
ETISS_CPU cpu
Definition
RV64IMACFD.h:19
RV64IMACFD::A1
etiss_uint64 A1
Definition
RV64IMACFD.h:32
RV64IMACFD::FS3
etiss_uint64 FS3
Definition
RV64IMACFD.h:109
RV64IMACFD::MINSTRET
etiss_uint64 MINSTRET
Definition
RV64IMACFD.h:73
RV64IMACFD::T1
etiss_uint64 T1
Definition
RV64IMACFD.h:27
RV64IMACFD::FT3
etiss_uint64 FT3
Definition
RV64IMACFD.h:93
RV64IMACFD::INSTRET
etiss_uint64 INSTRET
Definition
RV64IMACFD.h:71
RV64IMACFD::INSTRETH
etiss_uint64 INSTRETH
Definition
RV64IMACFD.h:72
RV64IMACFD::FS5
etiss_uint64 FS5
Definition
RV64IMACFD.h:111
RV64IMACFD::S2
etiss_uint64 S2
Definition
RV64IMACFD.h:39
RV64IMACFD::MCAUSE
etiss_uint64 MCAUSE
Definition
RV64IMACFD.h:86
RV64IMACFD::F
etiss_uint64 * F[32]
Definition
RV64IMACFD.h:122
RV64IMACFD::FENCE
etiss_uint64 FENCE[8]
Definition
RV64IMACFD.h:55
RV64IMACFD::MINSTRETH
etiss_uint64 MINSTRETH
Definition
RV64IMACFD.h:74
RV64IMACFD::RES_ADDR
etiss_uint64 RES_ADDR
Definition
RV64IMACFD.h:124
RV64IMACFD::MTVEC
etiss_uint64 MTVEC
Definition
RV64IMACFD.h:82
RV64IMACFD::A5
etiss_uint64 A5
Definition
RV64IMACFD.h:36
RV64IMACFD::MIP
etiss_uint64 MIP
Definition
RV64IMACFD.h:64
RV64IMACFD::ins_X
etiss_uint64 ins_X[32]
Definition
RV64IMACFD.h:54
RV64IMACFD::PRIV
etiss_uint8 PRIV
Definition
RV64IMACFD.h:57
RV64IMACFD::S1
etiss_uint64 S1
Definition
RV64IMACFD.h:30
RV64IMACFD::MIE
etiss_uint64 MIE
Definition
RV64IMACFD.h:63
RV64IMACFD::FT0
etiss_uint64 FT0
Definition
RV64IMACFD.h:90
RV64IMACFD::MEPC
etiss_uint64 MEPC
Definition
RV64IMACFD.h:85
RV64IMACFD::MEDELEG
etiss_uint64 MEDELEG
Definition
RV64IMACFD.h:80
RV64IMACFD::ins_CSR
etiss_uint64 ins_CSR[4096]
Definition
RV64IMACFD.h:89
RV64IMACFD::T2
etiss_uint64 T2
Definition
RV64IMACFD.h:28
RV64IMACFD::S10
etiss_uint64 S10
Definition
RV64IMACFD.h:47
RV64IMACFD::MARCHID
etiss_uint64 MARCHID
Definition
RV64IMACFD.h:76
RV64IMACFD::FS1
etiss_uint64 FS1
Definition
RV64IMACFD.h:99
RV64IMACFD::CSR
etiss_uint64 * CSR[4096]
Definition
RV64IMACFD.h:88
RV64IMACFD::RA
etiss_uint64 RA
Definition
RV64IMACFD.h:22
RV64IMACFD::FS8
etiss_uint64 FS8
Definition
RV64IMACFD.h:114
RV64IMACFD::S6
etiss_uint64 S6
Definition
RV64IMACFD.h:43
RV64IMACFD::MVENDORID
etiss_uint64 MVENDORID
Definition
RV64IMACFD.h:75
RV64IMACFD::FA4
etiss_uint64 FA4
Definition
RV64IMACFD.h:104
RV64IMACFD::S0
etiss_uint64 S0
Definition
RV64IMACFD.h:29
RV64IMACFD::S4
etiss_uint64 S4
Definition
RV64IMACFD.h:41
RV64IMACFD::FS0
etiss_uint64 FS0
Definition
RV64IMACFD.h:98
RV64IMACFD::FS7
etiss_uint64 FS7
Definition
RV64IMACFD.h:113
RV64IMACFD::ins_F
etiss_uint64 ins_F[32]
Definition
RV64IMACFD.h:123
RV64IMACFD::MTVAL
etiss_uint64 MTVAL
Definition
RV64IMACFD.h:87
RV64IMACFD::FFLAGS
etiss_uint64 FFLAGS
Definition
RV64IMACFD.h:60
RV64IMACFD::FA7
etiss_uint64 FA7
Definition
RV64IMACFD.h:107
RV64IMACFD::TIME
etiss_uint64 TIME
Definition
RV64IMACFD.h:69
RV64IMACFD::T3
etiss_uint64 T3
Definition
RV64IMACFD.h:49
RV64IMACFD::FT1
etiss_uint64 FT1
Definition
RV64IMACFD.h:91
RV64IMACFD::FS9
etiss_uint64 FS9
Definition
RV64IMACFD.h:115
RV64IMACFD::FT7
etiss_uint64 FT7
Definition
RV64IMACFD.h:97
RV64IMACFD::FS4
etiss_uint64 FS4
Definition
RV64IMACFD.h:110
RV64IMACFD::MIDELEG
etiss_uint64 MIDELEG
Definition
RV64IMACFD.h:81
RV64IMACFD::MCYCLE
etiss_uint64 MCYCLE
Definition
RV64IMACFD.h:67
RV64IMACFD::FCSR
etiss_uint64 FCSR
Definition
RV64IMACFD.h:59
RV64IMACFD::FS10
etiss_uint64 FS10
Definition
RV64IMACFD.h:116
RV64IMACFD::S7
etiss_uint64 S7
Definition
RV64IMACFD.h:44
RV64IMACFD::SP
etiss_uint64 SP
Definition
RV64IMACFD.h:23
RV64IMACFD::A7
etiss_uint64 A7
Definition
RV64IMACFD.h:38
RV64IMACFD::MCOUNTEREN
etiss_uint64 MCOUNTEREN
Definition
RV64IMACFD.h:83
RV64IMACFD::X
etiss_uint64 * X[32]
Definition
RV64IMACFD.h:53
RV64IMACFD::S3
etiss_uint64 S3
Definition
RV64IMACFD.h:40
RV64IMACFD::FT4
etiss_uint64 FT4
Definition
RV64IMACFD.h:94
RV64IMACFD::FS11
etiss_uint64 FS11
Definition
RV64IMACFD.h:117
RV64IMACFD::TIMEH
etiss_uint64 TIMEH
Definition
RV64IMACFD.h:70
RV64IMACFD::A0
etiss_uint64 A0
Definition
RV64IMACFD.h:31
RV64IMACFD::FA3
etiss_uint64 FA3
Definition
RV64IMACFD.h:103
RV64IMACFD::T6
etiss_uint64 T6
Definition
RV64IMACFD.h:52
RV64IMACFD::MCYCLEH
etiss_uint64 MCYCLEH
Definition
RV64IMACFD.h:68
RV64IMACFD::ZERO
etiss_uint64 ZERO
Definition
RV64IMACFD.h:21
RV64IMACFD::CYCLEH
etiss_uint64 CYCLEH
Definition
RV64IMACFD.h:66
RV64IMACFD::RES
etiss_uint8 RES[8]
Definition
RV64IMACFD.h:56
RV64IMACFD::TP
etiss_uint64 TP
Definition
RV64IMACFD.h:25
RV64IMACFD::T0
etiss_uint64 T0
Definition
RV64IMACFD.h:26
RV64IMACFD::MSCRATCH
etiss_uint64 MSCRATCH
Definition
RV64IMACFD.h:84
RV64IMACFD::FS2
etiss_uint64 FS2
Definition
RV64IMACFD.h:108
RV64IMACFD::A3
etiss_uint64 A3
Definition
RV64IMACFD.h:34
RV64IMACFD::FA5
etiss_uint64 FA5
Definition
RV64IMACFD.h:105
RV64IMACFD::S5
etiss_uint64 S5
Definition
RV64IMACFD.h:42
RV64IMACFD::FT10
etiss_uint64 FT10
Definition
RV64IMACFD.h:120
RV64IMACFD::MISA
etiss_uint64 MISA
Definition
RV64IMACFD.h:79
RV64IMACFD::FT8
etiss_uint64 FT8
Definition
RV64IMACFD.h:118
RV64IMACFD::A2
etiss_uint64 A2
Definition
RV64IMACFD.h:33
RV64IMACFD::T5
etiss_uint64 T5
Definition
RV64IMACFD.h:51
RV64IMACFD::FA1
etiss_uint64 FA1
Definition
RV64IMACFD.h:101
RV64IMACFD::GP
etiss_uint64 GP
Definition
RV64IMACFD.h:24
RV64IMACFD::MSTATUS
etiss_uint64 MSTATUS
Definition
RV64IMACFD.h:62
RV64IMACFD::FA0
etiss_uint64 FA0
Definition
RV64IMACFD.h:100
RV64IMACFD::MHARTID
etiss_uint64 MHARTID
Definition
RV64IMACFD.h:78
RV64IMACFD::A4
etiss_uint64 A4
Definition
RV64IMACFD.h:35
RV64IMACFD::FT5
etiss_uint64 FT5
Definition
RV64IMACFD.h:95
RV64IMACFD::S9
etiss_uint64 S9
Definition
RV64IMACFD.h:46
RV64IMACFD::MIMPID
etiss_uint64 MIMPID
Definition
RV64IMACFD.h:77
RV64IMACFD::FT2
etiss_uint64 FT2
Definition
RV64IMACFD.h:92
RV64IMACFD::S11
etiss_uint64 S11
Definition
RV64IMACFD.h:48
RV64IMACFD::FT6
etiss_uint64 FT6
Definition
RV64IMACFD.h:96
RV64IMACFD::FA2
etiss_uint64 FA2
Definition
RV64IMACFD.h:102
RV64IMACFD::FT11
etiss_uint64 FT11
Definition
RV64IMACFD.h:121
RV64IMACFD::T4
etiss_uint64 T4
Definition
RV64IMACFD.h:50
RV64IMACFD::FT9
etiss_uint64 FT9
Definition
RV64IMACFD.h:119
RV64IMACFD::FS6
etiss_uint64 FS6
Definition
RV64IMACFD.h:112
RV64IMACFD::DPC
etiss_uint64 DPC
Definition
RV64IMACFD.h:58
Generated on Wed Jun 17 2026 10:47:33 for ETISS 0.11.2 by
1.9.8