ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFDArch.cpp
Go to the documentation of this file.
1
7/*********************************************************************************************************************************
8
9* Modification guidelines:
10
11 1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized
12 through utility class etiss::VirtualStruct::Field.
13
14 2. Debug mode print out all assignment results. GDB in 8 is prefered.
15
16 3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction,
17 otherwise the emulation can not be ended.
18
19 4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate
20
21 5. If the PC register points to wrong address, please notice that some assembly may cause branch operation
22 implicitly such as "MOV Rd Rn" in ARMv6-M
23
24 6. If a variable is the result of dynamic slicing such as, var_1 = var_2<Hshift-1..Lshift-2>, the size would be
25 calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur
26 when var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit
27 slicing e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to
28 manually correct it.
29
30 7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding
31 interfaces are provided in RV64IMACFDArchSpecificImp.h
32
33 8. RV64IMACFDGDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need.
34
35 *********************************************************************************************************************************/
36
37#include "RV64IMACFDArch.h"
38#include "RV64IMACFDFuncs.h"
39
40#define RV64IMACFD_DEBUG_CALL 0
41using namespace etiss;
42using namespace etiss::instr;
43
44RV64IMACFDArch::RV64IMACFDArch(unsigned int coreno) : CPUArch("RV64IMACFD"), coreno_(coreno)
45{
46 headers_.insert("Arch/RV64IMACFD/RV64IMACFD.h");
47}
48
49const std::set<std::string> &RV64IMACFDArch::getListenerSupportedRegisters()
50{
51 return listenerSupportedRegisters_;
52}
53
54ETISS_CPU *RV64IMACFDArch::newCPU()
55{
56 ETISS_CPU *ret = (ETISS_CPU *)new RV64IMACFD();
57 resetCPU(ret, 0);
58 return ret;
59}
60
61void RV64IMACFDArch::resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
62{
63 memset(cpu, 0, sizeof(RV64IMACFD));
64 RV64IMACFD *rv64imacfdcpu = (RV64IMACFD *)cpu;
65
66 if (startpointer)
67 cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1);
68 else
69 cpu->instructionPointer = 0x0; // reference to manual
70 cpu->nextPc = cpu->instructionPointer;
71 cpu->mode = 1;
72 cpu->cpuTime_ps = 0;
73 cpu->cpuCycleTime_ps = 31250;
74
75 for (int i = 0; i < 4096; ++i)
76 {
77 rv64imacfdcpu->ins_CSR[i] = 0;
78 rv64imacfdcpu->CSR[i] = &rv64imacfdcpu->ins_CSR[i];
79 }
80 for (int i = 0; i < 32; ++i)
81 {
82 rv64imacfdcpu->ins_X[i] = 0;
83 rv64imacfdcpu->X[i] = &rv64imacfdcpu->ins_X[i];
84 }
85 for (int i = 0; i < 32; ++i)
86 {
87 rv64imacfdcpu->ins_F[i] = 0;
88 rv64imacfdcpu->F[i] = &rv64imacfdcpu->ins_F[i];
89 }
90
91 for (int i = 0; i < 8; ++i)
92 {
93 rv64imacfdcpu->FENCE[i] = 0;
94 }
95 for (int i = 0; i < 8; ++i)
96 {
97 rv64imacfdcpu->RES[i] = 0;
98 }
99 rv64imacfdcpu->FCSR = 0;
100 rv64imacfdcpu->FFLAGS = 0;
101 rv64imacfdcpu->FRM = 0;
102 rv64imacfdcpu->MSTATUS = 0;
103 rv64imacfdcpu->MIE = 0;
104 rv64imacfdcpu->MIP = 0;
105 rv64imacfdcpu->CYCLE = 0;
106 rv64imacfdcpu->CYCLEH = 0;
107 rv64imacfdcpu->MCYCLE = 0;
108 rv64imacfdcpu->MCYCLEH = 0;
109 rv64imacfdcpu->TIME = 0;
110 rv64imacfdcpu->TIMEH = 0;
111 rv64imacfdcpu->INSTRET = 0;
112 rv64imacfdcpu->INSTRETH = 0;
113 rv64imacfdcpu->MINSTRET = 0;
114 rv64imacfdcpu->MINSTRETH = 0;
115 rv64imacfdcpu->MVENDORID = 0;
116 rv64imacfdcpu->MARCHID = 0;
117 rv64imacfdcpu->MIMPID = 0;
118 rv64imacfdcpu->MHARTID = 0;
119 rv64imacfdcpu->MISA = 0;
120 rv64imacfdcpu->MEDELEG = 0;
121 rv64imacfdcpu->MIDELEG = 0;
122 rv64imacfdcpu->MTVEC = 0;
123 rv64imacfdcpu->MCOUNTEREN = 0;
124 rv64imacfdcpu->MSCRATCH = 0;
125 rv64imacfdcpu->MEPC = 0;
126 rv64imacfdcpu->MCAUSE = 0;
127 rv64imacfdcpu->MTVAL = 0;
128 rv64imacfdcpu->ZERO = 0;
129 rv64imacfdcpu->RA = 0;
130 rv64imacfdcpu->SP = 0;
131 rv64imacfdcpu->GP = 0;
132 rv64imacfdcpu->TP = 0;
133 rv64imacfdcpu->T0 = 0;
134 rv64imacfdcpu->T1 = 0;
135 rv64imacfdcpu->T2 = 0;
136 rv64imacfdcpu->S0 = 0;
137 rv64imacfdcpu->S1 = 0;
138 rv64imacfdcpu->A0 = 0;
139 rv64imacfdcpu->A1 = 0;
140 rv64imacfdcpu->A2 = 0;
141 rv64imacfdcpu->A3 = 0;
142 rv64imacfdcpu->A4 = 0;
143 rv64imacfdcpu->A5 = 0;
144 rv64imacfdcpu->A6 = 0;
145 rv64imacfdcpu->A7 = 0;
146 rv64imacfdcpu->S2 = 0;
147 rv64imacfdcpu->S3 = 0;
148 rv64imacfdcpu->S4 = 0;
149 rv64imacfdcpu->S5 = 0;
150 rv64imacfdcpu->S6 = 0;
151 rv64imacfdcpu->S7 = 0;
152 rv64imacfdcpu->S8 = 0;
153 rv64imacfdcpu->S9 = 0;
154 rv64imacfdcpu->S10 = 0;
155 rv64imacfdcpu->S11 = 0;
156 rv64imacfdcpu->T3 = 0;
157 rv64imacfdcpu->T4 = 0;
158 rv64imacfdcpu->T5 = 0;
159 rv64imacfdcpu->T6 = 0;
160 rv64imacfdcpu->PRIV = 0;
161 rv64imacfdcpu->DPC = 0;
162 rv64imacfdcpu->FT0 = 0;
163 rv64imacfdcpu->FT1 = 0;
164 rv64imacfdcpu->FT2 = 0;
165 rv64imacfdcpu->FT3 = 0;
166 rv64imacfdcpu->FT4 = 0;
167 rv64imacfdcpu->FT5 = 0;
168 rv64imacfdcpu->FT6 = 0;
169 rv64imacfdcpu->FT7 = 0;
170 rv64imacfdcpu->FS0 = 0;
171 rv64imacfdcpu->FS1 = 0;
172 rv64imacfdcpu->FA0 = 0;
173 rv64imacfdcpu->FA1 = 0;
174 rv64imacfdcpu->FA2 = 0;
175 rv64imacfdcpu->FA3 = 0;
176 rv64imacfdcpu->FA4 = 0;
177 rv64imacfdcpu->FA5 = 0;
178 rv64imacfdcpu->FA6 = 0;
179 rv64imacfdcpu->FA7 = 0;
180 rv64imacfdcpu->FS2 = 0;
181 rv64imacfdcpu->FS3 = 0;
182 rv64imacfdcpu->FS4 = 0;
183 rv64imacfdcpu->FS5 = 0;
184 rv64imacfdcpu->FS6 = 0;
185 rv64imacfdcpu->FS7 = 0;
186 rv64imacfdcpu->FS8 = 0;
187 rv64imacfdcpu->FS9 = 0;
188 rv64imacfdcpu->FS10 = 0;
189 rv64imacfdcpu->FS11 = 0;
190 rv64imacfdcpu->FT8 = 0;
191 rv64imacfdcpu->FT9 = 0;
192 rv64imacfdcpu->FT10 = 0;
193 rv64imacfdcpu->FT11 = 0;
194 rv64imacfdcpu->RES_ADDR = 0;
195 rv64imacfdcpu->FCSR = 0;
196 rv64imacfdcpu->FFLAGS = 0;
197 rv64imacfdcpu->FRM = 0;
198 rv64imacfdcpu->MSTATUS = 0;
199 rv64imacfdcpu->MIE = 0;
200 rv64imacfdcpu->MIP = 0;
201 rv64imacfdcpu->CYCLE = 0;
202 rv64imacfdcpu->CYCLEH = 0;
203 rv64imacfdcpu->MCYCLE = 0;
204 rv64imacfdcpu->MCYCLEH = 0;
205 rv64imacfdcpu->TIME = 0;
206 rv64imacfdcpu->TIMEH = 0;
207 rv64imacfdcpu->INSTRET = 0;
208 rv64imacfdcpu->INSTRETH = 0;
209 rv64imacfdcpu->MINSTRET = 0;
210 rv64imacfdcpu->MINSTRETH = 0;
211 rv64imacfdcpu->MVENDORID = 0;
212 rv64imacfdcpu->MARCHID = 0;
213 rv64imacfdcpu->MIMPID = 0;
214 rv64imacfdcpu->MHARTID = 0;
215 rv64imacfdcpu->MISA = 0;
216 rv64imacfdcpu->MEDELEG = 0;
217 rv64imacfdcpu->MIDELEG = 0;
218 rv64imacfdcpu->MTVEC = 0;
219 rv64imacfdcpu->MCOUNTEREN = 0;
220 rv64imacfdcpu->MSCRATCH = 0;
221 rv64imacfdcpu->MEPC = 0;
222 rv64imacfdcpu->MCAUSE = 0;
223 rv64imacfdcpu->MTVAL = 0;
224 rv64imacfdcpu->ZERO = 0;
225 rv64imacfdcpu->RA = 0;
226 rv64imacfdcpu->SP = 0;
227 rv64imacfdcpu->GP = 0;
228 rv64imacfdcpu->TP = 0;
229 rv64imacfdcpu->T0 = 0;
230 rv64imacfdcpu->T1 = 0;
231 rv64imacfdcpu->T2 = 0;
232 rv64imacfdcpu->S0 = 0;
233 rv64imacfdcpu->S1 = 0;
234 rv64imacfdcpu->A0 = 0;
235 rv64imacfdcpu->A1 = 0;
236 rv64imacfdcpu->A2 = 0;
237 rv64imacfdcpu->A3 = 0;
238 rv64imacfdcpu->A4 = 0;
239 rv64imacfdcpu->A5 = 0;
240 rv64imacfdcpu->A6 = 0;
241 rv64imacfdcpu->A7 = 0;
242 rv64imacfdcpu->S2 = 0;
243 rv64imacfdcpu->S3 = 0;
244 rv64imacfdcpu->S4 = 0;
245 rv64imacfdcpu->S5 = 0;
246 rv64imacfdcpu->S6 = 0;
247 rv64imacfdcpu->S7 = 0;
248 rv64imacfdcpu->S8 = 0;
249 rv64imacfdcpu->S9 = 0;
250 rv64imacfdcpu->S10 = 0;
251 rv64imacfdcpu->S11 = 0;
252 rv64imacfdcpu->T3 = 0;
253 rv64imacfdcpu->T4 = 0;
254 rv64imacfdcpu->T5 = 0;
255 rv64imacfdcpu->T6 = 0;
256 rv64imacfdcpu->FT0 = 0;
257 rv64imacfdcpu->FT1 = 0;
258 rv64imacfdcpu->FT2 = 0;
259 rv64imacfdcpu->FT3 = 0;
260 rv64imacfdcpu->FT4 = 0;
261 rv64imacfdcpu->FT5 = 0;
262 rv64imacfdcpu->FT6 = 0;
263 rv64imacfdcpu->FT7 = 0;
264 rv64imacfdcpu->FS0 = 0;
265 rv64imacfdcpu->FS1 = 0;
266 rv64imacfdcpu->FA0 = 0;
267 rv64imacfdcpu->FA1 = 0;
268 rv64imacfdcpu->FA2 = 0;
269 rv64imacfdcpu->FA3 = 0;
270 rv64imacfdcpu->FA4 = 0;
271 rv64imacfdcpu->FA5 = 0;
272 rv64imacfdcpu->FA6 = 0;
273 rv64imacfdcpu->FA7 = 0;
274 rv64imacfdcpu->FS2 = 0;
275 rv64imacfdcpu->FS3 = 0;
276 rv64imacfdcpu->FS4 = 0;
277 rv64imacfdcpu->FS5 = 0;
278 rv64imacfdcpu->FS6 = 0;
279 rv64imacfdcpu->FS7 = 0;
280 rv64imacfdcpu->FS8 = 0;
281 rv64imacfdcpu->FS9 = 0;
282 rv64imacfdcpu->FS10 = 0;
283 rv64imacfdcpu->FS11 = 0;
284 rv64imacfdcpu->FT8 = 0;
285 rv64imacfdcpu->FT9 = 0;
286 rv64imacfdcpu->FT10 = 0;
287 rv64imacfdcpu->FT11 = 0;
288
289 rv64imacfdcpu->CSR[3] = &rv64imacfdcpu->FCSR;
290 rv64imacfdcpu->CSR[1] = &rv64imacfdcpu->FFLAGS;
291 rv64imacfdcpu->CSR[2] = &rv64imacfdcpu->FRM;
292 rv64imacfdcpu->CSR[768] = &rv64imacfdcpu->MSTATUS;
293 rv64imacfdcpu->CSR[772] = &rv64imacfdcpu->MIE;
294 rv64imacfdcpu->CSR[836] = &rv64imacfdcpu->MIP;
295 rv64imacfdcpu->CSR[3072] = &rv64imacfdcpu->CYCLE;
296 rv64imacfdcpu->CSR[3200] = &rv64imacfdcpu->CYCLEH;
297 rv64imacfdcpu->CSR[2816] = &rv64imacfdcpu->MCYCLE;
298 rv64imacfdcpu->CSR[2944] = &rv64imacfdcpu->MCYCLEH;
299 rv64imacfdcpu->CSR[3073] = &rv64imacfdcpu->TIME;
300 rv64imacfdcpu->CSR[3201] = &rv64imacfdcpu->TIMEH;
301 rv64imacfdcpu->CSR[3074] = &rv64imacfdcpu->INSTRET;
302 rv64imacfdcpu->CSR[3202] = &rv64imacfdcpu->INSTRETH;
303 rv64imacfdcpu->CSR[2818] = &rv64imacfdcpu->MINSTRET;
304 rv64imacfdcpu->CSR[2946] = &rv64imacfdcpu->MINSTRETH;
305 rv64imacfdcpu->CSR[3857] = &rv64imacfdcpu->MVENDORID;
306 rv64imacfdcpu->CSR[3858] = &rv64imacfdcpu->MARCHID;
307 rv64imacfdcpu->CSR[3859] = &rv64imacfdcpu->MIMPID;
308 rv64imacfdcpu->CSR[3860] = &rv64imacfdcpu->MHARTID;
309 rv64imacfdcpu->CSR[769] = &rv64imacfdcpu->MISA;
310 rv64imacfdcpu->CSR[770] = &rv64imacfdcpu->MEDELEG;
311 rv64imacfdcpu->CSR[771] = &rv64imacfdcpu->MIDELEG;
312 rv64imacfdcpu->CSR[773] = &rv64imacfdcpu->MTVEC;
313 rv64imacfdcpu->CSR[774] = &rv64imacfdcpu->MCOUNTEREN;
314 rv64imacfdcpu->CSR[832] = &rv64imacfdcpu->MSCRATCH;
315 rv64imacfdcpu->CSR[833] = &rv64imacfdcpu->MEPC;
316 rv64imacfdcpu->CSR[834] = &rv64imacfdcpu->MCAUSE;
317 rv64imacfdcpu->CSR[835] = &rv64imacfdcpu->MTVAL;
318 rv64imacfdcpu->X[0] = &rv64imacfdcpu->ZERO;
319 rv64imacfdcpu->X[1] = &rv64imacfdcpu->RA;
320 rv64imacfdcpu->X[2] = &rv64imacfdcpu->SP;
321 rv64imacfdcpu->X[3] = &rv64imacfdcpu->GP;
322 rv64imacfdcpu->X[4] = &rv64imacfdcpu->TP;
323 rv64imacfdcpu->X[5] = &rv64imacfdcpu->T0;
324 rv64imacfdcpu->X[6] = &rv64imacfdcpu->T1;
325 rv64imacfdcpu->X[7] = &rv64imacfdcpu->T2;
326 rv64imacfdcpu->X[8] = &rv64imacfdcpu->S0;
327 rv64imacfdcpu->X[9] = &rv64imacfdcpu->S1;
328 rv64imacfdcpu->X[10] = &rv64imacfdcpu->A0;
329 rv64imacfdcpu->X[11] = &rv64imacfdcpu->A1;
330 rv64imacfdcpu->X[12] = &rv64imacfdcpu->A2;
331 rv64imacfdcpu->X[13] = &rv64imacfdcpu->A3;
332 rv64imacfdcpu->X[14] = &rv64imacfdcpu->A4;
333 rv64imacfdcpu->X[15] = &rv64imacfdcpu->A5;
334 rv64imacfdcpu->X[16] = &rv64imacfdcpu->A6;
335 rv64imacfdcpu->X[17] = &rv64imacfdcpu->A7;
336 rv64imacfdcpu->X[18] = &rv64imacfdcpu->S2;
337 rv64imacfdcpu->X[19] = &rv64imacfdcpu->S3;
338 rv64imacfdcpu->X[20] = &rv64imacfdcpu->S4;
339 rv64imacfdcpu->X[21] = &rv64imacfdcpu->S5;
340 rv64imacfdcpu->X[22] = &rv64imacfdcpu->S6;
341 rv64imacfdcpu->X[23] = &rv64imacfdcpu->S7;
342 rv64imacfdcpu->X[24] = &rv64imacfdcpu->S8;
343 rv64imacfdcpu->X[25] = &rv64imacfdcpu->S9;
344 rv64imacfdcpu->X[26] = &rv64imacfdcpu->S10;
345 rv64imacfdcpu->X[27] = &rv64imacfdcpu->S11;
346 rv64imacfdcpu->X[28] = &rv64imacfdcpu->T3;
347 rv64imacfdcpu->X[29] = &rv64imacfdcpu->T4;
348 rv64imacfdcpu->X[30] = &rv64imacfdcpu->T5;
349 rv64imacfdcpu->X[31] = &rv64imacfdcpu->T6;
350 rv64imacfdcpu->F[0] = &rv64imacfdcpu->FT0;
351 rv64imacfdcpu->F[1] = &rv64imacfdcpu->FT1;
352 rv64imacfdcpu->F[2] = &rv64imacfdcpu->FT2;
353 rv64imacfdcpu->F[3] = &rv64imacfdcpu->FT3;
354 rv64imacfdcpu->F[4] = &rv64imacfdcpu->FT4;
355 rv64imacfdcpu->F[5] = &rv64imacfdcpu->FT5;
356 rv64imacfdcpu->F[6] = &rv64imacfdcpu->FT6;
357 rv64imacfdcpu->F[7] = &rv64imacfdcpu->FT7;
358 rv64imacfdcpu->F[8] = &rv64imacfdcpu->FS0;
359 rv64imacfdcpu->F[9] = &rv64imacfdcpu->FS1;
360 rv64imacfdcpu->F[10] = &rv64imacfdcpu->FA0;
361 rv64imacfdcpu->F[11] = &rv64imacfdcpu->FA1;
362 rv64imacfdcpu->F[12] = &rv64imacfdcpu->FA2;
363 rv64imacfdcpu->F[13] = &rv64imacfdcpu->FA3;
364 rv64imacfdcpu->F[14] = &rv64imacfdcpu->FA4;
365 rv64imacfdcpu->F[15] = &rv64imacfdcpu->FA5;
366 rv64imacfdcpu->F[16] = &rv64imacfdcpu->FA6;
367 rv64imacfdcpu->F[17] = &rv64imacfdcpu->FA7;
368 rv64imacfdcpu->F[18] = &rv64imacfdcpu->FS2;
369 rv64imacfdcpu->F[19] = &rv64imacfdcpu->FS3;
370 rv64imacfdcpu->F[20] = &rv64imacfdcpu->FS4;
371 rv64imacfdcpu->F[21] = &rv64imacfdcpu->FS5;
372 rv64imacfdcpu->F[22] = &rv64imacfdcpu->FS6;
373 rv64imacfdcpu->F[23] = &rv64imacfdcpu->FS7;
374 rv64imacfdcpu->F[24] = &rv64imacfdcpu->FS8;
375 rv64imacfdcpu->F[25] = &rv64imacfdcpu->FS9;
376 rv64imacfdcpu->F[26] = &rv64imacfdcpu->FS10;
377 rv64imacfdcpu->F[27] = &rv64imacfdcpu->FS11;
378 rv64imacfdcpu->F[28] = &rv64imacfdcpu->FT8;
379 rv64imacfdcpu->F[29] = &rv64imacfdcpu->FT9;
380 rv64imacfdcpu->F[30] = &rv64imacfdcpu->FT10;
381 rv64imacfdcpu->F[31] = &rv64imacfdcpu->FT11;
382
383 *rv64imacfdcpu->CSR[0] = 11ULL;
384 *rv64imacfdcpu->CSR[256] = 11ULL;
385 *rv64imacfdcpu->CSR[768] = 11ULL;
386 *rv64imacfdcpu->CSR[769] = 9223372036856090925ULL;
387 *rv64imacfdcpu->CSR[3088] = 3ULL;
388 *rv64imacfdcpu->CSR[772] = 4294966203ULL;
389 *rv64imacfdcpu->CSR[260] = 4294964019ULL;
390 *rv64imacfdcpu->CSR[4] = 4294963473ULL;
391 rv64imacfdcpu->PRIV = 3ULL;
392 rv64imacfdcpu->DPC = 0LL;
393 rv64imacfdcpu->RES_ADDR = -1LL;
394}
395
396void RV64IMACFDArch::deleteCPU(ETISS_CPU *cpu)
397{
398 delete (RV64IMACFD *)cpu;
399}
400
404unsigned RV64IMACFDArch::getMaximumInstructionSizeInBytes()
405{
406 return 8;
407}
408
412unsigned RV64IMACFDArch::getInstructionSizeInBytes()
413{
414 return 2;
415}
416
420const std::set<std::string> &RV64IMACFDArch::getHeaders() const
421{
422 return headers_;
423}
424
425void RV64IMACFDArch::initCodeBlock(etiss::CodeBlock &cb) const
426{
427 cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n");
428 cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n");
429 cb.functionglobalCode().insert("cpu->exception = 0;\n");
430 cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
431 cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
432}
433
438
439// clang-format off
440const char * const reg_name[] =
441{
442 "X0",
443 "X1",
444 "X2",
445 "X3",
446 "X4",
447 "X5",
448 "X6",
449 "X7",
450 "X8",
451 "X9",
452 "X10",
453 "X11",
454 "X12",
455 "X13",
456 "X14",
457 "X15",
458 "X16",
459 "X17",
460 "X18",
461 "X19",
462 "X20",
463 "X21",
464 "X22",
465 "X23",
466 "X24",
467 "X25",
468 "X26",
469 "X27",
470 "X28",
471 "X29",
472 "X30",
473 "X31",
474 "F0",
475 "F1",
476 "F2",
477 "F3",
478 "F4",
479 "F5",
480 "F6",
481 "F7",
482 "F8",
483 "F9",
484 "F10",
485 "F11",
486 "F12",
487 "F13",
488 "F14",
489 "F15",
490 "F16",
491 "F17",
492 "F18",
493 "F19",
494 "F20",
495 "F21",
496 "F22",
497 "F23",
498 "F24",
499 "F25",
500 "F26",
501 "F27",
502 "F28",
503 "F29",
504 "F30",
505 "F31",
506};
507// clang-format on
508
509etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16);
510etiss::instr::InstructionClass ISA16_RV64IMACFDClass(1, "ISA16_RV64IMACFD", 16, ISA16_RV64IMACFD);
511etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32);
512etiss::instr::InstructionClass ISA32_RV64IMACFDClass(1, "ISA32_RV64IMACFD", 32, ISA32_RV64IMACFD);
513
514etiss::instr::InstructionCollection RV64IMACFDISA("RV64IMACFDISA", ISA16_RV64IMACFDClass, ISA32_RV64IMACFDClass);
reg_name
const char *const reg_name[]
Generated on Tue, 11 Aug 2026 12:31:38 +0000.
Definition RV64IMACFDArch.cpp:440
ISA16_RV64IMACFDClass
etiss::instr::InstructionClass ISA16_RV64IMACFDClass(1, "ISA16_RV64IMACFD", 16, ISA16_RV64IMACFD)
RV64IMACFDISA
etiss::instr::InstructionCollection RV64IMACFDISA("RV64IMACFDISA", ISA16_RV64IMACFDClass, ISA32_RV64IMACFDClass)
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
ISA32_RV64IMACFDClass
etiss::instr::InstructionClass ISA32_RV64IMACFDClass(1, "ISA32_RV64IMACFD", 32, ISA32_RV64IMACFD)
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
memset
__DEVICE__ void * memset(void *__a, int __b, size_t __c)
Definition __clang_cuda_device_functions.h:1480
RV64IMACFDArch::listenerSupportedRegisters_
std::set< std::string > listenerSupportedRegisters_
Definition RV64IMACFDArch.h:118
RV64IMACFDArch::deleteCPU
virtual void deleteCPU(ETISS_CPU *)
delete cpu structure
Definition RV64IMACFDArch.cpp:396
RV64IMACFDArch::getInstructionSizeInBytes
virtual unsigned getInstructionSizeInBytes()
Definition RV64IMACFDArch.cpp:412
RV64IMACFDArch::getMaximumInstructionSizeInBytes
virtual unsigned getMaximumInstructionSizeInBytes()
Definition RV64IMACFDArch.cpp:404
RV64IMACFDArch::gdbcore_
RV64IMACFDGDBCore gdbcore_
Definition RV64IMACFDArch.h:120
RV64IMACFDArch::RV64IMACFDArch
RV64IMACFDArch(unsigned int)
Definition RV64IMACFDArch.cpp:44
RV64IMACFDArch::getHeaders
virtual const std::set< std::string > & getHeaders() const
required headers (RV64IMACFD.h)
Definition RV64IMACFDArch.cpp:420
RV64IMACFDArch::newCPU
virtual ETISS_CPU * newCPU()
allocate new cpu structure
Definition RV64IMACFDArch.cpp:54
RV64IMACFDArch::resetCPU
virtual void resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
reset cpu (structure)
Definition RV64IMACFDArch.cpp:61
RV64IMACFDArch::initCodeBlock
virtual void initCodeBlock(etiss::CodeBlock &cb) const
called before instructions are translated for the code block
Definition RV64IMACFDArch.cpp:425
RV64IMACFDArch::getGDBCore
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
get the GDBcore for RV64IMACFD architecture
Definition RV64IMACFDArch.cpp:434
RV64IMACFDArch::headers_
std::set< std::string > headers_
Definition RV64IMACFDArch.h:119
RV64IMACFDArch::getListenerSupportedRegisters
virtual const std::set< std::string > & getListenerSupportedRegisters()
Definition RV64IMACFDArch.cpp:49
etiss::CPUArch
the interface to translate instructions of and processor architecture
Definition CPUArch.h:116
etiss::CodeBlock
A list of CodeSets.
Definition CodePart.h:532
etiss::CodeBlock::functionglobalCode
std::set< std::string > & functionglobalCode()
Definition CodePart.h:567
etiss::CodeBlock::fileglobalCode
std::set< std::string > & fileglobalCode()
Definition CodePart.h:566
etiss::instr::InstructionClass
maps to VariableInstructionSet
Definition Instruction.h:593
etiss::instr::InstructionCollection
maps to ModedInstructionSet
Definition Instruction.h:560
etiss::instr::InstructionGroup
maps to InstructionSet
Definition Instruction.h:632
etiss::plugin::gdb::GDBCore
provides to architecture dependent registers as defined by gdb
Definition GDBCore.h:39
etiss
forwards: include/jit/*
Definition Benchmark.h:17
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition CPU.h:54
ETISS_CPU::cpuCycleTime_ps
etiss_uint64 cpuCycleTime_ps
frequency of the cpu. use to allign e.g. memory delays
Definition CPU.h:67
ETISS_CPU::cpuTime_ps
etiss_uint64 cpuTime_ps
simulation time of cpu
Definition CPU.h:59
ETISS_CPU::nextPc
etiss_uint64 nextPc
Definition CPU.h:57
ETISS_CPU::mode
etiss_uint32 mode
instruction set mode of the processor
Definition CPU.h:71
RV64IMACFD
Generated on Tue, 11 Aug 2026 12:31:35 +0000.
Definition RV64IMACFD.h:17
RV64IMACFD::CYCLE
etiss_uint64 CYCLE
Definition RV64IMACFD.h:99
RV64IMACFD::FRM
etiss_uint64 FRM
Definition RV64IMACFD.h:95
RV64IMACFD::S8
etiss_uint64 S8
Definition RV64IMACFD.h:44
RV64IMACFD::FA6
etiss_uint64 FA6
Definition RV64IMACFD.h:72
RV64IMACFD::A6
etiss_uint64 A6
Definition RV64IMACFD.h:36
RV64IMACFD::A1
etiss_uint64 A1
Definition RV64IMACFD.h:31
RV64IMACFD::FS3
etiss_uint64 FS3
Definition RV64IMACFD.h:75
RV64IMACFD::MINSTRET
etiss_uint64 MINSTRET
Definition RV64IMACFD.h:107
RV64IMACFD::T1
etiss_uint64 T1
Definition RV64IMACFD.h:26
RV64IMACFD::FT3
etiss_uint64 FT3
Definition RV64IMACFD.h:59
RV64IMACFD::INSTRET
etiss_uint64 INSTRET
Definition RV64IMACFD.h:105
RV64IMACFD::INSTRETH
etiss_uint64 INSTRETH
Definition RV64IMACFD.h:106
RV64IMACFD::FS5
etiss_uint64 FS5
Definition RV64IMACFD.h:77
RV64IMACFD::S2
etiss_uint64 S2
Definition RV64IMACFD.h:38
RV64IMACFD::MCAUSE
etiss_uint64 MCAUSE
Definition RV64IMACFD.h:120
RV64IMACFD::F
etiss_uint64 * F[32]
Definition RV64IMACFD.h:88
RV64IMACFD::FENCE
etiss_uint64 FENCE[8]
Definition RV64IMACFD.h:91
RV64IMACFD::MINSTRETH
etiss_uint64 MINSTRETH
Definition RV64IMACFD.h:108
RV64IMACFD::RES_ADDR
etiss_uint64 RES_ADDR
Definition RV64IMACFD.h:90
RV64IMACFD::MTVEC
etiss_uint64 MTVEC
Definition RV64IMACFD.h:116
RV64IMACFD::A5
etiss_uint64 A5
Definition RV64IMACFD.h:35
RV64IMACFD::MIP
etiss_uint64 MIP
Definition RV64IMACFD.h:98
RV64IMACFD::ins_X
etiss_uint64 ins_X[32]
Definition RV64IMACFD.h:53
RV64IMACFD::PRIV
etiss_uint8 PRIV
Definition RV64IMACFD.h:54
RV64IMACFD::S1
etiss_uint64 S1
Definition RV64IMACFD.h:29
RV64IMACFD::MIE
etiss_uint64 MIE
Definition RV64IMACFD.h:97
RV64IMACFD::FT0
etiss_uint64 FT0
Definition RV64IMACFD.h:56
RV64IMACFD::MEPC
etiss_uint64 MEPC
Definition RV64IMACFD.h:119
RV64IMACFD::MEDELEG
etiss_uint64 MEDELEG
Definition RV64IMACFD.h:114
RV64IMACFD::ins_CSR
etiss_uint64 ins_CSR[4096]
Definition RV64IMACFD.h:123
RV64IMACFD::T2
etiss_uint64 T2
Definition RV64IMACFD.h:27
RV64IMACFD::S10
etiss_uint64 S10
Definition RV64IMACFD.h:46
RV64IMACFD::MARCHID
etiss_uint64 MARCHID
Definition RV64IMACFD.h:110
RV64IMACFD::FS1
etiss_uint64 FS1
Definition RV64IMACFD.h:65
RV64IMACFD::CSR
etiss_uint64 * CSR[4096]
Definition RV64IMACFD.h:122
RV64IMACFD::RA
etiss_uint64 RA
Definition RV64IMACFD.h:21
RV64IMACFD::FS8
etiss_uint64 FS8
Definition RV64IMACFD.h:80
RV64IMACFD::S6
etiss_uint64 S6
Definition RV64IMACFD.h:42
RV64IMACFD::MVENDORID
etiss_uint64 MVENDORID
Definition RV64IMACFD.h:109
RV64IMACFD::FA4
etiss_uint64 FA4
Definition RV64IMACFD.h:70
RV64IMACFD::S0
etiss_uint64 S0
Definition RV64IMACFD.h:28
RV64IMACFD::S4
etiss_uint64 S4
Definition RV64IMACFD.h:40
RV64IMACFD::FS0
etiss_uint64 FS0
Definition RV64IMACFD.h:64
RV64IMACFD::FS7
etiss_uint64 FS7
Definition RV64IMACFD.h:79
RV64IMACFD::ins_F
etiss_uint64 ins_F[32]
Definition RV64IMACFD.h:89
RV64IMACFD::RES
etiss_int8 RES[8]
Definition RV64IMACFD.h:92
RV64IMACFD::MTVAL
etiss_uint64 MTVAL
Definition RV64IMACFD.h:121
RV64IMACFD::FFLAGS
etiss_uint64 FFLAGS
Definition RV64IMACFD.h:94
RV64IMACFD::FA7
etiss_uint64 FA7
Definition RV64IMACFD.h:73
RV64IMACFD::TIME
etiss_uint64 TIME
Definition RV64IMACFD.h:103
RV64IMACFD::T3
etiss_uint64 T3
Definition RV64IMACFD.h:48
RV64IMACFD::FT1
etiss_uint64 FT1
Definition RV64IMACFD.h:57
RV64IMACFD::FS9
etiss_uint64 FS9
Definition RV64IMACFD.h:81
RV64IMACFD::FT7
etiss_uint64 FT7
Definition RV64IMACFD.h:63
RV64IMACFD::FS4
etiss_uint64 FS4
Definition RV64IMACFD.h:76
RV64IMACFD::MIDELEG
etiss_uint64 MIDELEG
Definition RV64IMACFD.h:115
RV64IMACFD::MCYCLE
etiss_uint64 MCYCLE
Definition RV64IMACFD.h:101
RV64IMACFD::FCSR
etiss_uint64 FCSR
Definition RV64IMACFD.h:93
RV64IMACFD::FS10
etiss_uint64 FS10
Definition RV64IMACFD.h:82
RV64IMACFD::S7
etiss_uint64 S7
Definition RV64IMACFD.h:43
RV64IMACFD::SP
etiss_uint64 SP
Definition RV64IMACFD.h:22
RV64IMACFD::A7
etiss_uint64 A7
Definition RV64IMACFD.h:37
RV64IMACFD::MCOUNTEREN
etiss_uint64 MCOUNTEREN
Definition RV64IMACFD.h:117
RV64IMACFD::X
etiss_uint64 * X[32]
Definition RV64IMACFD.h:52
RV64IMACFD::S3
etiss_uint64 S3
Definition RV64IMACFD.h:39
RV64IMACFD::FT4
etiss_uint64 FT4
Definition RV64IMACFD.h:60
RV64IMACFD::FS11
etiss_uint64 FS11
Definition RV64IMACFD.h:83
RV64IMACFD::TIMEH
etiss_uint64 TIMEH
Definition RV64IMACFD.h:104
RV64IMACFD::A0
etiss_uint64 A0
Definition RV64IMACFD.h:30
RV64IMACFD::FA3
etiss_uint64 FA3
Definition RV64IMACFD.h:69
RV64IMACFD::T6
etiss_uint64 T6
Definition RV64IMACFD.h:51
RV64IMACFD::MCYCLEH
etiss_uint64 MCYCLEH
Definition RV64IMACFD.h:102
RV64IMACFD::ZERO
etiss_uint64 ZERO
Definition RV64IMACFD.h:20
RV64IMACFD::CYCLEH
etiss_uint64 CYCLEH
Definition RV64IMACFD.h:100
RV64IMACFD::TP
etiss_uint64 TP
Definition RV64IMACFD.h:24
RV64IMACFD::T0
etiss_uint64 T0
Definition RV64IMACFD.h:25
RV64IMACFD::MSCRATCH
etiss_uint64 MSCRATCH
Definition RV64IMACFD.h:118
RV64IMACFD::FS2
etiss_uint64 FS2
Definition RV64IMACFD.h:74
RV64IMACFD::A3
etiss_uint64 A3
Definition RV64IMACFD.h:33
RV64IMACFD::FA5
etiss_uint64 FA5
Definition RV64IMACFD.h:71
RV64IMACFD::S5
etiss_uint64 S5
Definition RV64IMACFD.h:41
RV64IMACFD::FT10
etiss_uint64 FT10
Definition RV64IMACFD.h:86
RV64IMACFD::MISA
etiss_uint64 MISA
Definition RV64IMACFD.h:113
RV64IMACFD::FT8
etiss_uint64 FT8
Definition RV64IMACFD.h:84
RV64IMACFD::A2
etiss_uint64 A2
Definition RV64IMACFD.h:32
RV64IMACFD::T5
etiss_uint64 T5
Definition RV64IMACFD.h:50
RV64IMACFD::FA1
etiss_uint64 FA1
Definition RV64IMACFD.h:67
RV64IMACFD::GP
etiss_uint64 GP
Definition RV64IMACFD.h:23
RV64IMACFD::MSTATUS
etiss_uint64 MSTATUS
Definition RV64IMACFD.h:96
RV64IMACFD::FA0
etiss_uint64 FA0
Definition RV64IMACFD.h:66
RV64IMACFD::MHARTID
etiss_uint64 MHARTID
Definition RV64IMACFD.h:112
RV64IMACFD::A4
etiss_uint64 A4
Definition RV64IMACFD.h:34
RV64IMACFD::FT5
etiss_uint64 FT5
Definition RV64IMACFD.h:61
RV64IMACFD::S9
etiss_uint64 S9
Definition RV64IMACFD.h:45
RV64IMACFD::MIMPID
etiss_uint64 MIMPID
Definition RV64IMACFD.h:111
RV64IMACFD::FT2
etiss_uint64 FT2
Definition RV64IMACFD.h:58
RV64IMACFD::S11
etiss_uint64 S11
Definition RV64IMACFD.h:47
RV64IMACFD::FT6
etiss_uint64 FT6
Definition RV64IMACFD.h:62
RV64IMACFD::FA2
etiss_uint64 FA2
Definition RV64IMACFD.h:68
RV64IMACFD::FT11
etiss_uint64 FT11
Definition RV64IMACFD.h:87
RV64IMACFD::T4
etiss_uint64 T4
Definition RV64IMACFD.h:49
RV64IMACFD::FT9
etiss_uint64 FT9
Definition RV64IMACFD.h:85
RV64IMACFD::FS6
etiss_uint64 FS6
Definition RV64IMACFD.h:78
RV64IMACFD::DPC
etiss_uint64 DPC
Definition RV64IMACFD.h:55
Generated on Wed Aug 12 2026 10:22:56 for ETISS 0.11.2 by doxygen 1.9.8