ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFDArch.h
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1 
7 #ifndef ETISS_RV64IMACFDArch_RV64IMACFDArch_H_
8 #define ETISS_RV64IMACFDArch_RV64IMACFDArch_H_
9 
10 #include "etiss/CPUArch.h"
11 #include "etiss/Instruction.h"
12 #include "etiss/InterruptVector.h"
13 #include "etiss/InterruptEnable.h"
14 #include "RV64IMACFD.h"
15 #include "RV64IMACFDGDBCore.h"
16 
17 #include <map>
18 
19 extern const char * const reg_name[];
20 
25 
27 
29 
30 public:
31  RV64IMACFDArch(unsigned int);
32 
33  virtual const std::set<std::string> & getListenerSupportedRegisters();
34 
35 
36  virtual ETISS_CPU * newCPU();
37  virtual void resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer);
38  virtual void deleteCPU(ETISS_CPU *);
39 
45  virtual std::shared_ptr<etiss::VirtualStruct> getVirtualStruct(ETISS_CPU * cpu);
46 
50  virtual unsigned getMaximumInstructionSizeInBytes();
51 
55  virtual unsigned getInstructionSizeInBytes();
56 
60  virtual const std::set<std::string> & getHeaders() const;
61 
69 
75  virtual void initInstrSet(etiss::instr::ModedInstructionSet & ) const;
76  virtual void initCodeBlock(etiss::CodeBlock & cb) const;
77 
84  virtual void compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const ;
85 
92  virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
95 
102 
103 private:
104  std::set<std::string> listenerSupportedRegisters_;
105  std::set<std::string> headers_;
107  unsigned int coreno_;
108 };
109 #endif
etiss_int32 int32
Definition: 386-GCC.h:81
etiss_uint64 uint64
Definition: 386-GCC.h:82
contains neccesary interfaces for instruction translation.
contains container classes to store instruction definitions + translation functions and build a trans...
defines a general interface to set interrupt bits
const char *const reg_name[]
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss::instr::InstructionCollection RV64IMACFDISA
etiss::instr::InstructionGroup ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD
etiss::instr::InstructionClass ISA16_RV64IMACFDClass
etiss::instr::InstructionClass ISA32_RV64IMACFDClass
virtual void compensateEndianess(ETISS_CPU *cpu, etiss::instr::BitArray &ba) const
Target architecture may have inconsistent endianess.
virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU *cpu)
This function will be called automatically in order to handling architecure dependent exceptions such...
virtual void initInstrSet(etiss::instr::ModedInstructionSet &) const
This function is called during CPUArch initialization.
std::set< std::string > listenerSupportedRegisters_
virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU *cpu)
If interrupt handling is expected, vector table could be provided to support interrupt triggering.
virtual void deleteCPU(ETISS_CPU *)
delete cpu structure
virtual void deleteInterruptEnable(etiss::InterruptEnable *en, ETISS_CPU *cpu)
virtual unsigned getInstructionSizeInBytes()
virtual unsigned getMaximumInstructionSizeInBytes()
RV64IMACFDGDBCore gdbcore_
unsigned int coreno_
RV64IMACFDArch(unsigned int)
virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu)
delete an allocated interrupt vector object
virtual std::shared_ptr< etiss::VirtualStruct > getVirtualStruct(ETISS_CPU *cpu)
get the VirtualStruct of the core to mitigate register access
virtual const std::set< std::string > & getHeaders() const
required headers (RV64IMACFD.h)
virtual ETISS_CPU * newCPU()
allocate new cpu structure
virtual void resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
reset cpu (structure)
virtual etiss::InterruptEnable * createInterruptEnable(ETISS_CPU *cpu)
virtual void initCodeBlock(etiss::CodeBlock &cb) const
called before instructions are translated for the code block
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
get the GDBcore for RV64IMACFD architecture
std::set< std::string > headers_
virtual const std::set< std::string > & getListenerSupportedRegisters()
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
the interface to translate instructions of and processor architecture
Definition: CPUArch.h:162
A list of CodeSets.
Definition: CodePart.h:570
interface to set interrupt bits
stores a bit vector
Definition: Instruction.h:161
maps to VariableInstructionSet
Definition: Instruction.h:638
maps to ModedInstructionSet
Definition: Instruction.h:605
maps to InstructionSet
Definition: Instruction.h:677
holds etiss::instr::VariableInstructionSet instances for different modes.
Definition: Instruction.h:562
provides to architecture dependent registers as defined by gdb
Definition: GDBCore.h:77
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89