ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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GDBCore.h
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1
55#ifndef ETISS_INCLUDE_GDB_GDBCORE_H_
56#define ETISS_INCLUDE_GDB_GDBCORE_H_
57
58#include "etiss/jit/CPU.h"
59#include <string>
60
61namespace etiss
62{
63
64namespace plugin
65{
66
67namespace gdb
68{
69
77{
78 public:
79 virtual ~GDBCore();
84 virtual std::string mapRegister(unsigned index);
89 virtual unsigned mapRegister(std::string name);
93 virtual unsigned mappedRegisterCount();
97 virtual bool isLittleEndian();
104 virtual etiss::uint64 getInstructionPointer(ETISS_CPU *cpu);
105
106 public:
107 static const unsigned INVALIDMAPPING = (unsigned)-1;
108};
109
110} // namespace gdb
111
112} // namespace plugin
113} // namespace etiss
114
115#endif
provides to architecture dependent registers as defined by gdb
Definition GDBCore.h:77
static const unsigned INVALIDMAPPING
Definition GDBCore.h:107
virtual etiss::uint64 getInstructionPointer(ETISS_CPU *cpu)
allows to calculate the index of the instruction to be executed for breakpoint checks.
Definition GDBCore.cpp:74
virtual unsigned mappedRegisterCount()
returns the number of registers in the gdb defined register list
Definition GDBCore.cpp:66
virtual std::string mapRegister(unsigned index)
the returned string identifies the register at the given index as defined by gdb.
Definition GDBCore.cpp:58
virtual bool isLittleEndian()
returns true if the values are expected to be little endian
Definition GDBCore.cpp:70
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:89