ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFDGDBCore.h
Go to the documentation of this file.
1
10#ifndef ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_
11#define ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_
12
14#include <sstream>
15
34{
35 public:
36 std::string mapRegister(unsigned index)
37 {
38 if (index < 32)
39 {
40 std::stringstream ss;
41 ss << "X" << index;
42 return ss.str();
43 }
44 switch (index)
45 {
46 case 32:
47 return "instructionPointer";
48 /**************************************************************************
49 * Further register should be added here to send data over gdbserver *
50 **************************************************************************/
51 }
52 return "";
53 }
54
55 unsigned mapRegister(std::string name) { return INVALIDMAPPING; }
56
58 {
59 // Modify according to sent register number
60 return 33;
61 }
62
63 etiss::uint64 getInstructionPointer(ETISS_CPU *cpu) { return cpu->instructionPointer; }
64
66 {
67 // Modify according to RV64IMACFD manual
68 return true;
69 }
70};
71
72#endif
Generated on Mon, 10 Nov 2025 11:27:24 +0000.
bool isLittleEndian()
returns true if the values are expected to be little endian
unsigned mappedRegisterCount()
returns the number of registers in the gdb defined register list
unsigned mapRegister(std::string name)
returns the index of the given register name in the list of registers as defined by gdb.
std::string mapRegister(unsigned index)
the returned string identifies the register at the given index as defined by gdb.
etiss::uint64 getInstructionPointer(ETISS_CPU *cpu)
allows to calculate the index of the instruction to be executed for breakpoint checks.
provides to architecture dependent registers as defined by gdb
Definition GDBCore.h:39
static const unsigned INVALIDMAPPING
Definition GDBCore.h:69
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
etiss_uint64 instructionPointer
pointer to next instruction.
Definition CPU.h:54