7 #ifndef ETISS_RV32IMACFDArch_RV32IMACFDArch_H_
8 #define ETISS_RV32IMACFDArch_RV32IMACFDArch_H_
19 extern const char *
const reg_name[];
60 virtual const std::set<std::string> &
getHeaders()
const;
contains neccesary interfaces for instruction translation.
contains container classes to store instruction definitions + translation functions and build a trans...
defines a general interface to set interrupt bits
etiss::instr::InstructionGroup ISA32_RV32IMACFD
const char *const reg_name[]
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss::instr::InstructionClass ISA16_RV32IMACFDClass
etiss::instr::InstructionGroup ISA16_RV32IMACFD
etiss::instr::InstructionClass ISA32_RV32IMACFDClass
etiss::instr::InstructionCollection RV32IMACFDISA
virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu)
delete an allocated interrupt vector object
virtual void deleteInterruptEnable(etiss::InterruptEnable *en, ETISS_CPU *cpu)
RV32IMACFDArch(unsigned int)
virtual void deleteCPU(ETISS_CPU *)
delete cpu structure
virtual ETISS_CPU * newCPU()
allocate new cpu structure
RV32IMACFDGDBCore gdbcore_
virtual void initInstrSet(etiss::instr::ModedInstructionSet &) const
This function is called during CPUArch initialization.
virtual const std::set< std::string > & getHeaders() const
required headers (RV32IMACFD.h)
virtual unsigned getMaximumInstructionSizeInBytes()
virtual etiss::InterruptEnable * createInterruptEnable(ETISS_CPU *cpu)
virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU *cpu)
If interrupt handling is expected, vector table could be provided to support interrupt triggering.
virtual std::shared_ptr< etiss::VirtualStruct > getVirtualStruct(ETISS_CPU *cpu)
get the VirtualStruct of the core to mitigate register access
std::set< std::string > listenerSupportedRegisters_
virtual unsigned getInstructionSizeInBytes()
virtual void compensateEndianess(ETISS_CPU *cpu, etiss::instr::BitArray &ba) const
Target architecture may have inconsistent endianess.
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
get the GDBcore for RV32IMACFD architecture
virtual const std::set< std::string > & getListenerSupportedRegisters()
virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU *cpu)
This function will be called automatically in order to handling architecure dependent exceptions such...
virtual void initCodeBlock(etiss::CodeBlock &cb) const
called before instructions are translated for the code block
virtual void resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
reset cpu (structure)
std::set< std::string > headers_
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
the interface to translate instructions of and processor architecture
interface to set interrupt bits
maps to VariableInstructionSet
maps to ModedInstructionSet
holds etiss::instr::VariableInstructionSet instances for different modes.
provides to architecture dependent registers as defined by gdb
basic cpu state structure needed for execution of any cpu architecture.