Generated on Thu, 24 Oct 2024 10:16:12 +0200. More...
#include <RV32IMACFDGDBCore.h>
Public Member Functions | |
| std::string | mapRegister (unsigned index) |
| the returned string identifies the register at the given index as defined by gdb. More... | |
| unsigned | mapRegister (std::string name) |
| returns the index of the given register name in the list of registers as defined by gdb. More... | |
| unsigned | mappedRegisterCount () |
| returns the number of registers in the gdb defined register list More... | |
| etiss::uint64 | getInstructionPointer (ETISS_CPU *cpu) |
| allows to calculate the index of the instruction to be executed for breakpoint checks. More... | |
| bool | isLittleEndian () |
| returns true if the values are expected to be little endian More... | |
 Public Member Functions inherited from etiss::plugin::gdb::GDBCore | |
| virtual | ~GDBCore () |
Additional Inherited Members | |
| Static Public Attributes inherited from etiss::plugin::gdb::GDBCore | |
| static const unsigned | INVALIDMAPPING = (unsigned)-1 |
Detailed Description
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
This file contains the GDBCore adapter for the RV32IMACFD core architecture.
WARNING: This file contains user-added code, be mindful when overwriting this with generated code!
This class is the brige between RV32IMACFD architecture and gdbserver
Gdbserver integrated in ETISS calls GDBCore to read/write registers via virtualStrruct The index in mapRegister() should strictly follow the RV32IMACFD gdb tool defined register order. Because gdbserver will send raw register data sequentially in strict order over RSP ->TCP/IP ->RSP protocal
Check the order with gdb command: info all-registers which lists all registers supported and its order.
By default only general purpose register and instruction pointer are supported. Further Special Function Register/Control and Status Register could be added manually. Meanwhile virtualStruct in RV32IMACFDArch.cpp should be modified as well as well
Definition at line 33 of file RV32IMACFDGDBCore.h.
Member Function Documentation
◆ getInstructionPointer()
|
inlinevirtual |
allows to calculate the index of the instruction to be executed for breakpoint checks.
returns cpu->instructionPointer by default.
the OR1K architecture uses this to account for an invalid instruction pointer in case of a delay slot instruction
Reimplemented from etiss::plugin::gdb::GDBCore.
Definition at line 60 of file RV32IMACFDGDBCore.h.
References ETISS_CPU::instructionPointer.
◆ isLittleEndian()
|
inlinevirtual |
returns true if the values are expected to be little endian
Reimplemented from etiss::plugin::gdb::GDBCore.
Definition at line 64 of file RV32IMACFDGDBCore.h.
◆ mappedRegisterCount()
|
inlinevirtual |
returns the number of registers in the gdb defined register list
Reimplemented from etiss::plugin::gdb::GDBCore.
Definition at line 55 of file RV32IMACFDGDBCore.h.
◆ mapRegister() [1/2]
|
inlinevirtual |
returns the index of the given register name in the list of registers as defined by gdb.
max return INVALIDMAPPING if the passed name is not in the list
Reimplemented from etiss::plugin::gdb::GDBCore.
Definition at line 51 of file RV32IMACFDGDBCore.h.
References etiss::plugin::gdb::GDBCore::INVALIDMAPPING.
◆ mapRegister() [2/2]
|
inlinevirtual |
the returned string identifies the register at the given index as defined by gdb.
the returned string must match the get/setRegisterXX() functions of etiss::CPUArch
Reimplemented from etiss::plugin::gdb::GDBCore.
Definition at line 35 of file RV32IMACFDGDBCore.h.
The documentation for this class was generated from the following file:
- /home/runner/work/etiss/etiss/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
