ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFDGDBCore.h
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1 
10 #ifndef ETISS_RV32IMACFDArch_RV32IMACFDGDBCORE_H_
11 #define ETISS_RV32IMACFDArch_RV32IMACFDGDBCORE_H_
12 
14 #include <sstream>
15 
34 public:
35  std::string mapRegister(unsigned index){
36  if (index < 32){
37  std::stringstream ss;
38  ss << "X" << index;
39  return ss.str();
40  }
41  switch (index){
42  case 32:
43  return "instructionPointer";
44  /**************************************************************************
45  * Further register should be added here to send data over gdbserver *
46  ***************************************************************************/
47  }
48  return "";
49  }
50 
51  unsigned mapRegister(std::string name){
52  return INVALIDMAPPING;
53  }
54 
55  unsigned mappedRegisterCount(){
56  // Modify according to sent register number
57  return 33;
58  }
59 
61  return cpu->instructionPointer;
62  }
63 
65  // Modify according to RV32IMACFD manual
66  return true;
67  }
68 };
69 
70 #endif
etiss_uint64 uint64
Definition: 386-GCC.h:82
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
unsigned mapRegister(std::string name)
returns the index of the given register name in the list of registers as defined by gdb.
unsigned mappedRegisterCount()
returns the number of registers in the gdb defined register list
etiss::uint64 getInstructionPointer(ETISS_CPU *cpu)
allows to calculate the index of the instruction to be executed for breakpoint checks.
bool isLittleEndian()
returns true if the values are expected to be little endian
std::string mapRegister(unsigned index)
the returned string identifies the register at the given index as defined by gdb.
provides to architecture dependent registers as defined by gdb
Definition: GDBCore.h:77
static const unsigned INVALIDMAPPING
Definition: GDBCore.h:107
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
etiss_uint64 instructionPointer
pointer to next instruction.
Definition: CPU.h:92