65 std::string cfgPar =
"";
66 cfgPar =
etiss::cfg().
get<std::string>(
"jit.external_headers",
";");
67 etiss::cfg().
set<std::string>(
"jit.external_headers", cfgPar +
"etiss/jit/libsoftfloat.h");
69 cfgPar =
etiss::cfg().
get<std::string>(
"jit.external_libs",
";");
70 etiss::cfg().
set<std::string>(
"jit.external_libs", cfgPar +
"softfloat");
72 cfgPar =
etiss::cfg().
get<std::string>(
"jit.external_header_paths",
";");
73 etiss::cfg().
set<std::string>(
"jit.external_header_paths", cfgPar +
"/etiss/jit");
75 cfgPar =
etiss::cfg().
get<std::string>(
"jit.external_lib_paths",
";");
76 etiss::cfg().
set<std::string>(
"jit.external_lib_paths", cfgPar +
"/etiss/jit");
88 std::cout << iset.
print() << std::endl;
98 using namespace etiss;
112 error_code += R_error_code_0.
read(ba) << 0;
119 cp.
code() = std::string(
"//trap_entry 32\n");
123 cp.
code() +=
"{ // procedure\n";
124 cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) +
"ULL);\n";
126 cp.
code() +=
"} // procedure\n";
129 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
136 cp.
code() = std::string(
"//trap_entry 32\n");
139 cp.
code() +=
"return cpu->exception;\n";
159 error_code += R_error_code_0.
read(ba) << 0;
166 cp.
code() = std::string(
"//trap_entry 16\n");
170 cp.
code() +=
"{ // procedure\n";
171 cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) +
"ULL);\n";
173 cp.
code() +=
"} // procedure\n";
176 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
183 cp.
code() = std::string(
"//trap_entry 16\n");
186 cp.
code() +=
"return cpu->exception;\n";
202 else if ((opRd & 0x3f) == 0x1f)
204 else if (((opRd & 0x1f) >= 0x3) && ((opRd & 0x1f) < 0x1f))
206 else if(opRd == 0x7f)
208 else if ((opRd & 0x3) != 0x3)
230 if (((opRd & 0x3) != 0x3) || (opRd == 0))
237 updateRV32IMACFDInstrLength(ic, opRd);
241 if ((((opRd & 0x1f) >= 0x3) || ((opRd & 0x1f) < 0x1f)) || (opRd == 0))
246 else if(opRd == 0x7f)
248 updateRV32IMACFDInstrLength(ic, opRd);
253 updateRV32IMACFDInstrLength(ic, opRd);
257 if (((opRd & 0x3f) == 0x1f) || (opRd == 0))
264 updateRV32IMACFDInstrLength(ic, opRd);
268 if ((opRd == 0x3f) || (opRd == 0))
275 updateRV32IMACFDInstrLength(ic, opRd);
345 std::vector<etiss::uint32 *> vec;
346 std::vector<etiss::uint32 *> mask;
etiss::instr::InstructionCollection RV32IMACFDISA("RV32IMACFDISA", ISA16_RV32IMACFDClass, ISA32_RV32IMACFDClass)
void RV32IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
static __inline__ uint32_t
virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu)
delete an allocated interrupt vector object
virtual void deleteInterruptEnable(etiss::InterruptEnable *en, ETISS_CPU *cpu)
virtual void initInstrSet(etiss::instr::ModedInstructionSet &) const
This function is called during CPUArch initialization.
virtual etiss::InterruptEnable * createInterruptEnable(ETISS_CPU *cpu)
virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU *cpu)
If interrupt handling is expected, vector table could be provided to support interrupt triggering.
virtual std::shared_ptr< etiss::VirtualStruct > getVirtualStruct(ETISS_CPU *cpu)
get the VirtualStruct of the core to mitigate register access
virtual void compensateEndianess(ETISS_CPU *cpu, etiss::instr::BitArray &ba) const
Target architecture may have inconsistent endianess.
virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU *cpu)
This function will be called automatically in order to handling architecure dependent exceptions such...
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
Contains a small code snipped.
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
bool set(const std::string &key, T value)
template function to set the value of a configuration key.
T get(const std::string &key, T default_, bool *default_used=0)
template function to read the value of a configuration key.
interface to set interrupt bits
template implementation of an InterruptVector that uses integer variables to store interrupt bit valu...
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
a Field instance represents e.g.
static std::shared_ptr< VirtualStruct > allocate(void *structure, std::function< void(Field *)> delete_)
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
unsigned byteCount() const
void addTo(ModedInstructionSet &set, bool &ok)
this class contains parameters that persist in between instruction lookpus/translation within a trans...
bool is_not_default_width_
if true the this instruction is not as long as the width of the variable instruction set
bool instr_width_fully_evaluated_
if true the length_updater_ function will be called again after instr_width_ bits are available
uint64_t current_address_
start address of current instruction
Instruction & getInvalid()
bool addCallback(std::function< bool(BitArray &, etiss::CodeSet &, InstructionContext &)> callback, uint32_t builtinGroups, const std::set< uint32_t > &groups=std::set< uint32_t >())
holds etiss::instr::VariableInstructionSet instances for different modes.
std::string print(std::string prefix=std::string())
VariableInstructionSet * get(uint32_t mode)
holds etiss::instr::InstructionSet instances with different bit widths.
InstructionSet * get(unsigned width)
std::function< void(VariableInstructionSet &, InstructionContext &, BitArray &)> length_updater_
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Configuration & cfg(const std::string &cfgName)
Get reference of the global ETISS configuration object.
void log(Verbosity level, std::string msg)
write log message at the given level.
basic cpu state structure needed for execution of any cpu architecture.
etiss_uint64 instructionPointer
pointer to next instruction.
Generated on Thu, 24 Oct 2024 10:16:12 +0200.