ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
CPUArch.cpp
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1 
52 #include "etiss/CPUArch.h"
53 
54 #include <iostream>
55 
56 #include "etiss/CPUCore.h"
57 
58 using namespace etiss;
59 
61 
63 
65 { // disfunctional implementation
66  return 0;
67 }
68 
70 { // disfunctional implementation
71  delete timer;
72 }
73 
74 CPUArch::CPUArch(std::string archname) : archname_(archname)
75 {
76  setCorrespondingCPUCoreName(std::string("core") + std::to_string(CPUCore::getNextID()));
77 }
78 
80 
81 std::string CPUArch::getArchName() const
82 {
83  return archname_;
84 }
85 
86 bool CPUArch::unlikelyInstruction(etiss::uint8 *instr, unsigned length, bool &ismetainstruction)
87 { // simple implementation that return 0 if the
88  // data is 0
89  ismetainstruction = false;
90  while (length >= 4)
91  {
92  if (*(etiss::uint32 *)instr != 0)
93  return false;
94  instr += 4;
95  length -= 4;
96  }
97  while (length > 0)
98  {
99  if (*instr != 0)
100  return false;
101  instr += 1;
102  length -= 1;
103  }
104  return true;
105 }
106 
108 {
109  return "";
110 }
111 
113 {
116 }
117 
119 {
120  return 1;
121 }
122 
124 { // disfunctional implementation
125  return code;
126 }
127 
129 { // disfunctional implementation
130  return (etiss::InterruptVector *)0;
131 }
133 { // disfunctional
134  // implementation allow
135  // memory leak
136 }
137 
139  return new etiss::InterruptEnable();
140 }
142  delete en;
143 }
144 
146 { // disfunctional implementation
147  return gdbcore_;
148 }
149 
151 {
152  return etiss::cfg().get<std::string>("etiss_wd", "") + "Arch/" + getName() + "/";
153 }
154 
155 std::string CPUArch::_getPluginName() const
156 {
157  return getName();
158 }
159 
161 {
162  if (set == nullptr)
163  return;
164  set->foreach ([](etiss::instr::Instruction &instr) {
165  if (((uint32_t)instr.presentBuiltinGroups() &
166  (uint32_t)etiss::instr::Instruction::BUILTINGROUP::CPUTIMEUPDATE) == 0)
167  { // update time
168  instr.addCallback(
169  [](etiss::instr::BitArray &, etiss::CodeSet &cs, etiss::instr::InstructionContext &) {
170  CodePart &cp = cs.prepend(CodePart::INITIALREQUIRED);
171  cp.getAffectedRegisters().add("cpuTime_ps", 64);
172  cp.code() = "cpu->cpuTime_ps += (1 * cpu->cpuCycleTime_ps);";
173  return true;
174  },
175  (uint32_t)etiss::instr::Instruction::BUILTINGROUP::CPUTIMEUPDATE);
176  }
178  });
179 }
180 
181 void CPUArch::finalizeInstrSet(etiss::instr::ModedInstructionSet &mis) const
182 {
185  });
186 }
187 
189 {
190  etiss::instr::Buffer buffer(ba.intCount(), ba.to_ulong());
192  ba.set_value(buffer.data());
193 }
194 
195 extern "C"
196 {
197 
198  void ETISS_signalChangedRegisterValue(ETISS_CPU *cpu, const char *registerName)
199  {
200  CPUArch::signalChangedRegisterValue(cpu, registerName);
201  }
202 
203  void etiss_icache_flush(ETISS_CPU *cpu, ETISS_System * const system, void * const * const plugin_pointers)
204  {
205  cpu->exception = etiss::RETURNCODE::RELOADBLOCKS;
206  }
207 }
etiss_uint8 uint8
Definition: 386-GCC.h:76
etiss_int32 int32
Definition: 386-GCC.h:81
etiss_uint32 uint32
Definition: 386-GCC.h:80
void ETISS_signalChangedRegisterValue(ETISS_CPU *cpu, const char *registerName)
Definition: CPUArch.cpp:198
static void CPUArch_finalizeInstrSet(etiss::instr::InstructionSet *set)
Definition: CPUArch.cpp:160
void etiss_icache_flush(ETISS_CPU *cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: CPUArch.cpp:203
contains neccesary interfaces for instruction translation.
defines main cpu core interface
static __inline__ uint32_t
Definition: arm_cde.h:25
virtual etiss::Plugin * newTimer(ETISS_CPU *cpu)
create a simple default timer implementaion instance for this architecture.
Definition: CPUArch.cpp:64
virtual void deleteTimer(etiss::Plugin *timer)
delete timer instance
Definition: CPUArch.cpp:69
static void signalChangedRegisterValue(ETISS_CPU *cpu, const char *registerName)
call this function to inform RegisterDevicePlugins about changed special register values.
Definition: CPUCore.cpp:43
std::string archname_
Definition: CPUArch.h:276
virtual etiss::InterruptEnable * createInterruptEnable(ETISS_CPU *cpu)
Definition: CPUArch.cpp:138
virtual std::string getIncludePath()
returns a path that will be used to look up header files
Definition: CPUArch.cpp:150
CPUArch(std::string archname)
Definition: CPUArch.cpp:74
virtual unsigned getMaximumInstructionsPerMetaInstruction()
maximum number of instructions in a meta instruction
Definition: CPUArch.cpp:112
virtual std::string getBlockGlobalCode()
get c++ code snippet that is placed at the top of a translated block
Definition: CPUArch.cpp:107
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
returns arch dependent gdb functions.
Definition: CPUArch.cpp:145
virtual unsigned getInstructionSizeInBytes()=0
size of one instruction/ smalest data unit for instructions of variable length
virtual std::string _getPluginName() const
do not override. maps to getName().
Definition: CPUArch.cpp:155
virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu)
delete an allocated interrupt vector object
Definition: CPUArch.cpp:132
virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU *cpu)
allocate a new interrupt vector object for the given cpu
Definition: CPUArch.cpp:128
virtual void deleteInterruptEnable(etiss::InterruptEnable *en, ETISS_CPU *cpu)
Definition: CPUArch.cpp:141
std::string getArchName() const
returns the name of this architecture.
Definition: CPUArch.cpp:81
etiss::plugin::gdb::GDBCore gdbcore_
Definition: CPUArch.h:275
virtual bool unlikelyInstruction(etiss::uint8 *instr, unsigned length, bool &ismetainstruction)
return true if the given data is unlikely to be an instruction.
Definition: CPUArch.cpp:86
virtual unsigned getMaximumInstructionSizeInBytes()=0
used for variable instruction size and delay slots
virtual void compensateEndianess(ETISS_CPU *cpu, etiss::instr::BitArray &ba) const
this function should compensate for any endianess on a BitArray so that bit 0 is always the LSB.
Definition: CPUArch.cpp:188
virtual unsigned getSuperInstructionCount()
fixed number of sub instructions per instruction (e.g.
Definition: CPUArch.cpp:118
virtual ~CPUArch()
Definition: CPUArch.cpp:79
virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU *cpu)
translate/process exceptions that occur at runtime
Definition: CPUArch.cpp:123
std::string getName() const
returns the name of this architecture.
Definition: CPUArch.h:184
static int getNextID()
Definition: CPUCore.cpp:135
T get(const std::string &key, T default_, bool *default_used=0)
template function to read the value of a configuration key.
Definition: Misc.h:349
interface to set interrupt bits
base plugin class that provides access to different plugin functions if present
Definition: Plugin.h:77
void setCorrespondingCPUCoreName(std::string name)
Definition: Plugin.h:204
stores a bit vector
Definition: Instruction.h:161
void set_value(size_type width, unsigned long value)
change the value the object is holding
unsigned intCount() const
Buffer for reading data from memory while instructions are being fetched.
Definition: Instruction.h:92
void recoverFromEndianness(unsigned alignment, endian_t endianness)
changes byte positions as needed to resove endiannes incompabilities after using the internal buffer ...
Definition: Instruction.cpp:78
holds etiss::instr::Instruction instances and handles automatic instruction tree creation.
Definition: Instruction.h:442
void foreach(std::function< void(Instruction &)> func)
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
uint32_t & presentBuiltinGroups()
holds etiss::instr::VariableInstructionSet instances for different modes.
Definition: Instruction.h:562
void foreach(std::function< void(VariableInstructionSet &)> call)
holds etiss::instr::InstructionSet instances with different bit widths.
Definition: Instruction.h:500
void foreach(std::function< void(InstructionSet &)> func)
provides to architecture dependent registers as defined by gdb
Definition: GDBCore.h:77
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
@ _BIG_ENDIAN_
Definition: Misc.h:527
Configuration & cfg(const std::string &cfgName)
Get reference of the global ETISS configuration object.
Definition: Misc.cpp:560
float __ovld __cnfn length(float p)
Return the length of vector p, i.e., sqrt(p.x2 + p.y 2 + ...)
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
etiss_uint32 exception
Definition: CPU.h:111
memory access and time synchronization functions.
Definition: System.h:78