CPUCore.h File Reference

defines main cpu core interface More...

#include "etiss/ClassDefs.h"
#include "etiss/Misc.h"
#include "etiss/LibraryInterface.h"
#include "etiss/JIT.h"
#include "etiss/CPUArch.h"
#include "etiss/Translation.h"
#include "etiss/System.h"
#include "etiss/InterruptHandler.h"
#include "etiss/InterruptEnable.h"
#include "etiss/Plugin.h"
#include "etiss/jit/ReturnCode.h"
#include "etiss/mm/MMU.h"
#include "etiss/mm/DMMUWrapper.h"
#include "etiss/mm/PageFaultVector.h"
#include <mutex>
#include <memory>
#include <list>

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Classes
class	etiss::CPUCore
	CPUCore is responsible for the simulation of a CPU core in ETISS. More...
class	etiss::CPUCore::InterruptVectorWrapper

Namespaces
	etiss
	Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.

Macros
#define	ETISS_CPUCORE_DBG_APPROXIMATE_INSTRUCTION_COUNTER   0

Detailed Description

defines main cpu core interface

Copyright

Copyright 2018 Infineon Technologies AG

This file is part of ETISS tool, see https://github.com/tum-ei-eda/etiss.

The initial version of this software has been created with the funding support by the German Federal
Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.

Redistribution and use in source and binary forms, with or without modification, are permitted
provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and
the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
and the following disclaimer in the documentation and/or other materials provided with the distribution.

3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

Author

Marc Greim marc..nosp@m.grei.nosp@m.m@myt.nosp@m.um.d.nosp@m.e, Chair of Electronic Design Automation, TUM

Date

July 23, 2014

Version

0.1

Definition in file CPUCore.h.

Macro Definition Documentation

ETISS_CPUCORE_DBG_APPROXIMATE_INSTRUCTION_COUNTER

#define ETISS_CPUCORE_DBG_APPROXIMATE_INSTRUCTION_COUNTER   0

Definition at line 78 of file CPUCore.h.