ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
Loading...
Searching...
No Matches
RV32IMACFDFuncs.c
Go to the documentation of this file.
1
7#include "RV32IMACFDFuncs.h"
8// clang-format off
9
10etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
11{
12etiss_coverage_count(1, 80);
13{ // block
14etiss_coverage_count(1, 257);
15etiss_coverage_count(1, 256);
16return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
17etiss_coverage_count(9, 255, 252, 247, 250, 248, 249, 251, 253, 254);
18} // block
19}
20
21etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
22{
23etiss_coverage_count(1, 87);
24{ // block
25etiss_coverage_count(1, 277);
26etiss_coverage_count(1, 258);
27if (rm == 7ULL) { // conditional
28etiss_coverage_count(3, 261, 259, 260);
29rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 0x7ULL)) & 0x7ULL;
30etiss_coverage_count(6, 267, 262, 266, 263, 264, 265);
31} // conditional
32etiss_coverage_count(1, 268);
33if (rm > 4ULL) { // conditional
34etiss_coverage_count(3, 271, 269, 270);
35RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);
36etiss_coverage_count(2, 274, 272);
37} // conditional
38etiss_coverage_count(1, 276);
39return rm;
40etiss_coverage_count(1, 275);
41} // block
42}
43
44etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
45{
46etiss_coverage_count(1, 149);
47{ // block
48etiss_coverage_count(1, 350);
49etiss_uint32 mask = 0LL;
50etiss_coverage_count(2, 280, 279);
51etiss_coverage_count(1, 281);
52if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
53etiss_coverage_count(2, 283, 282);
54{ // block
55etiss_coverage_count(1, 347);
56mask = mask | 5767458ULL;
57etiss_coverage_count(2, 299, 284);
58etiss_coverage_count(1, 300);
59if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
60etiss_coverage_count(2, 302, 301);
61mask = mask | 1536LL;
62etiss_coverage_count(2, 305, 303);
63} // conditional
64etiss_coverage_count(1, 306);
65if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
66etiss_coverage_count(2, 308, 307);
67mask = mask | 24576LL;
68etiss_coverage_count(2, 311, 309);
69} // conditional
70etiss_coverage_count(1, 312);
71if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
72etiss_coverage_count(2, 314, 313);
73mask = mask | 98304LL;
74etiss_coverage_count(2, 317, 315);
75} // conditional
76etiss_coverage_count(1, 318);
77if ((RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
78etiss_coverage_count(3, 328, 324, 330);
79mask = mask | 262144LL;
80etiss_coverage_count(2, 346, 344);
81} // conditional
82} // block
83} // conditional
84etiss_coverage_count(1, 349);
85return mask;
86etiss_coverage_count(1, 348);
87} // block
88}
89
90etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
91{
92etiss_coverage_count(1, 150);
93{ // block
94etiss_coverage_count(1, 365);
95etiss_uint32 mask = 6280ULL;
96etiss_coverage_count(1, 360);
97etiss_coverage_count(1, 364);
98return mask | RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
99etiss_coverage_count(3, 363, 361, 362);
100} // block
101}
102
103etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
104{
105etiss_coverage_count(1, 151);
106{ // block
107etiss_coverage_count(1, 483);
108etiss_coverage_count(1, 366);
109if (csr == 1LL) { // conditional
110etiss_coverage_count(2, 369, 367);
111etiss_coverage_count(1, 375);
112return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
113etiss_coverage_count(3, 374, 372, 373);
114} // conditional
115etiss_coverage_count(1, 376);
116if (csr == 2LL) { // conditional
117etiss_coverage_count(2, 379, 377);
118etiss_coverage_count(1, 388);
119return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
120etiss_coverage_count(6, 387, 384, 382, 383, 385, 386);
121} // conditional
122etiss_coverage_count(1, 389);
123if (csr == 3072LL) { // conditional
124etiss_coverage_count(2, 392, 390);
125etiss_coverage_count(1, 394);
126return etiss_get_cycles(cpu, system, plugin_pointers);
127etiss_coverage_count(1, 393);
128} // conditional
129etiss_coverage_count(1, 395);
130if (csr == 3200LL) { // conditional
131etiss_coverage_count(2, 398, 396);
132etiss_coverage_count(1, 402);
133return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
134etiss_coverage_count(3, 401, 399, 400);
135} // conditional
136etiss_coverage_count(1, 403);
137if (csr == 3073LL) { // conditional
138etiss_coverage_count(2, 406, 404);
139etiss_coverage_count(1, 408);
140return etiss_get_time();
141etiss_coverage_count(1, 407);
142} // conditional
143etiss_coverage_count(1, 409);
144if (csr == 3201LL) { // conditional
145etiss_coverage_count(2, 412, 410);
146etiss_coverage_count(1, 416);
147return etiss_get_time() >> 32ULL;
148etiss_coverage_count(3, 415, 413, 414);
149} // conditional
150etiss_coverage_count(1, 417);
151if (csr == 3074LL) { // conditional
152etiss_coverage_count(2, 420, 418);
153etiss_coverage_count(1, 422);
154return etiss_get_instret(cpu, system, plugin_pointers);
155etiss_coverage_count(1, 421);
156} // conditional
157etiss_coverage_count(1, 423);
158if (csr == 3202LL) { // conditional
159etiss_coverage_count(2, 426, 424);
160etiss_coverage_count(1, 430);
161return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
162etiss_coverage_count(3, 429, 427, 428);
163} // conditional
164etiss_coverage_count(1, 431);
165if (csr == 768LL || csr == 256LL) { // conditional
166etiss_coverage_count(5, 438, 434, 432, 437, 435);
167etiss_coverage_count(1, 458);
168return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
169etiss_coverage_count(3, 457, 449, 441);
170} // conditional
171etiss_coverage_count(1, 459);
172if (csr == 769LL) { // conditional
173etiss_coverage_count(2, 462, 460);
174etiss_coverage_count(1, 478);
175return (((1ULL) << 30) | (((*((RV32IMACFD*)cpu)->CSR[769LL]) & 0x3fffffffULL)));
176etiss_coverage_count(4, 477, 476, 471, 475);
177} // conditional
178etiss_coverage_count(1, 482);
179return *((RV32IMACFD*)cpu)->CSR[csr];
180etiss_coverage_count(2, 481, 480);
181} // block
182}
183
184void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
185{
186etiss_coverage_count(1, 152);
187{ // block
188etiss_coverage_count(1, 565);
189etiss_coverage_count(1, 484);
190if (csr == 1LL) { // conditional
191etiss_coverage_count(2, 487, 485);
192*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
193etiss_coverage_count(10, 520, 505, 519, 513, 508, 514, 517, 515, 516, 518);
194} // conditional
195 else if (csr == 2LL) { // conditional
196etiss_coverage_count(2, 490, 488);
197*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
198etiss_coverage_count(14, 538, 523, 537, 529, 526, 524, 525, 527, 528, 530, 535, 533, 534, 536);
199} // conditional
200 else if (csr == 3LL) { // conditional
201etiss_coverage_count(2, 493, 491);
202*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
203etiss_coverage_count(5, 545, 541, 544, 542, 543);
204} // conditional
205 else if (csr == 768LL) { // conditional
206etiss_coverage_count(2, 496, 494);
207*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_mstatus_mask(cpu, system, plugin_pointers);
208etiss_coverage_count(5, 552, 548, 551, 549, 550);
209} // conditional
210 else if (csr == 256LL) { // conditional
211etiss_coverage_count(2, 499, 497);
212*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
213etiss_coverage_count(5, 559, 555, 558, 556, 557);
214} // conditional
215 else if (csr != 769LL) { // conditional
216etiss_coverage_count(2, 502, 500);
217*((RV32IMACFD*)cpu)->CSR[csr] = val;
218etiss_coverage_count(4, 564, 562, 561, 563);
219} // conditional
220} // block
221}
222
223etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
224{
225etiss_coverage_count(1, 159);
226{ // block
227etiss_coverage_count(1, 585);
228etiss_coverage_count(1, 566);
229if (!(mask)) { // conditional
230etiss_coverage_count(2, 568, 567);
231etiss_coverage_count(1, 570);
232return 0LL;
233etiss_coverage_count(1, 569);
234} // conditional
235etiss_coverage_count(1, 584);
236return (reg & mask) / (mask & ~((mask << 1ULL)));
237etiss_coverage_count(13, 583, 573, 571, 572, 574, 581, 575, 580, 578, 576, 577, 579, 582);
238} // block
239}
240
241etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
242{
243etiss_coverage_count(1, 160);
244{ // block
245etiss_coverage_count(1, 608);
246etiss_coverage_count(1, 607);
247return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
248etiss_coverage_count(21, 605, 589, 586, 588, 587, 590, 603, 600, 591, 598, 592, 597, 595, 593, 594, 596, 599, 601, 602, 604, 606);
249} // block
250}
251
252etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
253{
254etiss_coverage_count(1, 161);
255{ // block
256etiss_coverage_count(1, 703);
257etiss_coverage_count(1, 609);
258if (!(val)) { // conditional
259etiss_coverage_count(2, 611, 610);
260etiss_coverage_count(1, 613);
261return 0LL;
262etiss_coverage_count(1, 612);
263} // conditional
264etiss_uint8 res = 0LL;
265etiss_coverage_count(2, 616, 615);
266etiss_coverage_count(1, 617);
267if ((val << 32ULL) == 0LL) { // conditional
268etiss_coverage_count(6, 623, 620, 618, 619, 621, 622);
269{ // block
270etiss_coverage_count(1, 630);
271res = res + 32ULL;
272etiss_coverage_count(3, 626, 624, 625);
273val = val >> 32ULL;
274etiss_coverage_count(3, 629, 627, 628);
275} // block
276} // conditional
277etiss_coverage_count(1, 631);
278if ((val << 48ULL) == 0LL) { // conditional
279etiss_coverage_count(6, 637, 634, 632, 633, 635, 636);
280{ // block
281etiss_coverage_count(1, 644);
282res = res + 16ULL;
283etiss_coverage_count(3, 640, 638, 639);
284val = val >> 16ULL;
285etiss_coverage_count(3, 643, 641, 642);
286} // block
287} // conditional
288etiss_coverage_count(1, 645);
289if ((val << 56ULL) == 0LL) { // conditional
290etiss_coverage_count(6, 651, 648, 646, 647, 649, 650);
291{ // block
292etiss_coverage_count(1, 658);
293res = res + 8ULL;
294etiss_coverage_count(3, 654, 652, 653);
295val = val >> 8ULL;
296etiss_coverage_count(3, 657, 655, 656);
297} // block
298} // conditional
299etiss_coverage_count(1, 659);
300if ((val << 60ULL) == 0LL) { // conditional
301etiss_coverage_count(6, 665, 662, 660, 661, 663, 664);
302{ // block
303etiss_coverage_count(1, 672);
304res = res + 4ULL;
305etiss_coverage_count(3, 668, 666, 667);
306val = val >> 4ULL;
307etiss_coverage_count(3, 671, 669, 670);
308} // block
309} // conditional
310etiss_coverage_count(1, 673);
311if ((val << 62ULL) == 0LL) { // conditional
312etiss_coverage_count(6, 679, 676, 674, 675, 677, 678);
313{ // block
314etiss_coverage_count(1, 686);
315res = res + 2ULL;
316etiss_coverage_count(3, 682, 680, 681);
317val = val >> 2ULL;
318etiss_coverage_count(3, 685, 683, 684);
319} // block
320} // conditional
321etiss_coverage_count(1, 687);
322if ((val << 63ULL) == 0LL) { // conditional
323etiss_coverage_count(6, 693, 690, 688, 689, 691, 692);
324{ // block
325etiss_coverage_count(1, 700);
326res = res + 1ULL;
327etiss_coverage_count(3, 696, 694, 695);
328val = val >> 1ULL;
329etiss_coverage_count(3, 699, 697, 698);
330} // block
331} // conditional
332etiss_coverage_count(1, 702);
333return res;
334etiss_coverage_count(1, 701);
335} // block
336}
337
338void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
339{
340cpu->return_pending = 1;
341cpu->exception = 0;
342etiss_coverage_count(1, 162);
343{ // block
344etiss_coverage_count(1, 916);
345etiss_uint32 epc = cpu->instructionPointer;
346etiss_coverage_count(2, 706, 705);
347etiss_uint32 deleg = 0LL;
348etiss_coverage_count(1, 708);
349etiss_uint32 vector = 0LL;
350etiss_coverage_count(1, 709);
351etiss_uint32 bit = mcause;
352etiss_coverage_count(2, 711, 710);
353etiss_int32 irq2 = (mcause & 2147483648ULL) != 0LL;
354etiss_coverage_count(6, 727, 726, 723, 713, 724, 725);
355etiss_coverage_count(1, 728);
356if (irq2) { // conditional
357etiss_coverage_count(1, 729);
358{ // block
359etiss_coverage_count(1, 754);
360deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0LL);
361etiss_coverage_count(8, 740, 730, 739, 733, 731, 734, 737, 738);
362bit = bit & 2147483647ULL;
363etiss_coverage_count(2, 753, 741);
364} // block
365} // conditional
366else { // conditional
367{ // block
368etiss_coverage_count(1, 766);
369deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0LL);
370etiss_coverage_count(8, 765, 755, 764, 758, 756, 759, 762, 763);
371} // block
372} // conditional
373etiss_coverage_count(1, 767);
374if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
375etiss_coverage_count(9, 777, 770, 768, 776, 773, 771, 772, 774, 775);
376{ // block
377etiss_coverage_count(1, 846);
378vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
379etiss_coverage_count(13, 792, 778, 791, 786, 783, 781, 782, 784, 785, 789, 787, 788, 790);
380cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
381etiss_coverage_count(7, 805, 793, 804, 801, 796, 802, 803);
382*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
383etiss_coverage_count(3, 810, 808, 809);
384*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
385etiss_coverage_count(3, 815, 813, 814);
386etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
387etiss_coverage_count(2, 819, 818);
388s = RV32IMACFD_set_field(s, 32LL, RV32IMACFD_get_field(s, 2LL));
389etiss_coverage_count(6, 827, 820, 826, 821, 825, 823);
390s = RV32IMACFD_set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
391etiss_coverage_count(5, 833, 828, 832, 829, 831);
392s = RV32IMACFD_set_field(s, 2LL, 0LL);
393etiss_coverage_count(5, 839, 834, 838, 835, 837);
394RV32IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
395etiss_coverage_count(2, 842, 841);
396((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7ULL;
397etiss_coverage_count(2, 845, 843);
398} // block
399} // conditional
400else { // conditional
401{ // block
402etiss_coverage_count(1, 915);
403vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
404etiss_coverage_count(13, 861, 847, 860, 855, 852, 850, 851, 853, 854, 858, 856, 857, 859);
405cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
406etiss_coverage_count(7, 874, 862, 873, 870, 865, 871, 872);
407*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
408etiss_coverage_count(3, 879, 877, 878);
409*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
410etiss_coverage_count(3, 884, 882, 883);
411etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
412etiss_coverage_count(2, 888, 887);
413s = RV32IMACFD_set_field(s, 128LL, RV32IMACFD_get_field(s, 8LL));
414etiss_coverage_count(6, 896, 889, 895, 890, 894, 892);
415s = RV32IMACFD_set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
416etiss_coverage_count(5, 902, 897, 901, 898, 900);
417s = RV32IMACFD_set_field(s, 8LL, 0LL);
418etiss_coverage_count(5, 908, 903, 907, 904, 906);
419RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
420etiss_coverage_count(2, 911, 910);
421((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7ULL;
422etiss_coverage_count(2, 914, 912);
423} // block
424} // conditional
425} // block
426}
427
428void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
429{
430etiss_coverage_count(1, 163);
431{ // block
432etiss_coverage_count(1, 973);
433etiss_uint32 code = 0LL;
434etiss_coverage_count(2, 920, 919);
435etiss_coverage_count(1, 921);
436if (cause == -2147483648LL) { // conditional
437etiss_coverage_count(2, 924, 922);
438etiss_coverage_count(1, 943);
439return;
440} // conditional
441 else if (cause == -5LL) { // conditional
442etiss_coverage_count(2, 927, 925);
443code = 5LL;
444etiss_coverage_count(2, 946, 944);
445} // conditional
446 else if (cause == -14LL) { // conditional
447etiss_coverage_count(2, 930, 928);
448code = 13LL;
449etiss_coverage_count(2, 949, 947);
450} // conditional
451 else if (cause == -6LL) { // conditional
452etiss_coverage_count(2, 933, 931);
453code = 7LL;
454etiss_coverage_count(2, 952, 950);
455} // conditional
456 else if (cause == -15LL) { // conditional
457etiss_coverage_count(2, 936, 934);
458code = 15LL;
459etiss_coverage_count(2, 955, 953);
460} // conditional
461 else if (cause == -7LL) { // conditional
462etiss_coverage_count(2, 939, 937);
463code = 1LL;
464etiss_coverage_count(2, 958, 956);
465} // conditional
466 else if (cause == -9LL) { // conditional
467etiss_coverage_count(2, 942, 940);
468{ // block
469etiss_coverage_count(1, 966);
470code = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
471etiss_coverage_count(3, 961, 959, 960);
472etiss_coverage_count(1, 962);
473if (!(code)) { // conditional
474etiss_coverage_count(2, 964, 963);
475etiss_coverage_count(1, 965);
476return;
477} // conditional
478} // block
479} // conditional
480else { // conditional
481code = 2LL;
482etiss_coverage_count(2, 969, 967);
483} // conditional
484RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, code);
485etiss_coverage_count(3, 972, 970, 971);
486} // block
487}
488
489etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
490{
491etiss_coverage_count(1, 164);
492{ // block
493etiss_coverage_count(1, 1154);
494etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
495etiss_coverage_count(4, 982, 981, 977, 980);
496etiss_coverage_count(1, 983);
497if (!(pending_interrupts)) { // conditional
498etiss_coverage_count(2, 985, 984);
499etiss_coverage_count(1, 987);
500return 0LL;
501etiss_coverage_count(1, 986);
502} // conditional
503etiss_uint32 mie = RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
504etiss_coverage_count(3, 994, 993, 991);
505etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
506etiss_coverage_count(9, 1006, 1005, 998, 996, 1003, 1001, 999, 1002, 1004);
507etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
508etiss_coverage_count(8, 1017, 1016, 1013, 1008, 1012, 1011, 1015, 1014);
509etiss_coverage_count(1, 1018);
510if (enabled_interrupts == 0LL) { // conditional
511etiss_coverage_count(3, 1021, 1019, 1020);
512{ // block
513etiss_coverage_count(1, 1053);
514etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
515etiss_coverage_count(2, 1026, 1025);
516etiss_uint32 sie = RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
517etiss_coverage_count(3, 1032, 1031, 1029);
518etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
519etiss_coverage_count(9, 1044, 1043, 1036, 1034, 1041, 1039, 1037, 1040, 1042);
520enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
521etiss_coverage_count(8, 1052, 1045, 1051, 1048, 1046, 1047, 1050, 1049);
522} // block
523} // conditional
524etiss_coverage_count(1, 1054);
525if (enabled_interrupts) { // conditional
526etiss_coverage_count(1, 1055);
527{ // block
528etiss_coverage_count(1, 1151);
529etiss_coverage_count(1, 1056);
530if (enabled_interrupts >> 12ULL) { // conditional
531etiss_coverage_count(2, 1062, 1057);
532enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
533etiss_coverage_count(5, 1105, 1093, 1104, 1099, 1094);
534} // conditional
535 else if (enabled_interrupts & 2048LL) { // conditional
536etiss_coverage_count(2, 1065, 1063);
537enabled_interrupts = 2048LL;
538etiss_coverage_count(2, 1108, 1106);
539} // conditional
540 else if (enabled_interrupts & 8LL) { // conditional
541etiss_coverage_count(2, 1068, 1066);
542enabled_interrupts = 8LL;
543etiss_coverage_count(2, 1111, 1109);
544} // conditional
545 else if (enabled_interrupts & 128LL) { // conditional
546etiss_coverage_count(2, 1071, 1069);
547enabled_interrupts = 128LL;
548etiss_coverage_count(2, 1114, 1112);
549} // conditional
550 else if (enabled_interrupts & 512LL) { // conditional
551etiss_coverage_count(2, 1074, 1072);
552enabled_interrupts = 512LL;
553etiss_coverage_count(2, 1117, 1115);
554} // conditional
555 else if (enabled_interrupts & 2LL) { // conditional
556etiss_coverage_count(2, 1077, 1075);
557enabled_interrupts = 2LL;
558etiss_coverage_count(2, 1120, 1118);
559} // conditional
560 else if (enabled_interrupts & 32LL) { // conditional
561etiss_coverage_count(2, 1080, 1078);
562enabled_interrupts = 32LL;
563etiss_coverage_count(2, 1123, 1121);
564} // conditional
565 else if (enabled_interrupts & 8192LL) { // conditional
566etiss_coverage_count(2, 1083, 1081);
567enabled_interrupts = 8192LL;
568etiss_coverage_count(2, 1126, 1124);
569} // conditional
570 else if (enabled_interrupts & 1024LL) { // conditional
571etiss_coverage_count(2, 1086, 1084);
572enabled_interrupts = 1024LL;
573etiss_coverage_count(2, 1129, 1127);
574} // conditional
575 else if (enabled_interrupts & 4LL) { // conditional
576etiss_coverage_count(2, 1089, 1087);
577enabled_interrupts = 4LL;
578etiss_coverage_count(2, 1132, 1130);
579} // conditional
580 else if (enabled_interrupts & 64LL) { // conditional
581etiss_coverage_count(2, 1092, 1090);
582enabled_interrupts = 64LL;
583etiss_coverage_count(2, 1135, 1133);
584} // conditional
585else { // conditional
586etiss_coverage_count(1, 1137);
587return 0LL;
588etiss_coverage_count(1, 1136);
589} // conditional
590etiss_coverage_count(1, 1150);
591return 2147483648ULL | RV32IMACFD_ctz(enabled_interrupts);
592etiss_coverage_count(3, 1149, 1148, 1147);
593} // block
594} // conditional
595etiss_coverage_count(1, 1153);
596return 0LL;
597etiss_coverage_count(1, 1152);
598} // block
599}
600
601void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
602{
603etiss_coverage_count(1, 165);
604{ // block
605etiss_coverage_count(1, 1163);
606etiss_uint32 irq_mcause = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
607etiss_coverage_count(2, 1157, 1156);
608etiss_coverage_count(1, 1158);
609if (irq_mcause) { // conditional
610etiss_coverage_count(1, 1159);
611RV32IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
612etiss_coverage_count(3, 1162, 1160, 1161);
613} // conditional
614} // block
615}
616// clang-format on
RV32IMACFD_translate_exc_code
void RV32IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
Definition RV32IMACFDFuncs.c:428
RV32IMACFD_get_field
etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
Definition RV32IMACFDFuncs.c:223
RV32IMACFD_check_irq
void RV32IMACFD_check_irq(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:601
RV32IMACFD_set_field
etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
Definition RV32IMACFDFuncs.c:241
RV32IMACFD_csr_write
void RV32IMACFD_csr_write(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
Definition RV32IMACFDFuncs.c:184
RV32IMACFD_ctz
etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
Definition RV32IMACFDFuncs.c:252
RV32IMACFD_get_rm
etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint8 rm)
Definition RV32IMACFDFuncs.c:21
RV32IMACFD_sstatus_mask
etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:44
RV32IMACFD_mstatus_mask
etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:90
RV32IMACFD_extension_enabled
etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int8 extension)
Generated on Mon, 10 Nov 2025 11:27:12 +0000.
Definition RV32IMACFDFuncs.c:10
RV32IMACFD_calc_irq_mcause
etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:489
RV32IMACFD_raise
void RV32IMACFD_raise(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
Definition RV32IMACFDFuncs.c:338
RV32IMACFD_csr_read
etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr)
Definition RV32IMACFDFuncs.c:103
s
__device__ __2f16 float bool s
Definition __clang_hip_libdevice_declares.h:298
etiss_coverage_count
#define etiss_coverage_count(...)
Definition Coverage.h:18
etiss_get_instret
etiss_uint64 etiss_get_instret(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition CSRCounters.cpp:31
etiss_get_time
etiss_uint64 etiss_get_time()
Definition CSRCounters.cpp:24
etiss_get_cycles
etiss_uint64 etiss_get_cycles(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition CSRCounters.cpp:19
etiss_uint64
uint64_t etiss_uint64
Definition types.h:58
etiss_uint32
uint32_t etiss_uint32
Definition types.h:55
etiss_int8
int8_t etiss_int8
Definition types.h:48
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_int32
int32_t etiss_int32
Definition types.h:54
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition CPU.h:54
ETISS_CPU::exception
etiss_uint32 exception
Definition CPU.h:73
ETISS_CPU::return_pending
etiss_uint32 return_pending
Definition CPU.h:74
ETISS_System
memory access and time synchronization functions.
Definition System.h:40
RV32IMACFD
Generated on Mon, 10 Nov 2025 11:27:12 +0000.
Definition RV32IMACFD.h:18
Generated on Sat Nov 15 2025 19:30:09 for ETISS 0.11.2 by doxygen 1.9.8