ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV32IMACFDFuncs.c
Go to the documentation of this file.
1
7#include "RV32IMACFDFuncs.h"
8// clang-format off
9
10etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
11{
12etiss_coverage_count(1, 80);
13{ // block
14etiss_coverage_count(1, 257);
15etiss_coverage_count(1, 256);
16return (*((RV32IMACFD*)cpu)->CSR[769ULL] >> (extension - 65ULL)) & 1ULL;
17etiss_coverage_count(9, 255, 252, 247, 250, 248, 249, 251, 253, 254);
18} // block
19}
20
21etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
22{
23etiss_coverage_count(1, 87);
24{ // block
25etiss_coverage_count(1, 277);
26etiss_coverage_count(1, 258);
27if (rm == 7ULL) { // conditional
28etiss_coverage_count(3, 261, 259, 260);
29rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 0x7ULL)) & 0x7ULL;
30etiss_coverage_count(6, 267, 262, 266, 263, 264, 265);
31} // conditional
32etiss_coverage_count(1, 268);
33if (rm > 4ULL) { // conditional
34etiss_coverage_count(3, 271, 269, 270);
35RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);
36etiss_coverage_count(2, 274, 272);
37} // conditional
38etiss_coverage_count(1, 276);
39return rm;
40etiss_coverage_count(1, 275);
41} // block
42}
43
44etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
45{
46etiss_coverage_count(1, 149);
47{ // block
48etiss_coverage_count(1, 350);
49etiss_uint32 mask = 0LL;
50etiss_coverage_count(2, 280, 279);
51etiss_coverage_count(1, 281);
52if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
53etiss_coverage_count(2, 283, 282);
54{ // block
55etiss_coverage_count(1, 347);
56mask = mask | 5767458LL;
57etiss_coverage_count(2, 299, 284);
58etiss_coverage_count(1, 300);
59if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
60etiss_coverage_count(2, 302, 301);
61mask = mask | 1536ULL;
62etiss_coverage_count(2, 305, 303);
63} // conditional
64etiss_coverage_count(1, 306);
65if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
66etiss_coverage_count(2, 308, 307);
67mask = mask | 24576ULL;
68etiss_coverage_count(2, 311, 309);
69} // conditional
70etiss_coverage_count(1, 312);
71if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
72etiss_coverage_count(2, 314, 313);
73mask = mask | 98304ULL;
74etiss_coverage_count(2, 317, 315);
75} // conditional
76etiss_coverage_count(1, 318);
77if ((RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[384ULL], 2147483648ULL))) { // conditional
78etiss_coverage_count(3, 328, 324, 330);
79mask = mask | 262144ULL;
80etiss_coverage_count(2, 346, 344);
81} // conditional
82} // block
83} // conditional
84etiss_coverage_count(1, 349);
85return mask;
86etiss_coverage_count(1, 348);
87} // block
88}
89
90etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
91{
92etiss_coverage_count(1, 150);
93{ // block
94etiss_coverage_count(1, 365);
95etiss_uint32 mask = 6280LL;
96etiss_coverage_count(1, 360);
97etiss_coverage_count(1, 364);
98return mask | RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
99etiss_coverage_count(3, 363, 361, 362);
100} // block
101}
102
103etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
104{
105etiss_coverage_count(1, 151);
106{ // block
107etiss_coverage_count(1, 483);
108etiss_coverage_count(1, 366);
109if (csr == 1ULL) { // conditional
110etiss_coverage_count(2, 369, 367);
111etiss_coverage_count(1, 375);
112return *((RV32IMACFD*)cpu)->CSR[3ULL] & 31ULL;
113etiss_coverage_count(3, 374, 372, 373);
114} // conditional
115etiss_coverage_count(1, 376);
116if (csr == 2ULL) { // conditional
117etiss_coverage_count(2, 379, 377);
118etiss_coverage_count(1, 388);
119return (*((RV32IMACFD*)cpu)->CSR[3ULL] >> 5ULL) & 7ULL;
120etiss_coverage_count(6, 387, 384, 382, 383, 385, 386);
121} // conditional
122etiss_coverage_count(1, 389);
123if (csr == 3072ULL) { // conditional
124etiss_coverage_count(2, 392, 390);
125etiss_coverage_count(1, 394);
126return etiss_get_cycles(cpu, system, plugin_pointers);
127etiss_coverage_count(1, 393);
128} // conditional
129etiss_coverage_count(1, 395);
130if (csr == 3200ULL) { // conditional
131etiss_coverage_count(2, 398, 396);
132etiss_coverage_count(1, 402);
133return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
134etiss_coverage_count(3, 401, 399, 400);
135} // conditional
136etiss_coverage_count(1, 403);
137if (csr == 3073ULL) { // conditional
138etiss_coverage_count(2, 406, 404);
139etiss_coverage_count(1, 408);
140return etiss_get_time();
141etiss_coverage_count(1, 407);
142} // conditional
143etiss_coverage_count(1, 409);
144if (csr == 3201ULL) { // conditional
145etiss_coverage_count(2, 412, 410);
146etiss_coverage_count(1, 416);
147return etiss_get_time() >> 32ULL;
148etiss_coverage_count(3, 415, 413, 414);
149} // conditional
150etiss_coverage_count(1, 417);
151if (csr == 3074ULL) { // conditional
152etiss_coverage_count(2, 420, 418);
153etiss_coverage_count(1, 422);
154return etiss_get_instret(cpu, system, plugin_pointers);
155etiss_coverage_count(1, 421);
156} // conditional
157etiss_coverage_count(1, 423);
158if (csr == 3202ULL) { // conditional
159etiss_coverage_count(2, 426, 424);
160etiss_coverage_count(1, 430);
161return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
162etiss_coverage_count(3, 429, 427, 428);
163} // conditional
164etiss_coverage_count(1, 431);
165if (csr == 768ULL || csr == 256ULL) { // conditional
166etiss_coverage_count(5, 438, 434, 432, 437, 435);
167etiss_coverage_count(1, 458);
168return *((RV32IMACFD*)cpu)->CSR[768ULL] | 8589934592ULL | 34359738368ULL;
169etiss_coverage_count(3, 457, 449, 441);
170} // conditional
171etiss_coverage_count(1, 459);
172if (csr == 769ULL) { // conditional
173etiss_coverage_count(2, 462, 460);
174etiss_coverage_count(1, 478);
175return (((1ULL) << 30) | (((*((RV32IMACFD*)cpu)->CSR[769ULL]) & 0x3fffffffULL)));
176etiss_coverage_count(4, 477, 476, 471, 475);
177} // conditional
178etiss_coverage_count(1, 482);
179return *((RV32IMACFD*)cpu)->CSR[csr];
180etiss_coverage_count(2, 481, 480);
181} // block
182}
183
184void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
185{
186etiss_coverage_count(1, 152);
187{ // block
188etiss_coverage_count(1, 565);
189etiss_coverage_count(1, 484);
190if (csr == 1ULL) { // conditional
191etiss_coverage_count(2, 487, 485);
192*((RV32IMACFD*)cpu)->CSR[3ULL] = (*((RV32IMACFD*)cpu)->CSR[3ULL] & 224ULL) | (val & 31ULL);
193etiss_coverage_count(10, 520, 505, 519, 513, 508, 514, 517, 515, 516, 518);
194} // conditional
195 else if (csr == 2ULL) { // conditional
196etiss_coverage_count(2, 490, 488);
197*((RV32IMACFD*)cpu)->CSR[3ULL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3ULL] & 31ULL);
198etiss_coverage_count(14, 538, 523, 537, 529, 526, 524, 525, 527, 528, 530, 535, 533, 534, 536);
199} // conditional
200 else if (csr == 3ULL) { // conditional
201etiss_coverage_count(2, 493, 491);
202*((RV32IMACFD*)cpu)->CSR[3ULL] = val & 255ULL;
203etiss_coverage_count(5, 545, 541, 544, 542, 543);
204} // conditional
205 else if (csr == 768ULL) { // conditional
206etiss_coverage_count(2, 496, 494);
207*((RV32IMACFD*)cpu)->CSR[768ULL] = val & RV32IMACFD_mstatus_mask(cpu, system, plugin_pointers);
208etiss_coverage_count(5, 552, 548, 551, 549, 550);
209} // conditional
210 else if (csr == 256ULL) { // conditional
211etiss_coverage_count(2, 499, 497);
212*((RV32IMACFD*)cpu)->CSR[768ULL] = val & RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
213etiss_coverage_count(5, 559, 555, 558, 556, 557);
214} // conditional
215 else if (csr != 769ULL) { // conditional
216etiss_coverage_count(2, 502, 500);
217*((RV32IMACFD*)cpu)->CSR[csr] = val;
218etiss_coverage_count(4, 564, 562, 561, 563);
219} // conditional
220} // block
221}
222
223etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
224{
225etiss_coverage_count(1, 159);
226{ // block
227etiss_coverage_count(1, 585);
228etiss_coverage_count(1, 566);
229if (!(mask)) { // conditional
230etiss_coverage_count(2, 568, 567);
231etiss_coverage_count(1, 570);
232return 0LL;
233etiss_coverage_count(1, 569);
234} // conditional
235etiss_coverage_count(1, 584);
236return (reg & mask) / (mask & ~((mask << 1ULL)));
237etiss_coverage_count(13, 583, 573, 571, 572, 574, 581, 575, 580, 578, 576, 577, 579, 582);
238} // block
239}
240
241etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
242{
243etiss_coverage_count(1, 160);
244{ // block
245etiss_coverage_count(1, 608);
246etiss_coverage_count(1, 607);
247return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
248etiss_coverage_count(21, 605, 589, 586, 588, 587, 590, 603, 600, 591, 598, 592, 597, 595, 593, 594, 596, 599, 601, 602, 604, 606);
249} // block
250}
251
252etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
253{
254etiss_coverage_count(1, 161);
255{ // block
256etiss_coverage_count(1, 700);
257etiss_coverage_count(1, 609);
258if (!(val)) { // conditional
259etiss_coverage_count(2, 611, 610);
260etiss_coverage_count(1, 613);
261return 0LL;
262etiss_coverage_count(1, 612);
263} // conditional
264etiss_uint8 res = 0LL;
265etiss_coverage_count(2, 616, 615);
266etiss_coverage_count(1, 617);
267if ((val << 32ULL) == 0LL) { // conditional
268etiss_coverage_count(6, 623, 620, 618, 619, 621, 622);
269{ // block
270etiss_coverage_count(1, 630);
271res = res + 32ULL;
272etiss_coverage_count(3, 626, 624, 625);
273val = val >> 32ULL;
274etiss_coverage_count(3, 629, 627, 628);
275} // block
276} // conditional
277etiss_coverage_count(1, 631);
278if ((val << 48ULL) == 0LL) { // conditional
279etiss_coverage_count(6, 637, 634, 632, 633, 635, 636);
280{ // block
281etiss_coverage_count(1, 644);
282res = res + 16ULL;
283etiss_coverage_count(3, 640, 638, 639);
284val = val >> 16ULL;
285etiss_coverage_count(3, 643, 641, 642);
286} // block
287} // conditional
288etiss_coverage_count(1, 645);
289if ((val << 56ULL) == 0LL) { // conditional
290etiss_coverage_count(6, 651, 648, 646, 647, 649, 650);
291{ // block
292etiss_coverage_count(1, 658);
293res = res + 8ULL;
294etiss_coverage_count(3, 654, 652, 653);
295val = val >> 8ULL;
296etiss_coverage_count(3, 657, 655, 656);
297} // block
298} // conditional
299etiss_coverage_count(1, 659);
300if ((val << 60ULL) == 0LL) { // conditional
301etiss_coverage_count(6, 665, 662, 660, 661, 663, 664);
302{ // block
303etiss_coverage_count(1, 672);
304res = res + 4ULL;
305etiss_coverage_count(3, 668, 666, 667);
306val = val >> 4ULL;
307etiss_coverage_count(3, 671, 669, 670);
308} // block
309} // conditional
310etiss_coverage_count(1, 673);
311if ((val << 62ULL) == 0LL) { // conditional
312etiss_coverage_count(6, 679, 676, 674, 675, 677, 678);
313{ // block
314etiss_coverage_count(1, 686);
315res = res + 2ULL;
316etiss_coverage_count(3, 682, 680, 681);
317val = val >> 2ULL;
318etiss_coverage_count(3, 685, 683, 684);
319} // block
320} // conditional
321etiss_coverage_count(1, 687);
322if ((val << 63ULL) == 0LL) { // conditional
323etiss_coverage_count(6, 693, 690, 688, 689, 691, 692);
324{ // block
325etiss_coverage_count(1, 697);
326res = res + 1ULL;
327etiss_coverage_count(3, 696, 694, 695);
328} // block
329} // conditional
330etiss_coverage_count(1, 699);
331return res;
332etiss_coverage_count(1, 698);
333} // block
334}
335
336void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
337{
338cpu->return_pending = 1;
339cpu->exception = 0;
340etiss_coverage_count(1, 162);
341{ // block
342etiss_coverage_count(1, 929);
343etiss_uint32 epc = cpu->instructionPointer;
344etiss_coverage_count(2, 703, 702);
345etiss_int32 deleg = 0LL;
346etiss_coverage_count(1, 705);
347etiss_int32 vector = 0LL;
348etiss_coverage_count(1, 706);
349etiss_int32 bit = mcause;
350etiss_coverage_count(2, 708, 707);
351etiss_int32 irq2 = (mcause & 2147483648ULL) != 0LL;
352etiss_coverage_count(6, 724, 723, 720, 710, 721, 722);
353etiss_coverage_count(1, 725);
354if (irq2) { // conditional
355etiss_coverage_count(1, 726);
356{ // block
357etiss_coverage_count(1, 751);
358deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1ULL)) ? (*((RV32IMACFD*)cpu)->CSR[771ULL]) : (0LL);
359etiss_coverage_count(8, 737, 727, 736, 730, 728, 731, 734, 735);
360bit = bit & 2147483647ULL;
361etiss_coverage_count(2, 750, 738);
362} // block
363} // conditional
364else { // conditional
365{ // block
366etiss_coverage_count(1, 763);
367deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1ULL)) ? (*((RV32IMACFD*)cpu)->CSR[770ULL]) : (0LL);
368etiss_coverage_count(8, 762, 752, 761, 755, 753, 756, 759, 760);
369} // block
370} // conditional
371etiss_coverage_count(1, 764);
372if (((RV32IMACFD*)cpu)->PRIV <= 1ULL && (deleg >> bit) & 1ULL) { // conditional
373etiss_coverage_count(9, 774, 767, 765, 773, 770, 768, 769, 771, 772);
374{ // block
375etiss_coverage_count(1, 851);
376vector = ((*((RV32IMACFD*)cpu)->CSR[261ULL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
377etiss_coverage_count(13, 789, 775, 788, 783, 780, 778, 779, 781, 782, 786, 784, 785, 787);
378cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261ULL] & -2LL) + vector;
379etiss_coverage_count(7, 802, 790, 801, 798, 793, 799, 800);
380*((RV32IMACFD*)cpu)->CSR[321ULL] = epc;
381etiss_coverage_count(3, 807, 805, 806);
382*((RV32IMACFD*)cpu)->CSR[322ULL] = mcause;
383etiss_coverage_count(3, 812, 810, 811);
384etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256ULL);
385etiss_coverage_count(2, 816, 815);
386s = (etiss_uint32)(RV32IMACFD_set_field(s, 32ULL, RV32IMACFD_get_field(s, 2ULL)));
387etiss_coverage_count(7, 826, 817, 825, 823, 818, 822, 820);
388s = (etiss_uint32)(RV32IMACFD_set_field(s, 256ULL, ((RV32IMACFD*)cpu)->PRIV));
389etiss_coverage_count(6, 834, 827, 833, 831, 828, 830);
390s = (etiss_uint32)(RV32IMACFD_set_field(s, 2ULL, 0LL));
391etiss_coverage_count(6, 842, 835, 841, 839, 836, 838);
392RV32IMACFD_csr_write(cpu, system, plugin_pointers, 256ULL, s);
393etiss_coverage_count(2, 845, 844);
394((RV32IMACFD*)cpu)->PRIV = (1ULL) & 0x7ULL;
395etiss_coverage_count(2, 850, 846);
396} // block
397} // conditional
398else { // conditional
399{ // block
400etiss_coverage_count(1, 928);
401vector = ((*((RV32IMACFD*)cpu)->CSR[773ULL] & 1ULL) && irq2) ? (bit * 4ULL) : (0LL);
402etiss_coverage_count(13, 866, 852, 865, 860, 857, 855, 856, 858, 859, 863, 861, 862, 864);
403cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773ULL] & -2LL) + vector;
404etiss_coverage_count(7, 879, 867, 878, 875, 870, 876, 877);
405*((RV32IMACFD*)cpu)->CSR[833ULL] = epc;
406etiss_coverage_count(3, 884, 882, 883);
407*((RV32IMACFD*)cpu)->CSR[834ULL] = mcause;
408etiss_coverage_count(3, 889, 887, 888);
409etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768ULL);
410etiss_coverage_count(2, 893, 892);
411s = (etiss_uint32)(RV32IMACFD_set_field(s, 128ULL, RV32IMACFD_get_field(s, 8ULL)));
412etiss_coverage_count(7, 903, 894, 902, 900, 895, 899, 897);
413s = (etiss_uint32)(RV32IMACFD_set_field(s, 6144ULL, ((RV32IMACFD*)cpu)->PRIV));
414etiss_coverage_count(6, 911, 904, 910, 908, 905, 907);
415s = (etiss_uint32)(RV32IMACFD_set_field(s, 8ULL, 0LL));
416etiss_coverage_count(6, 919, 912, 918, 916, 913, 915);
417RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768ULL, s);
418etiss_coverage_count(2, 922, 921);
419((RV32IMACFD*)cpu)->PRIV = (3ULL) & 0x7ULL;
420etiss_coverage_count(2, 927, 923);
421} // block
422} // conditional
423} // block
424}
425
426void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
427{
428etiss_coverage_count(1, 163);
429{ // block
430etiss_coverage_count(1, 986);
431etiss_uint32 code = 0LL;
432etiss_coverage_count(2, 933, 932);
433etiss_coverage_count(1, 934);
434if (cause == -2147483648LL) { // conditional
435etiss_coverage_count(2, 937, 935);
436etiss_coverage_count(1, 956);
437return;
438} // conditional
439 else if (cause == -5LL) { // conditional
440etiss_coverage_count(2, 940, 938);
441code = 5ULL;
442etiss_coverage_count(2, 959, 957);
443} // conditional
444 else if (cause == -14LL) { // conditional
445etiss_coverage_count(2, 943, 941);
446code = 13ULL;
447etiss_coverage_count(2, 962, 960);
448} // conditional
449 else if (cause == -6LL) { // conditional
450etiss_coverage_count(2, 946, 944);
451code = 7ULL;
452etiss_coverage_count(2, 965, 963);
453} // conditional
454 else if (cause == -15LL) { // conditional
455etiss_coverage_count(2, 949, 947);
456code = 15ULL;
457etiss_coverage_count(2, 968, 966);
458} // conditional
459 else if (cause == -7LL) { // conditional
460etiss_coverage_count(2, 952, 950);
461code = 1ULL;
462etiss_coverage_count(2, 971, 969);
463} // conditional
464 else if (cause == -9LL) { // conditional
465etiss_coverage_count(2, 955, 953);
466{ // block
467etiss_coverage_count(1, 979);
468code = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
469etiss_coverage_count(3, 974, 972, 973);
470etiss_coverage_count(1, 975);
471if (!(code)) { // conditional
472etiss_coverage_count(2, 977, 976);
473etiss_coverage_count(1, 978);
474return;
475} // conditional
476} // block
477} // conditional
478else { // conditional
479code = 2ULL;
480etiss_coverage_count(2, 982, 980);
481} // conditional
482RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, code);
483etiss_coverage_count(3, 985, 983, 984);
484} // block
485}
486
487etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
488{
489etiss_coverage_count(1, 164);
490{ // block
491etiss_coverage_count(1, 1171);
492etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772ULL] & *((RV32IMACFD*)cpu)->CSR[836ULL];
493etiss_coverage_count(4, 995, 994, 990, 993);
494etiss_coverage_count(1, 996);
495if (!(pending_interrupts)) { // conditional
496etiss_coverage_count(2, 998, 997);
497etiss_coverage_count(1, 1000);
498return 0LL;
499etiss_coverage_count(1, 999);
500} // conditional
501etiss_uint32 mie = (etiss_uint32)(RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[768ULL], 8ULL));
502etiss_coverage_count(4, 1009, 1008, 1006, 1004);
503etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3ULL || (((RV32IMACFD*)cpu)->PRIV == 3ULL && mie);
504etiss_coverage_count(9, 1021, 1020, 1013, 1011, 1018, 1016, 1014, 1017, 1019);
505etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771ULL]) & -(m_enabled);
506etiss_coverage_count(8, 1032, 1031, 1028, 1023, 1027, 1026, 1030, 1029);
507etiss_coverage_count(1, 1033);
508if (enabled_interrupts == 0LL) { // conditional
509etiss_coverage_count(3, 1036, 1034, 1035);
510{ // block
511etiss_coverage_count(1, 1070);
512etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771ULL];
513etiss_coverage_count(2, 1041, 1040);
514etiss_uint32 sie = (etiss_uint32)(RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256ULL), 2ULL));
515etiss_coverage_count(4, 1049, 1048, 1046, 1044);
516etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1ULL || (((RV32IMACFD*)cpu)->PRIV == 1ULL && sie);
517etiss_coverage_count(9, 1061, 1060, 1053, 1051, 1058, 1056, 1054, 1057, 1059);
518enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
519etiss_coverage_count(8, 1069, 1062, 1068, 1065, 1063, 1064, 1067, 1066);
520} // block
521} // conditional
522etiss_coverage_count(1, 1071);
523if (enabled_interrupts) { // conditional
524etiss_coverage_count(1, 1072);
525{ // block
526etiss_coverage_count(1, 1168);
527etiss_coverage_count(1, 1073);
528if (enabled_interrupts >> 12ULL) { // conditional
529etiss_coverage_count(2, 1079, 1074);
530enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
531etiss_coverage_count(5, 1122, 1110, 1121, 1116, 1111);
532} // conditional
533 else if (enabled_interrupts & 2048ULL) { // conditional
534etiss_coverage_count(2, 1082, 1080);
535enabled_interrupts = 2048ULL;
536etiss_coverage_count(2, 1125, 1123);
537} // conditional
538 else if (enabled_interrupts & 8ULL) { // conditional
539etiss_coverage_count(2, 1085, 1083);
540enabled_interrupts = 8ULL;
541etiss_coverage_count(2, 1128, 1126);
542} // conditional
543 else if (enabled_interrupts & 128ULL) { // conditional
544etiss_coverage_count(2, 1088, 1086);
545enabled_interrupts = 128ULL;
546etiss_coverage_count(2, 1131, 1129);
547} // conditional
548 else if (enabled_interrupts & 512ULL) { // conditional
549etiss_coverage_count(2, 1091, 1089);
550enabled_interrupts = 512ULL;
551etiss_coverage_count(2, 1134, 1132);
552} // conditional
553 else if (enabled_interrupts & 2ULL) { // conditional
554etiss_coverage_count(2, 1094, 1092);
555enabled_interrupts = 2ULL;
556etiss_coverage_count(2, 1137, 1135);
557} // conditional
558 else if (enabled_interrupts & 32ULL) { // conditional
559etiss_coverage_count(2, 1097, 1095);
560enabled_interrupts = 32ULL;
561etiss_coverage_count(2, 1140, 1138);
562} // conditional
563 else if (enabled_interrupts & 8192ULL) { // conditional
564etiss_coverage_count(2, 1100, 1098);
565enabled_interrupts = 8192ULL;
566etiss_coverage_count(2, 1143, 1141);
567} // conditional
568 else if (enabled_interrupts & 1024ULL) { // conditional
569etiss_coverage_count(2, 1103, 1101);
570enabled_interrupts = 1024ULL;
571etiss_coverage_count(2, 1146, 1144);
572} // conditional
573 else if (enabled_interrupts & 4ULL) { // conditional
574etiss_coverage_count(2, 1106, 1104);
575enabled_interrupts = 4ULL;
576etiss_coverage_count(2, 1149, 1147);
577} // conditional
578 else if (enabled_interrupts & 64ULL) { // conditional
579etiss_coverage_count(2, 1109, 1107);
580enabled_interrupts = 64ULL;
581etiss_coverage_count(2, 1152, 1150);
582} // conditional
583else { // conditional
584etiss_coverage_count(1, 1154);
585return 0LL;
586etiss_coverage_count(1, 1153);
587} // conditional
588etiss_coverage_count(1, 1167);
589return 2147483648ULL | RV32IMACFD_ctz(enabled_interrupts);
590etiss_coverage_count(3, 1166, 1165, 1164);
591} // block
592} // conditional
593etiss_coverage_count(1, 1170);
594return 0LL;
595etiss_coverage_count(1, 1169);
596} // block
597}
598
599void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
600{
601etiss_coverage_count(1, 165);
602{ // block
603etiss_coverage_count(1, 1180);
604etiss_uint32 irq_mcause = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
605etiss_coverage_count(2, 1174, 1173);
606etiss_coverage_count(1, 1175);
607if (irq_mcause) { // conditional
608etiss_coverage_count(1, 1176);
609RV32IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
610etiss_coverage_count(3, 1179, 1177, 1178);
611} // conditional
612} // block
613}
614// clang-format on
RV32IMACFD_translate_exc_code
void RV32IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
Definition RV32IMACFDFuncs.c:426
RV32IMACFD_get_field
etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
Definition RV32IMACFDFuncs.c:223
RV32IMACFD_check_irq
void RV32IMACFD_check_irq(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:599
RV32IMACFD_set_field
etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
Definition RV32IMACFDFuncs.c:241
RV32IMACFD_csr_write
void RV32IMACFD_csr_write(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
Definition RV32IMACFDFuncs.c:184
RV32IMACFD_ctz
etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
Definition RV32IMACFDFuncs.c:252
RV32IMACFD_get_rm
etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint8 rm)
Definition RV32IMACFDFuncs.c:21
RV32IMACFD_sstatus_mask
etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:44
RV32IMACFD_mstatus_mask
etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:90
RV32IMACFD_extension_enabled
etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int8 extension)
Generated on Tue, 11 Aug 2026 12:31:38 +0000.
Definition RV32IMACFDFuncs.c:10
RV32IMACFD_calc_irq_mcause
etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition RV32IMACFDFuncs.c:487
RV32IMACFD_raise
void RV32IMACFD_raise(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
Definition RV32IMACFDFuncs.c:336
RV32IMACFD_csr_read
etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr)
Definition RV32IMACFDFuncs.c:103
s
__device__ __2f16 float bool s
Definition __clang_hip_libdevice_declares.h:298
etiss_coverage_count
#define etiss_coverage_count(...)
Definition Coverage.h:18
etiss_get_instret
etiss_uint64 etiss_get_instret(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition CSRCounters.cpp:31
etiss_get_time
etiss_uint64 etiss_get_time()
Definition CSRCounters.cpp:24
etiss_get_cycles
etiss_uint64 etiss_get_cycles(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition CSRCounters.cpp:19
etiss_uint64
uint64_t etiss_uint64
Definition types.h:58
etiss_uint32
uint32_t etiss_uint32
Definition types.h:55
etiss_int8
int8_t etiss_int8
Definition types.h:48
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_int32
int32_t etiss_int32
Definition types.h:54
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition CPU.h:54
ETISS_CPU::exception
etiss_uint32 exception
Definition CPU.h:73
ETISS_CPU::return_pending
etiss_uint32 return_pending
Definition CPU.h:74
ETISS_System
memory access and time synchronization functions.
Definition System.h:40
RV32IMACFD
Generated on Tue, 11 Aug 2026 12:31:38 +0000.
Definition RV32IMACFD.h:17
Generated on Wed Aug 12 2026 10:22:56 for ETISS 0.11.2 by doxygen 1.9.8