MMU.cpp File Reference

Modeling hardware memory management for virtual memory -> physical memory translation and protection. More...

#include "etiss/mm/MMU.h"
#include "etiss/CPUCore.h"
#include "etiss/jit/ReturnCode.h"

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Namespaces
	etiss
	Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
	etiss::mm

Functions
int32_t	etiss::mm::tlb_miss_handler (int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access)
void	etiss::mm::DUMP_MMU (MMU *mmu)
void	ETISS_SIGNAL_MMU (ETISS_CPU *cpu, etiss_uint64 mmu_signal_)

Detailed Description

Modeling hardware memory management for virtual memory -> physical memory translation and protection.

Copyright

Copyright 2018 Infineon Technologies AG

This file is part of ETISS tool, see https://github.com/tum-ei-eda/etiss.

The initial version of this software has been created with the funding support by the German Federal
Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.

Redistribution and use in source and binary forms, with or without modification, are permitted
provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and
the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
and the following disclaimer in the documentation and/or other materials provided with the distribution.

3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

Author

Aote Jin aote..nosp@m.jin@.nosp@m.tum.d.nosp@m.e, Chair of Electronic Design Automation, TUM

Date

June 24, 2018

Version

0.1 It is oriented for porting OS to ETISS.

Memory Management Unit is the key component to support OS. Modern architectures vote for TLB to speed up virtual memory address (vma) to physical memory address (pma) translation. Since vma to pma could easily become the bottleneck, it is assumed hardware managed TLB is adopted. As for software managed TLB (old design), MMU has to be modified accordingly.

Definition in file MMU.cpp.

Function Documentation

ETISS_SIGNAL_MMU()

void ETISS_SIGNAL_MMU	(	ETISS_CPU *	cpu,
		etiss_uint64	mmu_signal_
	)

Definition at line 256 of file MMU.cpp.

References ETISS_CPU::_etiss_private_handle_, etiss::ERROR, etiss::CPUCore::getMMU(), if(), and etiss::log().

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