MMU.h

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#ifndef ETISS_INCLUDE_MM_MMU_H_
#define ETISS_INCLUDE_MM_MMU_H_
 
#include "etiss/mm/PTE.h"
#include "etiss/mm/PageFaultVector.h"
#include "etiss/mm/TLB.h"
 
#include "etiss/Plugin.h"
 
namespace etiss
{
namespace mm
{
 
int32_t tlb_miss_handler(int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access);
// int32_t tlb_full_handler(int32_t fault, MMU * mmu);
 
class MMU
{
 
#define DEFAULT_PAGE_TABLE_WALKER -15
 
  public:
    explicit MMU(bool hw_ptw, std::string name, bool pid_enabled);
 
    virtual ~MMU() {}
 
    virtual int32_t Translate(const uint64_t vma, uint64_t *const pma_buf, MM_ACCESS access, uint64_t data = 0);
 
    void SignalMMU(uint64_t control_reg_val_);
 
    void Dump();
 
    void Init(ETISS_CPU *cpu, ETISS_System *system);
 
    void AddTLBEntryMap(uint64_t phy_addr_, PTE &pte);
 
    virtual bool CheckPrivilegedMode() = 0;
 
    virtual int32_t CheckProtection(const PTE &, MM_ACCESS access) = 0;
 
    virtual int32_t WalkPageTable(uint64_t, MM_ACCESS) { return DEFAULT_PAGE_TABLE_WALKER; }
 
    virtual void UpdatePTEFlags(PTE &, MM_ACCESS) {}
 
    bool IsTLBFull() const { return tlb_->IsFull(); }
 
    PTE EvictTLBEntry(const uint64_t vfn) { return tlb_->EvictPTE(vfn); }
 
    bool HasPageTableWalker() { return hw_page_table_walker_; }
 
    bool IsProcessIdEnabled() { return pid_enabled_; }
 
    void UpdatePid(uint32_t new_pid)
    {
        if (pid_enabled_)
            pid_ = new_pid;
    }
    void UpdatePid(uint32_t new_pid) {…}
 
    uint64_t GetMMUControlReg() { return mmu_control_reg_val_; }
 
    int32_t AddTLBEntry(const uint64_t vfn, const PTE &pte);
 
    std::string GetName() const { return name_; }
 
    virtual int32_t GetPid(uint64_t control_reg_val_) { return 0; }
 
    bool cache_flush_pending;
 
  protected:
    ETISS_CPU *cpu_;
    ETISS_System *system_;
    bool mmu_enabled_;
 
  private:
    // Resources in MMU
    std::shared_ptr<etiss::mm::TLB<0>> tlb_;
    // Map the virtual memory address (vma) of TLB entries to its own physical
    // location for coherence
    // NOTE: Write to TLB entries occurs rarely, so it is acceptable to evict
    //           them directly
    std::map<uint64_t, PTE *> tlb_entry_map_;
 
    uint64_t mmu_control_reg_val_;
    uint32_t pid_;
    std::string name_;
 
    const bool pid_enabled_;
    const bool hw_page_table_walker_;
};
class MMU {…};
 
void DUMP_MMU(MMU *mmu);
 
} // namespace mm
} // namespace etiss
 
#endif