ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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DMMUWrapper.h
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1
52#ifndef ETISS_INCLUDE_MM_DMMUWrapper_WRAPPER_H_
53#define ETISS_INCLUDE_MM_DMMUWrapper_WRAPPER_H_
54
55#include "etiss/ETISS.h"
56#include "etiss/Plugin.h"
57#include "etiss/mm/MMU.h"
58
59#include <sstream>
60
61namespace etiss
62{
63namespace mm
64{
65
67{
68
69 public:
70 explicit DMMUWrapper(std::shared_ptr<MMU> mmu);
71
72 virtual ~DMMUWrapper() {}
73
78
83
84 std::shared_ptr<MMU> mmu_;
85
86 protected:
87 std::string _getPluginName() const;
88};
89
97
98} // namespace mm
99} // namespace etiss
100
101#endif
Header file of the ETISS library.
Modeling hardware memory management for virtual memory -> physical memory translation and protection.
plugins for extensions to code translation and instruction execution
this plugin allows to wrap the ETISS_System interface
Definition Plugin.h:326
std::shared_ptr< MMU > mmu_
Definition DMMUWrapper.h:84
std::string _getPluginName() const
ETISS_System * unwrap(ETISS_CPU *cpu, ETISS_System *system)
SystemWrapperPlugin interface to unwrap original ETISS_System.
ETISS_System * wrap(ETISS_CPU *cpu, ETISS_System *system)
SystemWrapperPlugin interface to wrap around original ETISS_System.
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:89
memory access and time synchronization functions.
Definition System.h:78
struct ETISS_System sys
Definition DMMUWrapper.h:93