20 (uint64_t) 0xffffffff,
37 cp.
code() = std::string(
"//ECALL\n");
40cp.
code() +=
"etiss_coverage_count(1, 168);\n";
42cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
43cp.
code() +=
"{ // block\n";
45cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
46cp.
code() +=
"} // block\n";
49cp.
code() +=
"etiss_coverage_count(1, 6692);\n";
50cp.
code() +=
"{ // block\n";
52cp.
code() +=
"{ // procedure\n";
53cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
54cp.
code() +=
"etiss_coverage_count(4, 6691, 6687, 6690, 6689);\n";
56cp.
code() +=
"} // procedure\n";
58cp.
code() +=
"} // block\n";
61cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
68 cp.
code() = std::string(
"//ECALL\n");
71cp.
code() +=
"return cpu->exception;\n";
86ss <<
"ecall" <<
" # " << ba << (
" []");
96 (uint64_t) 0x30200073,
97 (uint64_t) 0xffffffff,
114 cp.
code() = std::string(
"//MRET\n");
117cp.
code() +=
"etiss_coverage_count(1, 166);\n";
119cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
120cp.
code() +=
"{ // block\n";
122cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
123cp.
code() +=
"} // block\n";
126cp.
code() +=
"etiss_coverage_count(1, 6621);\n";
127cp.
code() +=
"{ // block\n";
128cp.
code() +=
"etiss_coverage_count(1, 6548);\n";
129cp.
code() +=
"if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
130cp.
code() +=
"etiss_coverage_count(2, 6551, 6549);\n";
132cp.
code() +=
"{ // procedure\n";
133cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
134cp.
code() +=
"etiss_coverage_count(2, 6554, 6552);\n";
136cp.
code() +=
"} // procedure\n";
138cp.
code() +=
"} // conditional\n";
139cp.
code() +=
"cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";
140cp.
code() +=
"etiss_coverage_count(3, 6559, 6555, 6558);\n";
141cp.
code() +=
"etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
142cp.
code() +=
"etiss_coverage_count(2, 6563, 6562);\n";
143cp.
code() +=
"etiss_uint64 prev_prv = (etiss_uint64)(RV64IMACFD_get_field(s, 6144LL));\n";
144cp.
code() +=
"etiss_coverage_count(4, 6570, 6569, 6567, 6565);\n";
145cp.
code() +=
"etiss_coverage_count(1, 6571);\n";
146cp.
code() +=
"if (prev_prv != 3LL) { // conditional\n";
147cp.
code() +=
"etiss_coverage_count(2, 6574, 6572);\n";
148cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 131072LL, 0LL));\n";
149cp.
code() +=
"etiss_coverage_count(6, 6582, 6575, 6581, 6579, 6576, 6578);\n";
150cp.
code() +=
"} // conditional\n";
151cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL)));\n";
152cp.
code() +=
"etiss_coverage_count(7, 6592, 6583, 6591, 6589, 6584, 6588, 6586);\n";
153cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 128LL, 1ULL));\n";
154cp.
code() +=
"etiss_coverage_count(6, 6600, 6593, 6599, 6597, 6594, 6596);\n";
155cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL)));\n";
156cp.
code() +=
"etiss_coverage_count(8, 6612, 6601, 6611, 6609, 6602, 6608, 6605, 6604);\n";
157cp.
code() +=
"RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
158cp.
code() +=
"etiss_coverage_count(2, 6615, 6614);\n";
159cp.
code() +=
"((RV64IMACFD*)cpu)->PRIV = ((etiss_uint8)(prev_prv)) & 0x7ULL;\n";
160cp.
code() +=
"etiss_coverage_count(4, 6620, 6616, 6619, 6617);\n";
161cp.
code() +=
"} // block\n";
164cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
171 cp.
code() = std::string(
"//MRET\n");
174cp.
code() +=
"return cpu->exception;\n";
187 std::stringstream ss;
189ss <<
"mret" <<
" # " << ba << (
" []");
199 (uint64_t) 0x10500073,
200 (uint64_t) 0xffffffff,
217 cp.
code() = std::string(
"//WFI\n");
220cp.
code() +=
"etiss_coverage_count(1, 169);\n";
222cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
223cp.
code() +=
"{ // block\n";
225cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
226cp.
code() +=
"} // block\n";
229cp.
code() +=
"etiss_coverage_count(1, 6693);\n";
230cp.
code() +=
"{ // block\n";
231cp.
code() +=
"} // block\n";
234cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
241 cp.
code() = std::string(
"//WFI\n");
244cp.
code() +=
"return cpu->exception;\n";
257 std::stringstream ss;
259ss <<
"wfi" <<
" # " << ba << (
" []");
269 (uint64_t) 0x10200073,
270 (uint64_t) 0xffffffff,
287 cp.
code() = std::string(
"//SRET\n");
290cp.
code() +=
"etiss_coverage_count(1, 167);\n";
292cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
293cp.
code() +=
"{ // block\n";
295cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
296cp.
code() +=
"} // block\n";
299cp.
code() +=
"etiss_coverage_count(1, 6686);\n";
300cp.
code() +=
"{ // block\n";
301cp.
code() +=
"etiss_coverage_count(1, 6622);\n";
302cp.
code() +=
"if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
303cp.
code() +=
"etiss_coverage_count(6, 6632, 6623, 6630, 6627, 6625, 6631);\n";
305cp.
code() +=
"{ // procedure\n";
306cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
307cp.
code() +=
"etiss_coverage_count(2, 6635, 6633);\n";
309cp.
code() +=
"} // procedure\n";
311cp.
code() +=
"} // conditional\n";
312cp.
code() +=
"cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";
313cp.
code() +=
"etiss_coverage_count(3, 6640, 6636, 6639);\n";
314cp.
code() +=
"etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
315cp.
code() +=
"etiss_coverage_count(2, 6644, 6643);\n";
316cp.
code() +=
"etiss_uint64 prev_prv = (etiss_uint64)(RV64IMACFD_get_field(s, 256LL));\n";
317cp.
code() +=
"etiss_coverage_count(4, 6651, 6650, 6648, 6646);\n";
318cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL)));\n";
319cp.
code() +=
"etiss_coverage_count(7, 6661, 6652, 6660, 6658, 6653, 6657, 6655);\n";
320cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 32LL, 1ULL));\n";
321cp.
code() +=
"etiss_coverage_count(6, 6669, 6662, 6668, 6666, 6663, 6665);\n";
322cp.
code() +=
"s = (etiss_uint64)(RV64IMACFD_set_field(s, 256LL, 0LL));\n";
323cp.
code() +=
"etiss_coverage_count(5, 6677, 6670, 6676, 6674, 6671);\n";
324cp.
code() +=
"RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
325cp.
code() +=
"etiss_coverage_count(2, 6680, 6679);\n";
326cp.
code() +=
"((RV64IMACFD*)cpu)->PRIV = ((etiss_uint8)(prev_prv)) & 0x7ULL;\n";
327cp.
code() +=
"etiss_coverage_count(4, 6685, 6681, 6684, 6682);\n";
328cp.
code() +=
"} // block\n";
331cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
338 cp.
code() = std::string(
"//SRET\n");
341cp.
code() +=
"return cpu->exception;\n";
354 std::stringstream ss;
356ss <<
"sret" <<
" # " << ba << (
" []");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition ecall_(ISA32_RV64IMACFD, "ecall",(uint64_t) 0x000073,(uint64_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="etiss_coverage_count(1, 168);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6692);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";cp.code()+="etiss_coverage_count(4, 6691, 6687, 6690, 6689);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition sret_(ISA32_RV64IMACFD, "sret",(uint64_t) 0x10200073,(uint64_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="etiss_coverage_count(1, 167);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6686);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 6622);\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";cp.code()+="etiss_coverage_count(6, 6632, 6623, 6630, 6627, 6625, 6631);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 6635, 6633);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_coverage_count(3, 6640, 6636, 6639);\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_coverage_count(2, 6644, 6643);\n";cp.code()+="etiss_uint64 prev_prv = (etiss_uint64)(RV64IMACFD_get_field(s, 256LL));\n";cp.code()+="etiss_coverage_count(4, 6651, 6650, 6648, 6646);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL)));\n";cp.code()+="etiss_coverage_count(7, 6661, 6652, 6660, 6658, 6653, 6657, 6655);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 32LL, 1ULL));\n";cp.code()+="etiss_coverage_count(6, 6669, 6662, 6668, 6666, 6663, 6665);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 256LL, 0LL));\n";cp.code()+="etiss_coverage_count(5, 6677, 6670, 6676, 6674, 6671);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 6680, 6679);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = ((etiss_uint8)(prev_prv)) & 0x7ULL;\n";cp.code()+="etiss_coverage_count(4, 6685, 6681, 6684, 6682);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition mret_(ISA32_RV64IMACFD, "mret",(uint64_t) 0x30200073,(uint64_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="etiss_coverage_count(1, 166);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6621);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 6548);\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 6551, 6549);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 6554, 6552);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_coverage_count(3, 6559, 6555, 6558);\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_coverage_count(2, 6563, 6562);\n";cp.code()+="etiss_uint64 prev_prv = (etiss_uint64)(RV64IMACFD_get_field(s, 6144LL));\n";cp.code()+="etiss_coverage_count(4, 6570, 6569, 6567, 6565);\n";cp.code()+="etiss_coverage_count(1, 6571);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 6574, 6572);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 131072LL, 0LL));\n";cp.code()+="etiss_coverage_count(6, 6582, 6575, 6581, 6579, 6576, 6578);\n";cp.code()+="} // conditional\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL)));\n";cp.code()+="etiss_coverage_count(7, 6592, 6583, 6591, 6589, 6584, 6588, 6586);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 128LL, 1ULL));\n";cp.code()+="etiss_coverage_count(6, 6600, 6593, 6599, 6597, 6594, 6596);\n";cp.code()+="s = (etiss_uint64)(RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL)));\n";cp.code()+="etiss_coverage_count(8, 6612, 6601, 6611, 6609, 6602, 6608, 6605, 6604);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 6615, 6614);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = ((etiss_uint8)(prev_prv)) & 0x7ULL;\n";cp.code()+="etiss_coverage_count(4, 6620, 6616, 6619, 6617);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition wfi_(ISA32_RV64IMACFD, "wfi",(uint64_t) 0x10500073,(uint64_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="etiss_coverage_count(1, 169);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6693);\n";cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.