20 (uint32_t) 0xffffffff,
35 cp.
code() = std::string(
"//ECALL\n");
38cp.
code() +=
"etiss_coverage_count(1, 168);\n";
40cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
41cp.
code() +=
"{ // block\n";
43cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
44cp.
code() +=
"} // block\n";
47cp.
code() +=
"etiss_coverage_count(1, 2191);\n";
48cp.
code() +=
"{ // block\n";
50cp.
code() +=
"{ // procedure\n";
51cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
52cp.
code() +=
"etiss_coverage_count(4, 2190, 2186, 2189, 2188);\n";
54cp.
code() +=
"} // procedure\n";
56cp.
code() +=
"} // block\n";
59cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
66 cp.
code() = std::string(
"//ECALL\n");
69cp.
code() +=
"return cpu->exception;\n";
84ss <<
"ecall" <<
" # " << ba << (
" []");
94 (uint32_t) 0x30200073,
95 (uint32_t) 0xffffffff,
110 cp.
code() = std::string(
"//MRET\n");
113cp.
code() +=
"etiss_coverage_count(1, 166);\n";
115cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
116cp.
code() +=
"{ // block\n";
118cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
119cp.
code() +=
"} // block\n";
122cp.
code() +=
"etiss_coverage_count(1, 2325);\n";
123cp.
code() +=
"{ // block\n";
124cp.
code() +=
"etiss_coverage_count(1, 2264);\n";
125cp.
code() +=
"if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
126cp.
code() +=
"etiss_coverage_count(2, 2267, 2265);\n";
128cp.
code() +=
"{ // procedure\n";
129cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
130cp.
code() +=
"etiss_coverage_count(2, 2270, 2268);\n";
132cp.
code() +=
"} // procedure\n";
134cp.
code() +=
"} // conditional\n";
135cp.
code() +=
"cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";
136cp.
code() +=
"etiss_coverage_count(3, 2275, 2271, 2274);\n";
137cp.
code() +=
"etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
138cp.
code() +=
"etiss_coverage_count(2, 2279, 2278);\n";
139cp.
code() +=
"etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";
140cp.
code() +=
"etiss_coverage_count(3, 2284, 2283, 2281);\n";
141cp.
code() +=
"etiss_coverage_count(1, 2285);\n";
142cp.
code() +=
"if (prev_prv != 3LL) { // conditional\n";
143cp.
code() +=
"etiss_coverage_count(2, 2288, 2286);\n";
144cp.
code() +=
"s = RV64IMACFD_set_field(s, 131072LL, 0LL);\n";
145cp.
code() +=
"etiss_coverage_count(5, 2294, 2289, 2293, 2290, 2292);\n";
146cp.
code() +=
"} // conditional\n";
147cp.
code() +=
"s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";
148cp.
code() +=
"etiss_coverage_count(6, 2302, 2295, 2301, 2296, 2300, 2298);\n";
149cp.
code() +=
"s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";
150cp.
code() +=
"etiss_coverage_count(5, 2308, 2303, 2307, 2304, 2306);\n";
151cp.
code() +=
"s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
152cp.
code() +=
"etiss_coverage_count(7, 2318, 2309, 2317, 2310, 2316, 2313, 2312);\n";
153cp.
code() +=
"RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
154cp.
code() +=
"etiss_coverage_count(2, 2321, 2320);\n";
155cp.
code() +=
"((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
156cp.
code() +=
"etiss_coverage_count(3, 2324, 2322, 2323);\n";
157cp.
code() +=
"} // block\n";
160cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
167 cp.
code() = std::string(
"//MRET\n");
170cp.
code() +=
"return cpu->exception;\n";
183 std::stringstream ss;
185ss <<
"mret" <<
" # " << ba << (
" []");
195 (uint32_t) 0x10500073,
196 (uint32_t) 0xffffffff,
211 cp.
code() = std::string(
"//WFI\n");
214cp.
code() +=
"etiss_coverage_count(1, 169);\n";
216cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
217cp.
code() +=
"{ // block\n";
219cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
220cp.
code() +=
"} // block\n";
223cp.
code() +=
"etiss_coverage_count(1, 2326);\n";
224cp.
code() +=
"{ // block\n";
225cp.
code() +=
"} // block\n";
228cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
235 cp.
code() = std::string(
"//WFI\n");
238cp.
code() +=
"return cpu->exception;\n";
251 std::stringstream ss;
253ss <<
"wfi" <<
" # " << ba << (
" []");
263 (uint32_t) 0x10200073,
264 (uint32_t) 0xffffffff,
279 cp.
code() = std::string(
"//SRET\n");
282cp.
code() +=
"etiss_coverage_count(1, 167);\n";
284cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
285cp.
code() +=
"{ // block\n";
287cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
288cp.
code() +=
"} // block\n";
291cp.
code() +=
"etiss_coverage_count(1, 6415);\n";
292cp.
code() +=
"{ // block\n";
293cp.
code() +=
"etiss_coverage_count(1, 6361);\n";
294cp.
code() +=
"if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
295cp.
code() +=
"etiss_coverage_count(6, 6371, 6362, 6369, 6366, 6364, 6370);\n";
297cp.
code() +=
"{ // procedure\n";
298cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
299cp.
code() +=
"etiss_coverage_count(2, 6374, 6372);\n";
301cp.
code() +=
"} // procedure\n";
303cp.
code() +=
"} // conditional\n";
304cp.
code() +=
"cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";
305cp.
code() +=
"etiss_coverage_count(3, 6379, 6375, 6378);\n";
306cp.
code() +=
"etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
307cp.
code() +=
"etiss_coverage_count(2, 6383, 6382);\n";
308cp.
code() +=
"etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";
309cp.
code() +=
"etiss_coverage_count(3, 6388, 6387, 6385);\n";
310cp.
code() +=
"s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";
311cp.
code() +=
"etiss_coverage_count(6, 6396, 6389, 6395, 6390, 6394, 6392);\n";
312cp.
code() +=
"s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";
313cp.
code() +=
"etiss_coverage_count(5, 6402, 6397, 6401, 6398, 6400);\n";
314cp.
code() +=
"s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";
315cp.
code() +=
"etiss_coverage_count(4, 6408, 6403, 6407, 6404);\n";
316cp.
code() +=
"RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
317cp.
code() +=
"etiss_coverage_count(2, 6411, 6410);\n";
318cp.
code() +=
"((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
319cp.
code() +=
"etiss_coverage_count(3, 6414, 6412, 6413);\n";
320cp.
code() +=
"} // block\n";
323cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
330 cp.
code() = std::string(
"//SRET\n");
333cp.
code() +=
"return cpu->exception;\n";
346 std::stringstream ss;
348ss <<
"sret" <<
" # " << ba << (
" []");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition mret_(ISA32_RV64IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="etiss_coverage_count(1, 166);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2325);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2264);\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 2267, 2265);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2270, 2268);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_coverage_count(3, 2275, 2271, 2274);\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_coverage_count(2, 2279, 2278);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";cp.code()+="etiss_coverage_count(3, 2284, 2283, 2281);\n";cp.code()+="etiss_coverage_count(1, 2285);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 2288, 2286);\n";cp.code()+="s = RV64IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="etiss_coverage_count(5, 2294, 2289, 2293, 2290, 2292);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";cp.code()+="etiss_coverage_count(6, 2302, 2295, 2301, 2296, 2300, 2298);\n";cp.code()+="s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 2308, 2303, 2307, 2304, 2306);\n";cp.code()+="s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="etiss_coverage_count(7, 2318, 2309, 2317, 2310, 2316, 2313, 2312);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 2321, 2320);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="etiss_coverage_count(3, 2324, 2322, 2323);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition sret_(ISA32_RV64IMACFD, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="etiss_coverage_count(1, 167);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6415);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 6361);\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";cp.code()+="etiss_coverage_count(6, 6371, 6362, 6369, 6366, 6364, 6370);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 6374, 6372);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_coverage_count(3, 6379, 6375, 6378);\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_coverage_count(2, 6383, 6382);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";cp.code()+="etiss_coverage_count(3, 6388, 6387, 6385);\n";cp.code()+="s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";cp.code()+="etiss_coverage_count(6, 6396, 6389, 6395, 6390, 6394, 6392);\n";cp.code()+="s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 6402, 6397, 6401, 6398, 6400);\n";cp.code()+="s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="etiss_coverage_count(4, 6408, 6403, 6407, 6404);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 6411, 6410);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="etiss_coverage_count(3, 6414, 6412, 6413);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition wfi_(ISA32_RV64IMACFD, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="etiss_coverage_count(1, 169);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2326);\n";cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition ecall_(ISA32_RV64IMACFD, "ecall",(uint32_t) 0x000073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="etiss_coverage_count(1, 168);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2191);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";cp.code()+="etiss_coverage_count(4, 2190, 2186, 2189, 2188);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.