RV64IMACFD_tum_retInstr.cpp File Reference

#include "RV64IMACFDArch.h"
#include "RV64IMACFDFuncs.h"

Include dependency graph for RV64IMACFD_tum_retInstr.cpp:

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Variables
static InstructionDefinition	ecall_ (ISA32_RV64IMACFD, "ecall",(uint32_t) 0x000073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition	mret_ (ISA32_RV64IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition	wfi_ (ISA32_RV64IMACFD, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition	sret_ (ISA32_RV64IMACFD, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();})

Variable Documentation

ecall_

InstructionDefinition ecall_(ISA32_RV64IMACFD, "ecall",(uint32_t) 0x000073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n"); { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n"); cp.code()+="return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "ecall"<< " # "<< ba<<(" []"); return ss.str();}) ( ISA32_RV64IMACFD  , "ecall"  , (uint32_t)  0x000073, (uint32_t)  0xffffffff, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();}    )

static

mret_

InstructionDefinition mret_(ISA32_RV64IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n"); { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n"); cp.code()+="return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "mret"<< " # "<< ba<<(" []"); return ss.str();}) ( ISA32_RV64IMACFD  , "mret"  , (uint32_t)  0x30200073, (uint32_t)  0xffffffff, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();}    )

static

sret_

InstructionDefinition sret_(ISA32_RV64IMACFD, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n"); { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n"); cp.code()+="return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "sret"<< " # "<< ba<<(" []"); return ss.str();}) ( ISA32_RV64IMACFD  , "sret"  , (uint32_t)  0x10200073, (uint32_t)  0xffffffff, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";cp.code()+="s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();}    )

static

wfi_

InstructionDefinition wfi_(ISA32_RV64IMACFD, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n"); { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n"); cp.code()+="return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "wfi"<< " # "<< ba<<(" []"); return ss.str();}) ( ISA32_RV64IMACFD  , "wfi"  , (uint32_t)  0x10500073, (uint32_t)  0xffffffff, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();}    )

static