ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
main.cpp
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1 /*
2 
3  @copyright
4 
5  <pre>
6 
7  Copyright 2018 Infineon Technologies AG
8 
9  This file is part of ETISS tool, see <https://github.com/tum-ei-eda/etiss>.
10 
11  The initial version of this software has been created with the funding support by the German Federal
12  Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.
13 
14  Redistribution and use in source and binary forms, with or without modification, are permitted
15  provided that the following conditions are met:
16 
17  1. Redistributions of source code must retain the above copyright notice, this list of conditions and
18  the following disclaimer.
19 
20  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
21  and the following disclaimer in the documentation and/or other materials provided with the distribution.
22 
23  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
24  or promote products derived from this software without specific prior written permission.
25 
26  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
27  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
28  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
29  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
32  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  POSSIBILITY OF SUCH DAMAGE.
34 
35  </pre>
36 
37  @author Chair of Electronic Design Automation, TUM
38 
39  @version 0.1
40 
41 */
42 
43 #include "TracePrinter.h"
44 #include "etiss/SimpleMemSystem.h"
45 #include "etiss/ETISS.h"
46 
47 
48 int main(int argc, const char *argv[])
49 {
50  // by default etiss wil search for plugin libraries in its install path and
51  // relative to the library using the file plugins/list.txt.
52  // For loading configurations and ETISS internal plug-ins you can add a list
53  // with .ini file to the Initializer. See ETISS.ini for more details. Ini
54  // files and All configurations can be set with program arguments, too. E.g.:
55  // ./main [-o<option> <value>] [-f[no]<flag>] [-i<additionalinifile>]
56  // All arguments with this format will be evaluated by the Initializer.
57  std::cout << "=== Setting up configurations ===" << std::endl;
58  //std::list<std::string> iniFiles;
59  // iniFiles.push_back("../ETISS.ini"); // will be loaded within the run.sh
60  // iniFiles.push_back("additional.ini");
61  etiss::Initializer initializer(argc, argv); //add &iniFiles as the first argument if .ini files are loaded explicitly here
62  std::cout << "=== Finished setting up configurations ===" << std::endl << std::endl;
63 
64  std::cout << "=== Setting up test system ===" << std::endl;
65  std::cout << " Setting up Memory" << std::endl;
66 
68  dsys.init_memory();
69 
70  if (!etiss::cfg().isSet("arch.cpu")) {
71  std::cout << " CPU architecture was not set anywhere! Please set it manually using the arch.cpu configuration option!";
72  return 3;
73  }
74 
75  if (false)
76  {
77  std::list<etiss::uint32> instructions;
78  {
79  instructions.push_back(0x80b584b0); // push {r7, lr}, sub sp, #16
80  }
81  // write instructions into debug system
82  unsigned pos = 0;
83  for (auto it_instr : instructions)
84  {
85  etiss::uint8 buf[4];
86  buf[0] = it_instr >> 24;
87  buf[1] = it_instr >> 16;
88  buf[2] = it_instr >> 8;
89  buf[3] = it_instr;
90  dsys.dbg_write(pos, buf, 4);
91  pos += 4;
92  }
93  }
94 
95 
96  std::cout << " Setting up CPUCore" << std::endl;
97  // create a cpu core named core0 with the or1k architecture
98  std::string CPUArchName = etiss::cfg().get<std::string>("arch.cpu", "");
99  etiss::uint64 sa = etiss::cfg().get<uint64_t>("vp.entry_point", dsys.get_startaddr());
100  std::cout << " CPU start address: 0x" << std::hex << sa << std::dec << std::endl;
101  std::shared_ptr<etiss::CPUCore> cpu = etiss::CPUCore::create(CPUArchName, "core0");
102  if (!cpu)
103  {
104  etiss::log(etiss::FATALERROR, " Failed to create CPU core!");
105  }
106 
107  // disable timer plugin
108  cpu->setTimer(false);
109 
110  // reset CPU with a manual start address
111  cpu->reset(&sa);
112 
113  // add the virtual structure of the cpu to the VirtualStruct root. This allows
114  // to access the field of the cpu from a global context. See
115  // etiss::VirtualStruct::getVirtualStruct() and
116  // etiss::VirtualStruct::getResolvedField(). In this case e.g. the
117  // instructionPointer can be read from a global context by calling
118  // etiss::VirtualStruct::root()->getResolvedField("core0.instructionPointer")
119  // ->read().
120  etiss::VirtualStruct::root()->mountStruct("core0", cpu->getStruct());
121  std::cout << "=== Finished Setting up test system ===" << std::endl << std::endl;
122 
123  std::cout << "=== Setting up plug-ins ===" << std::endl;
124 
125  auto irq_handler = std::make_shared<etiss::InterruptHandler>(cpu->getInterruptVector(), cpu->getInterruptEnable(), cpu->getArch(), etiss::LEVEL_TRIGGERED, false);
126  cpu->addPlugin(irq_handler);
127 
128  initializer.loadIniPlugins(cpu);
129  initializer.loadIniJIT(cpu);
130  // here own developped plug-ins can be added with:
131  if (etiss::cfg().get<bool>("etiss.log_pc", false)) {
132  etiss::cfg().set<int>("etiss.max_block_size", 1);
133  cpu->addPlugin(std::shared_ptr<etiss::Plugin>(new TracePrinter(0x88888)));
134  }
135 
136  std::cout << "=== Setting up plug-ins ===" << std::endl << std::endl;
137 
138  // Simulation start
139  std::cout << std::endl << "=== Simulation start ===" << std::endl;
140  //float startTime = (float)clock() / CLOCKS_PER_SEC; // TESTING
141  // run cpu with the SimpleMemSystem (in other cases that "system" is most likely a
142  // bus that connects the cpu to memory,periphery,etc)
143  etiss_int32 exception = cpu->execute(dsys);
144  //float endTime = (float)clock() / CLOCKS_PER_SEC;
145  std::cout << "=== Simulation end ===" << std::endl << std::endl;
146 
147 
148  // print the exception code returned by the cpu core
149  std::cout << "CPU0 exited with exception: 0x" << std::hex << exception << std::dec << ": "
150  << etiss::RETURNCODE::getErrorMessages()[exception] << std::endl;
151 
152 
153  switch(exception){
154  case etiss::RETURNCODE::CPUFINISHED:
156  case etiss::RETURNCODE::CPUTERMINATED:
157  return 0;
158  break;
159  case etiss::RETURNCODE::DBUS_READ_ERROR:
160  case etiss::RETURNCODE::DBUS_WRITE_ERROR:
161  case etiss::RETURNCODE::IBUS_READ_ERROR:
162  case etiss::RETURNCODE::IBUS_WRITE_ERROR:
163  case etiss::RETURNCODE::INTERRUPT:
164  case etiss::RETURNCODE::RESET:
165  case etiss::RETURNCODE::ILLEGALINSTRUCTION:
166  case etiss::RETURNCODE::ILLEGALJUMP:
167  case etiss::RETURNCODE::INSTR_PAGEFAULT:
168  case etiss::RETURNCODE::LOAD_PAGEFAULT:
169  case etiss::RETURNCODE::STORE_PAGEFAULT:
170  case etiss::RETURNCODE::GDBNOERROR:
171  case etiss::RETURNCODE::SYSCALL:
172  case etiss::RETURNCODE::PAGEFAULT:
173  return 1;
174  break;
175  case etiss::RETURNCODE::JITERROR:
176  case etiss::RETURNCODE::JITCOMPILATIONERROR:
177  return 2;
178  break;
179  case etiss::RETURNCODE::GENERALERROR:
180  case etiss::RETURNCODE::RELOADBLOCKS:
181  case etiss::RETURNCODE::RELOADCURRENTBLOCK:
182  case etiss::RETURNCODE::BREAKPOINT:
183  case etiss::RETURNCODE::ARCHERROR:
184  case etiss::RETURNCODE::EMULATIONNOTSUPPORTED:
185  case etiss::RETURNCODE::INVALIDSYSTEM:
186  return 3;
187  break;
188  default:
189  return -1;
190  break;
191  }
192 }
193 
194 
etiss_uint8 uint8
Definition: 386-GCC.h:76
etiss_uint64 uint64
Definition: 386-GCC.h:82
Header file of the ETISS library.
simple test system implementation
static __inline__ uint64_t
Definition: arm_cde.h:31
int32_t etiss_int32
Definition: types.h:92
A simple logger dedicated to print PC trace.
Definition: TracePrinter.h:61
static std::shared_ptr< CPUCore > create(std::string archname, std::string instancename="", std::map< std::string, std::string > archoptions=std::map< std::string, std::string >())
Create a CPUCore instance.
Definition: CPUCore.cpp:249
bool set(const std::string &key, T value)
template function to set the value of a configuration key.
Definition: Misc.h:372
T get(const std::string &key, T default_, bool *default_used=0)
template function to read the value of a configuration key.
Definition: Misc.h:349
Wrapper for the initialize and shutdown of the ETISS environment.
Definition: ETISS.h:253
void loadIniPlugins(std::shared_ptr< etiss::CPUCore > cpu)
loads the plugins given with the previous loaded .ini files
Definition: ETISS.cpp:556
void loadIniJIT(std::shared_ptr< etiss::CPUCore > cpu)
sets the JIT given with the previous loaded .ini files
Definition: ETISS.cpp:665
simple etiss:System implementation for testing
etiss::uint64 get_startaddr(void)
etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug write operation.
static std::shared_ptr< VirtualStruct > root()
int main(int argc, const char *argv[])
Definition: main.cpp:48
MM_EXPORT const int32_t NOERROR
@ LEVEL_TRIGGERED
@ FATALERROR
Definition: Misc.h:126
Configuration & cfg(const std::string &cfgName)
Get reference of the global ETISS configuration object.
Definition: Misc.cpp:560
void log(Verbosity level, std::string msg)
write log message at the given level.
Definition: Misc.cpp:125