ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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SimpleMemSystem.h
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1// SPDX-License-Identifier: BSD-3-Clause
2//
3// This file is part of ETISS. It is licensed under the BSD 3-Clause License; you may not use this file except in
4// compliance with the License. You should have received a copy of the license along with this project. If not, see the
5// LICENSE file.
13#ifndef ETISS_INCLUDE_SimpleMemSystem_H_
14#define ETISS_INCLUDE_SimpleMemSystem_H_
15#include "etiss/Misc.h"
16#include "etiss/System.h"
17#include "etiss/make_unique.h"
18#include <fstream>
19#include <random>
20
21#include <cstring>
22#include <iostream>
23#include <memory>
24#include <map>
25
26namespace etiss
27{
28
30{
31 bool self_allocated_{ false };
32
33 public:
35 {
36 UNSET = 0,
37 READ = 1,
38 WRITE = 2,
39 EXEC = 4
40 };
41 /*
42 typedef enum ACCESS
43 {
44 READ,
45 WRITE,
46 } access_t;
47 */
48 etiss::uint8 *mem_;
49
50 std::string name_;
51 const etiss::uint64 start_addr_;
52 const etiss::uint64 end_addr_;
53 const etiss::uint64 size_;
55
66 MemSegment(etiss::uint64 start_addr, etiss::uint64 size, access_t mode, const std::string name,
67 etiss::uint8 *mem = nullptr, std::string initString = "", bool InitEleSet = false,
68 uint64_t randomRoot = 0);
69
70 // Can be overwritten afterwards with load_elf
71 void memInit(std::string initString, uint64_t randomRoot = 0);
72
73 virtual ~MemSegment(void)
74 {
75 if (self_allocated_ == true)
76 delete[] mem_;
77 }
78
79 void load(const void *data, size_t offset, size_t file_size_bytes);
80
81 bool addr_in_range(etiss::uint64 addr) const;
82
83 bool payload_in_range(etiss::uint64 addr, etiss::uint64 payload_size) const;
84};
85
89class SimpleMemSystem : public System
90{
91 public:
92 SimpleMemSystem(void);
93
94 virtual ~SimpleMemSystem(void)
95 {
96 for (auto &mseg : msegs_)
97 mseg.reset();
98 }
99 // memory access
100 etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len);
101 etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
102 etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
103 etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
104 etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
105 etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
106
107 // sync time
108 void syncTime(ETISS_CPU *cpu);
109
110 void init_memory();
111 void load_elf();
112 void load_segments(void);
113 etiss::uint64 get_startaddr(void) { return (start_addr_); }
114 void add_memsegment(std::unique_ptr<MemSegment> &mseg, const void *raw_data, size_t file_size_bytes);
115
116 protected:
117 template <bool write>
118 etiss::int32 dbus_access(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
119
120 private:
121 std::vector<std::unique_ptr<MemSegment>> msegs_{};
122
123 etiss::uint64 start_addr_{ 0 };
124
126 {
127 find_fitting_mseg(uint64 addr, uint64 size) : addr(addr), size(size) {}
128 bool operator()(const std::unique_ptr<MemSegment> &mseg) { return mseg->payload_in_range(addr, size); }
129
130 private:
131 uint64 addr, size;
132 };
133
138
140
142
143 std::ofstream trace_file_dbus_;
144
145 std::map<etiss::uint64, etiss::uint64> configured_address_spaces_;
146};
147
148} // namespace etiss
149
150void access_error(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len, std::string error, etiss::Verbosity verbosity);
151#endif
general configuration and logging
void access_error(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len, std::string error, etiss::Verbosity verbosity)
static __inline__ uint64_t
Definition arm_cde.h:31
bool payload_in_range(etiss::uint64 addr, etiss::uint64 payload_size) const
void memInit(std::string initString, uint64_t randomRoot=0)
bool addr_in_range(etiss::uint64 addr) const
const etiss::uint64 start_addr_
virtual ~MemSegment(void)
const etiss::uint64 end_addr_
void load(const void *data, size_t offset, size_t file_size_bytes)
const etiss::uint64 size_
etiss::uint8 * mem_
simple etiss:System implementation for testing
virtual ~SimpleMemSystem(void)
std::map< etiss::uint64, etiss::uint64 > configured_address_spaces_
etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data read operation.
std::vector< std::unique_ptr< MemSegment > > msegs_
etiss::uint64 get_startaddr(void)
etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data write operation.
etiss::int32 dbus_access(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
void add_memsegment(std::unique_ptr< MemSegment > &mseg, const void *raw_data, size_t file_size_bytes)
etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug write operation.
etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug read operation.
etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)
Instruction read operation.
etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Instruction write operation.
std::ofstream trace_file_dbus_
void syncTime(ETISS_CPU *cpu)
Synchronize simulation time.
System Interface for the basic system IO operations and time synchronization.
Definition System.h:38
conatins a convinience class that can be wrapped as a ETISS_System structure
forwards: include/jit/*
Definition Benchmark.h:17
Verbosity
Enumeration type for the log levels.
Definition Misc.h:82
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
bool operator()(const std::unique_ptr< MemSegment > &mseg)
find_fitting_mseg(uint64 addr, uint64 size)