13#ifndef ETISS_INCLUDE_SimpleMemSystem_H_
14#define ETISS_INCLUDE_SimpleMemSystem_H_
66 MemSegment(etiss::uint64 start_addr, etiss::uint64 size,
access_t mode,
const std::string name,
67 etiss::uint8 *mem =
nullptr, std::string initString =
"",
bool InitEleSet =
false,
79 void load(
const void *data,
size_t offset,
size_t file_size_bytes);
100 etiss::int32
iread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len);
101 etiss::int32
iwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
102 etiss::int32
dread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
103 etiss::int32
dwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
104 etiss::int32
dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
105 etiss::int32
dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
114 void add_memsegment(std::unique_ptr<MemSegment> &mseg,
const void *raw_data,
size_t file_size_bytes);
117 template <
bool write>
118 etiss::int32
dbus_access(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
121 std::vector<std::unique_ptr<MemSegment>>
msegs_{};
128 bool operator()(
const std::unique_ptr<MemSegment> &mseg) {
return mseg->payload_in_range(
addr,
size); }
general configuration and logging
void access_error(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len, std::string error, etiss::Verbosity verbosity)
static __inline__ uint64_t
bool payload_in_range(etiss::uint64 addr, etiss::uint64 payload_size) const
void memInit(std::string initString, uint64_t randomRoot=0)
bool addr_in_range(etiss::uint64 addr) const
const etiss::uint64 start_addr_
virtual ~MemSegment(void)
const etiss::uint64 end_addr_
void load(const void *data, size_t offset, size_t file_size_bytes)
const etiss::uint64 size_
simple etiss:System implementation for testing
virtual ~SimpleMemSystem(void)
etiss::uint64 start_addr_
std::map< etiss::uint64, etiss::uint64 > configured_address_spaces_
etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data read operation.
bool error_on_seg_mismatch_
std::vector< std::unique_ptr< MemSegment > > msegs_
etiss::uint64 get_startaddr(void)
etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data write operation.
etiss::int32 dbus_access(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
void add_memsegment(std::unique_ptr< MemSegment > &mseg, const void *raw_data, size_t file_size_bytes)
bool print_dbgbus_access_
etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug write operation.
etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug read operation.
etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)
Instruction read operation.
etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Instruction write operation.
std::ofstream trace_file_dbus_
void syncTime(ETISS_CPU *cpu)
Synchronize simulation time.
System Interface for the basic system IO operations and time synchronization.
conatins a convinience class that can be wrapped as a ETISS_System structure
Verbosity
Enumeration type for the log levels.
basic cpu state structure needed for execution of any cpu architecture.
bool operator()(const std::unique_ptr< MemSegment > &mseg)
find_fitting_mseg(uint64 addr, uint64 size)