ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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SimpleMemSystem.h
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1
51#ifndef ETISS_INCLUDE_SimpleMemSystem_H_
52#define ETISS_INCLUDE_SimpleMemSystem_H_
53#include "etiss/System.h"
54#include "etiss/make_unique.h"
55#include <fstream>
56#include <random>
57
58#include <cstring>
59#include <iostream>
60#include <memory>
61#include <map>
62
63namespace etiss
64{
65
67{
68 bool self_allocated_{ false };
69
70 public:
71 enum access_t {
72 UNSET = 0,
73 READ = 1,
74 WRITE = 2,
75 EXEC = 4
76 };
77 /*
78 typedef enum ACCESS
79 {
80 READ,
81 WRITE,
82 } access_t;
83 */
84 etiss::uint8 *mem_;
85
86 std::string name_;
87 const etiss::uint64 start_addr_;
88 const etiss::uint64 end_addr_;
89 const etiss::uint64 size_;
91
101 MemSegment(etiss::uint64 start_addr, etiss::uint64 size, access_t mode, const std::string name,
102 etiss::uint8 *mem = nullptr, std::string initString = "", bool InitEleSet = false, uint64_t randomRoot = 0);
103
104 // Can be overwritten afterwards with load_elf
105 void memInit(std::string initString, uint64_t randomRoot = 0);
106
107 virtual ~MemSegment(void)
108 {
109 if (self_allocated_ == true)
110 delete[] mem_;
111 }
112
113 void load(const void *data, size_t offset, size_t file_size_bytes);
114
115 bool addr_in_range(etiss::uint64 addr) const;
116
117 bool payload_in_range(etiss::uint64 addr, etiss::uint64 payload_size) const;
118};
119
124{
125 public:
126 SimpleMemSystem(void);
127
128 virtual ~SimpleMemSystem(void)
129 {
130 for (auto &mseg : msegs_)
131 mseg.reset();
132 }
133 // memory access
134 etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len);
135 etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
136 etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
137 etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
138 etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
139 etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
140
141 // sync time
142 void syncTime(ETISS_CPU *cpu);
143
144 void init_memory();
145 void load_elf();
146 void load_segments(void);
147 etiss::uint64 get_startaddr(void) { return (start_addr_); }
148 void add_memsegment(std::unique_ptr<MemSegment>& mseg, const void *raw_data, size_t file_size_bytes);
149
150 private:
151 std::vector<std::unique_ptr<MemSegment>> msegs_{};
152
153 template <bool write>
154 etiss::int32 dbus_access(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
155
156 etiss::uint64 start_addr_{ 0 };
157
160 bool operator() (const std::unique_ptr<MemSegment> & mseg) { return mseg->payload_in_range(addr, size); }
161 private:
163 };
164
169
171
173
174 std::ofstream trace_file_dbus_;
175
176 std::map<etiss::uint64, etiss::uint64> configured_address_spaces_;
177};
178
179} // namespace etiss
180
181#endif
etiss_uint64 uint64
Definition 386-GCC.h:82
static __inline__ uint64_t
Definition arm_cde.h:31
bool payload_in_range(etiss::uint64 addr, etiss::uint64 payload_size) const
void memInit(std::string initString, uint64_t randomRoot=0)
bool addr_in_range(etiss::uint64 addr) const
const etiss::uint64 start_addr_
virtual ~MemSegment(void)
const etiss::uint64 end_addr_
void load(const void *data, size_t offset, size_t file_size_bytes)
const etiss::uint64 size_
etiss::uint8 * mem_
simple etiss:System implementation for testing
virtual ~SimpleMemSystem(void)
std::map< etiss::uint64, etiss::uint64 > configured_address_spaces_
etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data read operation.
std::vector< std::unique_ptr< MemSegment > > msegs_
etiss::uint64 get_startaddr(void)
etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data write operation.
etiss::int32 dbus_access(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
void add_memsegment(std::unique_ptr< MemSegment > &mseg, const void *raw_data, size_t file_size_bytes)
etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug write operation.
etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug read operation.
etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)
Instruction read operation.
etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Instruction write operation.
std::ofstream trace_file_dbus_
void syncTime(ETISS_CPU *cpu)
Synchronize simulation time.
System Interface for the basic system IO operations and time synchronization.
Definition System.h:77
conatins a convinience class that can be wrapped as a ETISS_System structure
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:89
bool operator()(const std::unique_ptr< MemSegment > &mseg)
find_fitting_mseg(uint64 addr, uint64 size)