15#ifndef ETISS_INCLUDE_SYSTEM_H_
16#define ETISS_INCLUDE_SYSTEM_H_
19#include "etiss/jit/ReturnCode.h"
62 virtual etiss::int32
iread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len) = 0;
86 virtual etiss::int32
iwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
105 virtual etiss::int32
dread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
124 virtual etiss::int32
dwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
144 virtual etiss::int32
dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
161 virtual etiss::int32
dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
185 virtual etiss::int32
iread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len);
186 virtual etiss::int32
iwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
187 virtual etiss::int32
dread(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
188 virtual etiss::int32
dwrite(
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
189 virtual etiss::int32
dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
190 virtual etiss::int32
dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len);
193 virtual bool read(
bool debug,
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
194 virtual bool write(
bool debug,
ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len) = 0;
general configuration and logging
A simple system, that implements the etiss::System interface.
virtual etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data read operation.
virtual etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Data write operation.
virtual etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)
Instruction read operation.
virtual bool write(bool debug, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
virtual etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug read operation.
virtual etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Debug write operation.
virtual bool read(bool debug, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
virtual etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
Instruction write operation.
virtual void syncTime(ETISS_CPU *cpu)
Synchronize simulation time.
System Interface for the basic system IO operations and time synchronization.
virtual void syncTime(ETISS_CPU *cpu)=0
Synchronize simulation time.
virtual etiss::int32 dbg_write(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
Debug write operation.
virtual etiss::int32 dbg_read(etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
Debug read operation.
virtual etiss::int32 iwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
Instruction write operation.
virtual etiss::int32 iread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)=0
Instruction read operation.
virtual etiss::int32 dwrite(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
Data write operation.
virtual etiss::int32 dread(ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)=0
Data read operation.
std::shared_ptr< ETISS_System > wrap(etiss::System *sys)
wraps a etiss::System in a ETISS_System structure.
basic cpu state structure needed for execution of any cpu architecture.