RV64IMACFD_tum_semihostingInstr.cpp File Reference

#include "RV64IMACFDArch.h"
#include "RV64IMACFDFuncs.h"

Include dependency graph for RV64IMACFD_tum_semihostingInstr.cpp:

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Variables
static InstructionDefinition	ebreak_ (ISA32_RV64IMACFD, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="etiss_coverage_count(1, 183);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2263);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2192);\n";cp.code()+="if (etiss_semihost_enabled()) { // conditional\n";cp.code()+="etiss_coverage_count(1, 2193);\n";{ cp.code()+="etiss_coverage_count(1, 2258);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_ - 4ULL)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+0LL)+"LL, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";cp.code()+="etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";cp.code()+="etiss_uint32 mem_val_2;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+4ULL)+"ULL, (etiss_uint8*)&mem_val_2, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";cp.code()+="etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";cp.code()+="etiss_coverage_count(1, 2221);\n";cp.code()+="if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";{ cp.code()+="etiss_coverage_count(1, 2253);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";cp.code()+="etiss_coverage_count(3, 2237, 2236, 2235);\n";cp.code()+="etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";cp.code()+="etiss_coverage_count(3, 2242, 2241, 2240);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";cp.code()+="etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2257);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2256, 2254);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2262);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2261, 2259);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ebreak"<< " # "<< ba<<(" []");return ss.str();})

Variable Documentation

ebreak_

InstructionDefinition ebreak_(ISA32_RV64IMACFD, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//EBREAK\n"); cp.code()+="etiss_coverage_count(1, 183);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2263);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2192);\n";cp.code()+="if (etiss_semihost_enabled()) { // conditional\n";cp.code()+="etiss_coverage_count(1, 2193);\n";{ cp.code()+="etiss_coverage_count(1, 2258);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_ - 4ULL)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+0LL)+"LL, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";cp.code()+="etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";cp.code()+="etiss_uint32 mem_val_2;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+4ULL)+"ULL, (etiss_uint8*)&mem_val_2, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";cp.code()+="etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";cp.code()+="etiss_coverage_count(1, 2221);\n";cp.code()+="if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";{ cp.code()+="etiss_coverage_count(1, 2253);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";cp.code()+="etiss_coverage_count(3, 2237, 2236, 2235);\n";cp.code()+="etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";cp.code()+="etiss_coverage_count(3, 2242, 2241, 2240);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";cp.code()+="etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2257);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2256, 2254);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2262);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2261, 2259);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//EBREAK\n"); cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "ebreak"<< " # "<< ba<<(" []"); return ss.str();}) ( ISA32_RV64IMACFD  , "ebreak"  , (uint32_t)  0x100073, (uint32_t)  0xffffffff, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="etiss_coverage_count(1, 183);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2263);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2192);\n";cp.code()+="if (etiss_semihost_enabled()) { // conditional\n";cp.code()+="etiss_coverage_count(1, 2193);\n";{ cp.code()+="etiss_coverage_count(1, 2258);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_ - 4ULL)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+0LL)+"LL, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";cp.code()+="etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";cp.code()+="etiss_uint32 mem_val_2;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+4ULL)+"ULL, (etiss_uint8*)&mem_val_2, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";cp.code()+="etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";cp.code()+="etiss_coverage_count(1, 2221);\n";cp.code()+="if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";{ cp.code()+="etiss_coverage_count(1, 2253);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";cp.code()+="etiss_coverage_count(3, 2237, 2236, 2235);\n";cp.code()+="etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";cp.code()+="etiss_coverage_count(3, 2242, 2241, 2240);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";cp.code()+="etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2257);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2256, 2254);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2262);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2261, 2259);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ebreak"<< " # "<< ba<<(" []");return ss.str();}    )

static