ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFDFuncs.h
Go to the documentation of this file.
1 
7 #ifndef __RV64IMACFD_FUNCS_H
8 #define __RV64IMACFD_FUNCS_H
9 
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 #include "RV64IMACFD.h"
15 #include "etiss/jit/CPU.h"
16 #include "etiss/jit/System.h"
17 #include "etiss/jit/ReturnCode.h"
18 #include "etiss/jit/Coverage.h"
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21 void leave(etiss_int32 priv_lvl);
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25 etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
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55 etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
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83 etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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87 etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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89 etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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91 etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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93 etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
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95 void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
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103 void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
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105 void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
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107 etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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109 void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
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119 etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
120 
121 #ifdef __cplusplus
122 }
123 #endif
124 
125 #endif
char flag
Definition: 386-GCC.h:75
etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8)
etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8)
void leave(etiss_int32 priv_lvl)
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8)
etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8)
etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32)
void RV64IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y)
etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32)
etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint32 unbox_s(etiss_uint64)
etiss_uint64 etiss_get_instret(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: CSRCounters.cpp:26
void wait(etiss_int32 flag)
etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr)
etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8)
etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint64 etiss_get_time()
Definition: CSRCounters.cpp:18
etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8)
void RV64IMACFD_csr_write(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
etiss_uint8 etiss_semihost_enabled()
Checks whether semihosting is enabled in the config.
Definition: semihost.cpp:43
etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8)
etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int8 extension)
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss_uint32 fclass_s(etiss_uint32)
etiss_uint64 etiss_get_cycles(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
Definition: CSRCounters.cpp:13
etiss_uint32 fget_flags()
etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8)
void RV64IMACFD_check_irq(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y)
etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32)
etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y)
etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32)
etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val)
void RV64IMACFD_raise(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint8 rm)
etiss_int64 etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter)
Executes the semihosting call based on the operation number.
Definition: semihost.cpp:48
etiss_uint64 fclass_d(etiss_uint64)
etiss_uint64 unbox_d(etiss_uint64)
etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8)
uint64_t etiss_uint64
Definition: types.h:96
uint32_t etiss_uint32
Definition: types.h:93
int64_t etiss_int64
Definition: types.h:95
int8_t etiss_int8
Definition: types.h:86
uint8_t etiss_uint8
Definition: types.h:87
int32_t etiss_int32
Definition: types.h:92
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
memory access and time synchronization functions.
Definition: System.h:78