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RV64IMACFD_tum_semihostingInstr.cpp
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1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// EBREAK ----------------------------------------------------------------------
16static InstructionDefinition ebreak_ (
17 ISA32_RV64IMACFD,
18 "ebreak",
19 (uint32_t) 0x100073,
20 (uint32_t) 0xffffffff,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29
30// -----------------------------------------------------------------------------
31
32 {
33 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
34
35 cp.code() = std::string("//EBREAK\n");
36
37// -----------------------------------------------------------------------------
38cp.code() += "etiss_coverage_count(1, 183);\n";
39{ // block
40cp.code() += "etiss_coverage_count(1, 1169);\n";
41cp.code() += "{ // block\n";
42cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
43cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
44cp.code() += "} // block\n";
45} // block
46{ // block
47cp.code() += "etiss_coverage_count(1, 2263);\n";
48cp.code() += "{ // block\n";
49cp.code() += "etiss_coverage_count(1, 2192);\n";
50cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";
51cp.code() += "etiss_coverage_count(1, 2193);\n";
52{ // block
53cp.code() += "etiss_coverage_count(1, 2258);\n";
54cp.code() += "{ // block\n";
55cp.code() += "etiss_uint32 mem_val_0;\n";
56cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
57cp.code() += "if (cpu->exception) { // conditional\n";
58{ // procedure
59cp.code() += "{ // procedure\n";
60cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
61cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
62cp.code() += "} // procedure\n";
63} // procedure
64cp.code() += "} // conditional\n";
65cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
66cp.code() += "etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";
67cp.code() += "etiss_uint32 mem_val_1;\n";
68cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0LL) + "LL, (etiss_uint8*)&mem_val_1, 4);\n";
69cp.code() += "if (cpu->exception) { // conditional\n";
70{ // procedure
71cp.code() += "{ // procedure\n";
72cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
73cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
74cp.code() += "} // procedure\n";
75} // procedure
76cp.code() += "} // conditional\n";
77cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
78cp.code() += "etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";
79cp.code() += "etiss_uint32 mem_val_2;\n";
80cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n";
81cp.code() += "if (cpu->exception) { // conditional\n";
82{ // procedure
83cp.code() += "{ // procedure\n";
84cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
85cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
86cp.code() += "} // procedure\n";
87} // procedure
88cp.code() += "} // conditional\n";
89cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
90cp.code() += "etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";
91cp.code() += "etiss_coverage_count(1, 2221);\n";
92cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";
93cp.code() += "etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";
94{ // block
95cp.code() += "etiss_coverage_count(1, 2253);\n";
96cp.code() += "{ // block\n";
97cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";
98cp.code() += "etiss_coverage_count(3, 2237, 2236, 2235);\n";
99cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";
100cp.code() += "etiss_coverage_count(3, 2242, 2241, 2240);\n";
101cp.code() += "*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";
102cp.code() += "etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";
103cp.code() += "} // block\n";
104} // block
105cp.code() += "} // conditional\n";
106cp.code() += "else { // conditional\n";
107{ // block
108cp.code() += "etiss_coverage_count(1, 2257);\n";
109cp.code() += "{ // block\n";
110{ // procedure
111cp.code() += "{ // procedure\n";
112cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
113cp.code() += "etiss_coverage_count(2, 2256, 2254);\n";
114cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
115cp.code() += "} // procedure\n";
116} // procedure
117cp.code() += "} // block\n";
118} // block
119cp.code() += "} // conditional\n";
120cp.code() += "} // block\n";
121} // block
122cp.code() += "} // conditional\n";
123cp.code() += "else { // conditional\n";
124{ // block
125cp.code() += "etiss_coverage_count(1, 2262);\n";
126cp.code() += "{ // block\n";
127{ // procedure
128cp.code() += "{ // procedure\n";
129cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
130cp.code() += "etiss_coverage_count(2, 2261, 2259);\n";
131cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
132cp.code() += "} // procedure\n";
133} // procedure
134cp.code() += "} // block\n";
135} // block
136cp.code() += "} // conditional\n";
137cp.code() += "} // block\n";
138} // block
139cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
140cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
141// -----------------------------------------------------------------------------
142 cp.getAffectedRegisters().add("instructionPointer", 32);
143 }
144 {
145 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
146
147 cp.code() = std::string("//EBREAK\n");
148
149// -----------------------------------------------------------------------------
150cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
151// -----------------------------------------------------------------------------
152 }
153
154 return true;
155 },
156 0,
157 [] (BitArray & ba, Instruction & instr)
158 {
159// -----------------------------------------------------------------------------
160
161// -----------------------------------------------------------------------------
162
163 std::stringstream ss;
164// -----------------------------------------------------------------------------
165ss << "ebreak" << " # " << ba << (" []");
166// -----------------------------------------------------------------------------
167 return ss.str();
168 }
169);
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
ebreak_
static InstructionDefinition ebreak_(ISA32_RV64IMACFD, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="etiss_coverage_count(1, 183);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2263);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2192);\n";cp.code()+="if (etiss_semihost_enabled()) { // conditional\n";cp.code()+="etiss_coverage_count(1, 2193);\n";{ cp.code()+="etiss_coverage_count(1, 2258);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_ - 4ULL)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+0LL)+"LL, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";cp.code()+="etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";cp.code()+="etiss_uint32 mem_val_2;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+4ULL)+"ULL, (etiss_uint8*)&mem_val_2, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";cp.code()+="etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";cp.code()+="etiss_coverage_count(1, 2221);\n";cp.code()+="if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";{ cp.code()+="etiss_coverage_count(1, 2253);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";cp.code()+="etiss_coverage_count(3, 2237, 2236, 2235);\n";cp.code()+="etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";cp.code()+="etiss_coverage_count(3, 2242, 2241, 2240);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";cp.code()+="etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2257);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2256, 2254);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2262);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2261, 2259);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ebreak"<< " # "<< ba<<(" []");return ss.str();})
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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