ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_tum_semihostingInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // EBREAK ----------------------------------------------------------------------
16 static InstructionDefinition ebreak_ (
17  ISA32_RV64IMACFD,
18  "ebreak",
19  (uint32_t) 0x100073,
20  (uint32_t) 0xffffffff,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 
30 // -----------------------------------------------------------------------------
31 
32  {
33  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
34 
35  cp.code() = std::string("//EBREAK\n");
36 
37 // -----------------------------------------------------------------------------
38 cp.code() += "etiss_coverage_count(1, 183);\n";
39 { // block
40 cp.code() += "etiss_coverage_count(1, 1169);\n";
41 cp.code() += "{ // block\n";
42 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
43 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
44 cp.code() += "} // block\n";
45 } // block
46 { // block
47 cp.code() += "etiss_coverage_count(1, 2263);\n";
48 cp.code() += "{ // block\n";
49 cp.code() += "etiss_coverage_count(1, 2192);\n";
50 cp.code() += "if (etiss_semihost_enabled()) { // conditional\n";
51 cp.code() += "etiss_coverage_count(1, 2193);\n";
52 { // block
53 cp.code() += "etiss_coverage_count(1, 2258);\n";
54 cp.code() += "{ // block\n";
55 cp.code() += "etiss_uint32 mem_val_0;\n";
56 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
57 cp.code() += "if (cpu->exception) { // conditional\n";
58 { // procedure
59 cp.code() += "{ // procedure\n";
60 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
61 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
62 cp.code() += "} // procedure\n";
63 } // procedure
64 cp.code() += "} // conditional\n";
65 cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";
66 cp.code() += "etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";
67 cp.code() += "etiss_uint32 mem_val_1;\n";
68 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0LL) + "LL, (etiss_uint8*)&mem_val_1, 4);\n";
69 cp.code() += "if (cpu->exception) { // conditional\n";
70 { // procedure
71 cp.code() += "{ // procedure\n";
72 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
73 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
74 cp.code() += "} // procedure\n";
75 } // procedure
76 cp.code() += "} // conditional\n";
77 cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";
78 cp.code() += "etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";
79 cp.code() += "etiss_uint32 mem_val_2;\n";
80 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n";
81 cp.code() += "if (cpu->exception) { // conditional\n";
82 { // procedure
83 cp.code() += "{ // procedure\n";
84 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
85 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
86 cp.code() += "} // procedure\n";
87 } // procedure
88 cp.code() += "} // conditional\n";
89 cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";
90 cp.code() += "etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";
91 cp.code() += "etiss_coverage_count(1, 2221);\n";
92 cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";
93 cp.code() += "etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";
94 { // block
95 cp.code() += "etiss_coverage_count(1, 2253);\n";
96 cp.code() += "{ // block\n";
97 cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";
98 cp.code() += "etiss_coverage_count(3, 2237, 2236, 2235);\n";
99 cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";
100 cp.code() += "etiss_coverage_count(3, 2242, 2241, 2240);\n";
101 cp.code() += "*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";
102 cp.code() += "etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";
103 cp.code() += "} // block\n";
104 } // block
105 cp.code() += "} // conditional\n";
106 cp.code() += "else { // conditional\n";
107 { // block
108 cp.code() += "etiss_coverage_count(1, 2257);\n";
109 cp.code() += "{ // block\n";
110 { // procedure
111 cp.code() += "{ // procedure\n";
112 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
113 cp.code() += "etiss_coverage_count(2, 2256, 2254);\n";
114 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
115 cp.code() += "} // procedure\n";
116 } // procedure
117 cp.code() += "} // block\n";
118 } // block
119 cp.code() += "} // conditional\n";
120 cp.code() += "} // block\n";
121 } // block
122 cp.code() += "} // conditional\n";
123 cp.code() += "else { // conditional\n";
124 { // block
125 cp.code() += "etiss_coverage_count(1, 2262);\n";
126 cp.code() += "{ // block\n";
127 { // procedure
128 cp.code() += "{ // procedure\n";
129 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
130 cp.code() += "etiss_coverage_count(2, 2261, 2259);\n";
131 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
132 cp.code() += "} // procedure\n";
133 } // procedure
134 cp.code() += "} // block\n";
135 } // block
136 cp.code() += "} // conditional\n";
137 cp.code() += "} // block\n";
138 } // block
139 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
140 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
141 // -----------------------------------------------------------------------------
142  cp.getAffectedRegisters().add("instructionPointer", 32);
143  }
144  {
145  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
146 
147  cp.code() = std::string("//EBREAK\n");
148 
149 // -----------------------------------------------------------------------------
150 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
151 // -----------------------------------------------------------------------------
152  }
153 
154  return true;
155  },
156  0,
157  [] (BitArray & ba, Instruction & instr)
158  {
159 // -----------------------------------------------------------------------------
160 
161 // -----------------------------------------------------------------------------
162 
163  std::stringstream ss;
164 // -----------------------------------------------------------------------------
165 ss << "ebreak" << " # " << ba << (" []");
166 // -----------------------------------------------------------------------------
167  return ss.str();
168  }
169 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
ebreak_
static InstructionDefinition ebreak_(ISA32_RV64IMACFD, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="etiss_coverage_count(1, 183);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2263);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2192);\n";cp.code()+="if (etiss_semihost_enabled()) { // conditional\n";cp.code()+="etiss_coverage_count(1, 2193);\n";{ cp.code()+="etiss_coverage_count(1, 2258);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_ - 4ULL)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 2202, 2201, 2199, 2198, 2196, 2197);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+0LL)+"LL, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n";cp.code()+="etiss_coverage_count(6, 2211, 2210, 2208, 2207, 2205, 2206);\n";cp.code()+="etiss_uint32 mem_val_2;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, "+std::to_string(ic.current_address_+4ULL)+"ULL, (etiss_uint8*)&mem_val_2, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 post = (etiss_uint32)(mem_val_2);\n";cp.code()+="etiss_coverage_count(6, 2220, 2219, 2217, 2216, 2214, 2215);\n";cp.code()+="etiss_coverage_count(1, 2221);\n";cp.code()+="if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2232, 2228, 2224, 2222, 2223, 2227, 2225, 2226, 2231, 2229, 2230);\n";{ cp.code()+="etiss_coverage_count(1, 2253);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n";cp.code()+="etiss_coverage_count(3, 2237, 2236, 2235);\n";cp.code()+="etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n";cp.code()+="etiss_coverage_count(3, 2242, 2241, 2240);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n";cp.code()+="etiss_coverage_count(7, 2252, 2245, 2244, 2251, 2249, 2247, 2248);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2257);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2256, 2254);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 2262);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2261, 2259);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//EBREAK\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ebreak"<< " # "<< ba<<(" []");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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