ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
Variables
RV64IMACFD_tum_csrInstr.cpp File Reference
#include "RV64IMACFDArch.h"
#include "RV64IMACFDFuncs.h"
Include dependency graph for RV64IMACFD_tum_csrInstr.cpp:

Go to the source code of this file.

Variables

static InstructionDefinition csrrw_rd_rs1_csr (ISA32_RV64IMACFD, "csrrw",(uint32_t) 0x001073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRW\n");cp.code()+="etiss_coverage_count(1, 153);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3249);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3222, 3221, 3220, 3218);\n";cp.code()+="etiss_coverage_count(1, 3223);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3229, 3226, 3224, 3227, 3228);\n";{ cp.code()+="etiss_coverage_count(1, 3244);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3233, 3232, 3231);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3236, 3234, 3235);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3243, 3241, 3240, 3238, 3242);\n";cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 3248);\n";cp.code()+="{ // block\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3247, 3245, 3246);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 
static InstructionDefinition csrrs_rd_rs1_csr (ISA32_RV64IMACFD, "csrrs",(uint32_t) 0x002073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRS\n");cp.code()+="etiss_coverage_count(1, 154);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3284);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3253, 3252, 3251);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3260, 3259, 3258, 3256);\n";cp.code()+="etiss_coverage_count(1, 3261);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3264, 3262, 3263);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | xrs1);\n";cp.code()+="etiss_coverage_count(5, 3269, 3265, 3268, 3266, 3267);\n";} cp.code()+="etiss_coverage_count(1, 3270);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3276, 3273, 3271, 3274, 3275);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3283, 3281, 3280, 3278, 3282);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrs"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 
static InstructionDefinition csrrc_rd_rs1_csr (ISA32_RV64IMACFD, "csrrc",(uint32_t) 0x003073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRC\n");cp.code()+="etiss_coverage_count(1, 155);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3288, 3287, 3286);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3295, 3294, 3293, 3291);\n";cp.code()+="etiss_coverage_count(1, 3296);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3299, 3297, 3298);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & ~(xrs1));\n";cp.code()+="etiss_coverage_count(6, 3305, 3300, 3304, 3301, 3303, 3302);\n";} cp.code()+="etiss_coverage_count(1, 3306);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3312, 3309, 3307, 3310, 3311);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3319, 3317, 3316, 3314, 3318);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 
static InstructionDefinition csrrwi_rd_zimm_csr (ISA32_RV64IMACFD, "csrrwi",(uint32_t) 0x005073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRWI\n");cp.code()+="etiss_coverage_count(1, 156);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3344);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3324, 3323, 3322);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(4, 3329, 3325, 3328, 3326);\n";cp.code()+="etiss_coverage_count(1, 3330);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3336, 3333, 3331, 3334, 3335);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3343, 3341, 3340, 3338, 3342);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrwi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 
static InstructionDefinition csrrsi_rd_zimm_csr (ISA32_RV64IMACFD, "csrrsi",(uint32_t) 0x006073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRSI\n");cp.code()+="etiss_coverage_count(1, 157);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3374);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3348, 3347, 3346);\n";cp.code()+="etiss_coverage_count(1, 3349);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3352, 3350, 3351);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(6, 3359, 3353, 3358, 3354, 3357, 3355);\n";} cp.code()+="etiss_coverage_count(1, 3360);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3366, 3363, 3361, 3364, 3365);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3373, 3371, 3370, 3368, 3372);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrsi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 
static InstructionDefinition csrrci_rd_zimm_csr (ISA32_RV64IMACFD, "csrrci",(uint32_t) 0x007073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRCI\n");cp.code()+="etiss_coverage_count(1, 158);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3378, 3377, 3376);\n";cp.code()+="etiss_coverage_count(1, 3379);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3382, 3380, 3381);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & "+std::to_string(~(((etiss_uint64)(zimm))))+"ULL);\n";cp.code()+="etiss_coverage_count(8, 3391, 3383, 3390, 3384, 3389, 3387, 3385, 3388);\n";} cp.code()+="etiss_coverage_count(1, 3392);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3398, 3395, 3393, 3396, 3397);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3405, 3403, 3402, 3400, 3404);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrci"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
 

Variable Documentation

◆ csrrc_rd_rs1_csr

InstructionDefinition csrrc_rd_rs1_csr(ISA32_RV64IMACFD, "csrrc",(uint32_t) 0x003073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRC\n"); cp.code()+="etiss_coverage_count(1, 155);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3288, 3287, 3286);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3295, 3294, 3293, 3291);\n";cp.code()+="etiss_coverage_count(1, 3296);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3299, 3297, 3298);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & ~(xrs1));\n";cp.code()+="etiss_coverage_count(6, 3305, 3300, 3304, 3301, 3303, 3302);\n";} cp.code()+="etiss_coverage_count(1, 3306);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3312, 3309, 3307, 3310, 3311);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3319, 3317, 3316, 3314, 3318);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrc"  ,
(uint32_t 0x003073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRC\n");cp.code()+="etiss_coverage_count(1, 155);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3288, 3287, 3286);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3295, 3294, 3293, 3291);\n";cp.code()+="etiss_coverage_count(1, 3296);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3299, 3297, 3298);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & ~(xrs1));\n";cp.code()+="etiss_coverage_count(6, 3305, 3300, 3304, 3301, 3303, 3302);\n";} cp.code()+="etiss_coverage_count(1, 3306);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3312, 3309, 3307, 3310, 3311);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3319, 3317, 3316, 3314, 3318);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static

◆ csrrci_rd_zimm_csr

InstructionDefinition csrrci_rd_zimm_csr(ISA32_RV64IMACFD, "csrrci",(uint32_t) 0x007073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRCI\n"); cp.code()+="etiss_coverage_count(1, 158);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3378, 3377, 3376);\n";cp.code()+="etiss_coverage_count(1, 3379);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3382, 3380, 3381);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & "+std::to_string(~(((etiss_uint64)(zimm))))+"ULL);\n";cp.code()+="etiss_coverage_count(8, 3391, 3383, 3390, 3384, 3389, 3387, 3385, 3388);\n";} cp.code()+="etiss_coverage_count(1, 3392);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3398, 3395, 3393, 3396, 3397);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3405, 3403, 3402, 3400, 3404);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrci"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrci"  ,
(uint32_t 0x007073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRCI\n");cp.code()+="etiss_coverage_count(1, 158);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3378, 3377, 3376);\n";cp.code()+="etiss_coverage_count(1, 3379);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3382, 3380, 3381);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & "+std::to_string(~(((etiss_uint64)(zimm))))+"ULL);\n";cp.code()+="etiss_coverage_count(8, 3391, 3383, 3390, 3384, 3389, 3387, 3385, 3388);\n";} cp.code()+="etiss_coverage_count(1, 3392);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3398, 3395, 3393, 3396, 3397);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3405, 3403, 3402, 3400, 3404);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrci"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static

◆ csrrs_rd_rs1_csr

InstructionDefinition csrrs_rd_rs1_csr(ISA32_RV64IMACFD, "csrrs",(uint32_t) 0x002073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRS\n"); cp.code()+="etiss_coverage_count(1, 154);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3284);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3253, 3252, 3251);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3260, 3259, 3258, 3256);\n";cp.code()+="etiss_coverage_count(1, 3261);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3264, 3262, 3263);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | xrs1);\n";cp.code()+="etiss_coverage_count(5, 3269, 3265, 3268, 3266, 3267);\n";} cp.code()+="etiss_coverage_count(1, 3270);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3276, 3273, 3271, 3274, 3275);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3283, 3281, 3280, 3278, 3282);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrs"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrs"  ,
(uint32_t 0x002073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRS\n");cp.code()+="etiss_coverage_count(1, 154);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3284);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3253, 3252, 3251);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3260, 3259, 3258, 3256);\n";cp.code()+="etiss_coverage_count(1, 3261);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3264, 3262, 3263);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | xrs1);\n";cp.code()+="etiss_coverage_count(5, 3269, 3265, 3268, 3266, 3267);\n";} cp.code()+="etiss_coverage_count(1, 3270);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3276, 3273, 3271, 3274, 3275);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3283, 3281, 3280, 3278, 3282);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrs"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static

◆ csrrsi_rd_zimm_csr

InstructionDefinition csrrsi_rd_zimm_csr(ISA32_RV64IMACFD, "csrrsi",(uint32_t) 0x006073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRSI\n"); cp.code()+="etiss_coverage_count(1, 157);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3374);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3348, 3347, 3346);\n";cp.code()+="etiss_coverage_count(1, 3349);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3352, 3350, 3351);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(6, 3359, 3353, 3358, 3354, 3357, 3355);\n";} cp.code()+="etiss_coverage_count(1, 3360);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3366, 3363, 3361, 3364, 3365);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3373, 3371, 3370, 3368, 3372);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrsi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrsi"  ,
(uint32_t 0x006073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRSI\n");cp.code()+="etiss_coverage_count(1, 157);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3374);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3348, 3347, 3346);\n";cp.code()+="etiss_coverage_count(1, 3349);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3352, 3350, 3351);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(6, 3359, 3353, 3358, 3354, 3357, 3355);\n";} cp.code()+="etiss_coverage_count(1, 3360);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3366, 3363, 3361, 3364, 3365);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3373, 3371, 3370, 3368, 3372);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrsi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static

◆ csrrw_rd_rs1_csr

InstructionDefinition csrrw_rd_rs1_csr(ISA32_RV64IMACFD, "csrrw",(uint32_t) 0x001073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRW\n"); cp.code()+="etiss_coverage_count(1, 153);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3249);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3222, 3221, 3220, 3218);\n";cp.code()+="etiss_coverage_count(1, 3223);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3229, 3226, 3224, 3227, 3228);\n";{ cp.code()+="etiss_coverage_count(1, 3244);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3233, 3232, 3231);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3236, 3234, 3235);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3243, 3241, 3240, 3238, 3242);\n";cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 3248);\n";cp.code()+="{ // block\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3247, 3245, 3246);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrw"  ,
(uint32_t 0x001073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRW\n");cp.code()+="etiss_coverage_count(1, 153);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3249);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3222, 3221, 3220, 3218);\n";cp.code()+="etiss_coverage_count(1, 3223);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3229, 3226, 3224, 3227, 3228);\n";{ cp.code()+="etiss_coverage_count(1, 3244);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3233, 3232, 3231);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3236, 3234, 3235);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3243, 3241, 3240, 3238, 3242);\n";cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 3248);\n";cp.code()+="{ // block\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3247, 3245, 3246);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static

◆ csrrwi_rd_zimm_csr

InstructionDefinition csrrwi_rd_zimm_csr(ISA32_RV64IMACFD, "csrrwi",(uint32_t) 0x005073,(uint32_t) 0x00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRWI\n"); cp.code()+="etiss_coverage_count(1, 156);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3344);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3324, 3323, 3322);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(4, 3329, 3325, 3328, 3326);\n";cp.code()+="etiss_coverage_count(1, 3330);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3336, 3333, 3331, 3334, 3335);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3343, 3341, 3340, 3338, 3342);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0; std::stringstream ss; ss<< "csrrwi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  ,
"csrrwi"  ,
(uint32_t 0x005073,
(uint32_t 0x00707f,
[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRWI\n");cp.code()+="etiss_coverage_count(1, 156);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3344);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3324, 3323, 3322);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(4, 3329, 3325, 3328, 3326);\n";cp.code()+="etiss_coverage_count(1, 3330);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3336, 3333, 3331, 3334, 3335);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3343, 3341, 3340, 3338, 3342);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  ,
,
[] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrwi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();}   
)
static