ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_tum_csrInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CSRRW -----------------------------------------------------------------------
16 static InstructionDefinition csrrw_rd_rs1_csr (
17  ISA32_RV64IMACFD,
18  "csrrw",
19  (uint32_t) 0x001073,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 csr = 0;
36 static BitArrayRange R_csr_0(31, 20);
37 csr += R_csr_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//CSRRW\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
55 if ((rd % 32ULL) != 0LL) { // conditional
56 { // block
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
59 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
60 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
61 cp.code() += "} // block\n";
62 } // block
63 } // conditional
64 else { // conditional
65 { // block
66 cp.code() += "{ // block\n";
67 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
68 cp.code() += "} // block\n";
69 } // block
70 } // conditional
71 cp.code() += "} // block\n";
72 } // block
73 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75 // -----------------------------------------------------------------------------
76  cp.getAffectedRegisters().add("instructionPointer", 32);
77  }
78 
79  return true;
80  },
81  0,
82  [] (BitArray & ba, Instruction & instr)
83  {
84 // -----------------------------------------------------------------------------
85 etiss_uint8 rd = 0;
86 static BitArrayRange R_rd_0(11, 7);
87 rd += R_rd_0.read(ba) << 0;
88 etiss_uint8 rs1 = 0;
89 static BitArrayRange R_rs1_0(19, 15);
90 rs1 += R_rs1_0.read(ba) << 0;
91 etiss_uint16 csr = 0;
92 static BitArrayRange R_csr_0(31, 20);
93 csr += R_csr_0.read(ba) << 0;
94 
95 // -----------------------------------------------------------------------------
96 
97  std::stringstream ss;
98 // -----------------------------------------------------------------------------
99 ss << "csrrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
100 // -----------------------------------------------------------------------------
101  return ss.str();
102  }
103 );
104 
105 // CSRRS -----------------------------------------------------------------------
106 static InstructionDefinition csrrs_rd_rs1_csr (
107  ISA32_RV64IMACFD,
108  "csrrs",
109  (uint32_t) 0x002073,
110  (uint32_t) 0x00707f,
111  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
112  {
113 
114 // -----------------------------------------------------------------------------
115 
116 // -----------------------------------------------------------------------------
117 
118 // -----------------------------------------------------------------------------
119 etiss_uint8 rd = 0;
120 static BitArrayRange R_rd_0(11, 7);
121 rd += R_rd_0.read(ba) << 0;
122 etiss_uint8 rs1 = 0;
123 static BitArrayRange R_rs1_0(19, 15);
124 rs1 += R_rs1_0.read(ba) << 0;
125 etiss_uint16 csr = 0;
126 static BitArrayRange R_csr_0(31, 20);
127 csr += R_csr_0.read(ba) << 0;
128 
129 // -----------------------------------------------------------------------------
130 
131  {
132  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
133 
134  cp.code() = std::string("//CSRRS\n");
135 
136 // -----------------------------------------------------------------------------
137 { // block
138 cp.code() += "{ // block\n";
139 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
140 cp.code() += "} // block\n";
141 } // block
142 { // block
143 cp.code() += "{ // block\n";
144 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
145 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
146 if (rs1 != 0LL) { // conditional
147 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
148 } // conditional
149 if ((rd % 32ULL) != 0LL) { // conditional
150 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
151 } // conditional
152 cp.code() += "} // block\n";
153 } // block
154 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
155 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
156 // -----------------------------------------------------------------------------
157  cp.getAffectedRegisters().add("instructionPointer", 32);
158  }
159 
160  return true;
161  },
162  0,
163  [] (BitArray & ba, Instruction & instr)
164  {
165 // -----------------------------------------------------------------------------
166 etiss_uint8 rd = 0;
167 static BitArrayRange R_rd_0(11, 7);
168 rd += R_rd_0.read(ba) << 0;
169 etiss_uint8 rs1 = 0;
170 static BitArrayRange R_rs1_0(19, 15);
171 rs1 += R_rs1_0.read(ba) << 0;
172 etiss_uint16 csr = 0;
173 static BitArrayRange R_csr_0(31, 20);
174 csr += R_csr_0.read(ba) << 0;
175 
176 // -----------------------------------------------------------------------------
177 
178  std::stringstream ss;
179 // -----------------------------------------------------------------------------
180 ss << "csrrs" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
181 // -----------------------------------------------------------------------------
182  return ss.str();
183  }
184 );
185 
186 // CSRRC -----------------------------------------------------------------------
187 static InstructionDefinition csrrc_rd_rs1_csr (
188  ISA32_RV64IMACFD,
189  "csrrc",
190  (uint32_t) 0x003073,
191  (uint32_t) 0x00707f,
192  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
193  {
194 
195 // -----------------------------------------------------------------------------
196 
197 // -----------------------------------------------------------------------------
198 
199 // -----------------------------------------------------------------------------
200 etiss_uint8 rd = 0;
201 static BitArrayRange R_rd_0(11, 7);
202 rd += R_rd_0.read(ba) << 0;
203 etiss_uint8 rs1 = 0;
204 static BitArrayRange R_rs1_0(19, 15);
205 rs1 += R_rs1_0.read(ba) << 0;
206 etiss_uint16 csr = 0;
207 static BitArrayRange R_csr_0(31, 20);
208 csr += R_csr_0.read(ba) << 0;
209 
210 // -----------------------------------------------------------------------------
211 
212  {
213  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
214 
215  cp.code() = std::string("//CSRRC\n");
216 
217 // -----------------------------------------------------------------------------
218 { // block
219 cp.code() += "{ // block\n";
220 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
221 cp.code() += "} // block\n";
222 } // block
223 { // block
224 cp.code() += "{ // block\n";
225 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
226 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
227 if (rs1 != 0LL) { // conditional
228 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
229 } // conditional
230 if ((rd % 32ULL) != 0LL) { // conditional
231 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
232 } // conditional
233 cp.code() += "} // block\n";
234 } // block
235 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
236 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
237 // -----------------------------------------------------------------------------
238  cp.getAffectedRegisters().add("instructionPointer", 32);
239  }
240 
241  return true;
242  },
243  0,
244  [] (BitArray & ba, Instruction & instr)
245  {
246 // -----------------------------------------------------------------------------
247 etiss_uint8 rd = 0;
248 static BitArrayRange R_rd_0(11, 7);
249 rd += R_rd_0.read(ba) << 0;
250 etiss_uint8 rs1 = 0;
251 static BitArrayRange R_rs1_0(19, 15);
252 rs1 += R_rs1_0.read(ba) << 0;
253 etiss_uint16 csr = 0;
254 static BitArrayRange R_csr_0(31, 20);
255 csr += R_csr_0.read(ba) << 0;
256 
257 // -----------------------------------------------------------------------------
258 
259  std::stringstream ss;
260 // -----------------------------------------------------------------------------
261 ss << "csrrc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
262 // -----------------------------------------------------------------------------
263  return ss.str();
264  }
265 );
266 
267 // CSRRWI ----------------------------------------------------------------------
268 static InstructionDefinition csrrwi_rd_zimm_csr (
269  ISA32_RV64IMACFD,
270  "csrrwi",
271  (uint32_t) 0x005073,
272  (uint32_t) 0x00707f,
273  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
274  {
275 
276 // -----------------------------------------------------------------------------
277 
278 // -----------------------------------------------------------------------------
279 
280 // -----------------------------------------------------------------------------
281 etiss_uint8 rd = 0;
282 static BitArrayRange R_rd_0(11, 7);
283 rd += R_rd_0.read(ba) << 0;
284 etiss_uint8 zimm = 0;
285 static BitArrayRange R_zimm_0(19, 15);
286 zimm += R_zimm_0.read(ba) << 0;
287 etiss_uint16 csr = 0;
288 static BitArrayRange R_csr_0(31, 20);
289 csr += R_csr_0.read(ba) << 0;
290 
291 // -----------------------------------------------------------------------------
292 
293  {
294  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
295 
296  cp.code() = std::string("//CSRRWI\n");
297 
298 // -----------------------------------------------------------------------------
299 { // block
300 cp.code() += "{ // block\n";
301 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
302 cp.code() += "} // block\n";
303 } // block
304 { // block
305 cp.code() += "{ // block\n";
306 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
307 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
308 if ((rd % 32ULL) != 0LL) { // conditional
309 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
310 } // conditional
311 cp.code() += "} // block\n";
312 } // block
313 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
314 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
315 // -----------------------------------------------------------------------------
316  cp.getAffectedRegisters().add("instructionPointer", 32);
317  }
318 
319  return true;
320  },
321  0,
322  [] (BitArray & ba, Instruction & instr)
323  {
324 // -----------------------------------------------------------------------------
325 etiss_uint8 rd = 0;
326 static BitArrayRange R_rd_0(11, 7);
327 rd += R_rd_0.read(ba) << 0;
328 etiss_uint8 zimm = 0;
329 static BitArrayRange R_zimm_0(19, 15);
330 zimm += R_zimm_0.read(ba) << 0;
331 etiss_uint16 csr = 0;
332 static BitArrayRange R_csr_0(31, 20);
333 csr += R_csr_0.read(ba) << 0;
334 
335 // -----------------------------------------------------------------------------
336 
337  std::stringstream ss;
338 // -----------------------------------------------------------------------------
339 ss << "csrrwi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
340 // -----------------------------------------------------------------------------
341  return ss.str();
342  }
343 );
344 
345 // CSRRSI ----------------------------------------------------------------------
346 static InstructionDefinition csrrsi_rd_zimm_csr (
347  ISA32_RV64IMACFD,
348  "csrrsi",
349  (uint32_t) 0x006073,
350  (uint32_t) 0x00707f,
351  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
352  {
353 
354 // -----------------------------------------------------------------------------
355 
356 // -----------------------------------------------------------------------------
357 
358 // -----------------------------------------------------------------------------
359 etiss_uint8 rd = 0;
360 static BitArrayRange R_rd_0(11, 7);
361 rd += R_rd_0.read(ba) << 0;
362 etiss_uint8 zimm = 0;
363 static BitArrayRange R_zimm_0(19, 15);
364 zimm += R_zimm_0.read(ba) << 0;
365 etiss_uint16 csr = 0;
366 static BitArrayRange R_csr_0(31, 20);
367 csr += R_csr_0.read(ba) << 0;
368 
369 // -----------------------------------------------------------------------------
370 
371  {
372  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
373 
374  cp.code() = std::string("//CSRRSI\n");
375 
376 // -----------------------------------------------------------------------------
377 { // block
378 cp.code() += "{ // block\n";
379 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
380 cp.code() += "} // block\n";
381 } // block
382 { // block
383 cp.code() += "{ // block\n";
384 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
385 if (zimm != 0LL) { // conditional
386 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
387 } // conditional
388 if ((rd % 32ULL) != 0LL) { // conditional
389 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
390 } // conditional
391 cp.code() += "} // block\n";
392 } // block
393 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
394 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
395 // -----------------------------------------------------------------------------
396  cp.getAffectedRegisters().add("instructionPointer", 32);
397  }
398 
399  return true;
400  },
401  0,
402  [] (BitArray & ba, Instruction & instr)
403  {
404 // -----------------------------------------------------------------------------
405 etiss_uint8 rd = 0;
406 static BitArrayRange R_rd_0(11, 7);
407 rd += R_rd_0.read(ba) << 0;
408 etiss_uint8 zimm = 0;
409 static BitArrayRange R_zimm_0(19, 15);
410 zimm += R_zimm_0.read(ba) << 0;
411 etiss_uint16 csr = 0;
412 static BitArrayRange R_csr_0(31, 20);
413 csr += R_csr_0.read(ba) << 0;
414 
415 // -----------------------------------------------------------------------------
416 
417  std::stringstream ss;
418 // -----------------------------------------------------------------------------
419 ss << "csrrsi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
420 // -----------------------------------------------------------------------------
421  return ss.str();
422  }
423 );
424 
425 // CSRRCI ----------------------------------------------------------------------
426 static InstructionDefinition csrrci_rd_zimm_csr (
427  ISA32_RV64IMACFD,
428  "csrrci",
429  (uint32_t) 0x007073,
430  (uint32_t) 0x00707f,
431  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
432  {
433 
434 // -----------------------------------------------------------------------------
435 
436 // -----------------------------------------------------------------------------
437 
438 // -----------------------------------------------------------------------------
439 etiss_uint8 rd = 0;
440 static BitArrayRange R_rd_0(11, 7);
441 rd += R_rd_0.read(ba) << 0;
442 etiss_uint8 zimm = 0;
443 static BitArrayRange R_zimm_0(19, 15);
444 zimm += R_zimm_0.read(ba) << 0;
445 etiss_uint16 csr = 0;
446 static BitArrayRange R_csr_0(31, 20);
447 csr += R_csr_0.read(ba) << 0;
448 
449 // -----------------------------------------------------------------------------
450 
451  {
452  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
453 
454  cp.code() = std::string("//CSRRCI\n");
455 
456 // -----------------------------------------------------------------------------
457 { // block
458 cp.code() += "{ // block\n";
459 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
460 cp.code() += "} // block\n";
461 } // block
462 { // block
463 cp.code() += "{ // block\n";
464 cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
465 if (zimm != 0LL) { // conditional
466 cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
467 } // conditional
468 if ((rd % 32ULL) != 0LL) { // conditional
469 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
470 } // conditional
471 cp.code() += "} // block\n";
472 } // block
473 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
474 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
475 // -----------------------------------------------------------------------------
476  cp.getAffectedRegisters().add("instructionPointer", 32);
477  }
478 
479  return true;
480  },
481  0,
482  [] (BitArray & ba, Instruction & instr)
483  {
484 // -----------------------------------------------------------------------------
485 etiss_uint8 rd = 0;
486 static BitArrayRange R_rd_0(11, 7);
487 rd += R_rd_0.read(ba) << 0;
488 etiss_uint8 zimm = 0;
489 static BitArrayRange R_zimm_0(19, 15);
490 zimm += R_zimm_0.read(ba) << 0;
491 etiss_uint16 csr = 0;
492 static BitArrayRange R_csr_0(31, 20);
493 csr += R_csr_0.read(ba) << 0;
494 
495 // -----------------------------------------------------------------------------
496 
497  std::stringstream ss;
498 // -----------------------------------------------------------------------------
499 ss << "csrrci" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
500 // -----------------------------------------------------------------------------
501  return ss.str();
502  }
503 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
csrrsi_rd_zimm_csr
static InstructionDefinition csrrsi_rd_zimm_csr(ISA32_RV64IMACFD, "csrrsi",(uint32_t) 0x006073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRSI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";if(zimm !=0LL) { cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrsi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrci_rd_zimm_csr
static InstructionDefinition csrrci_rd_zimm_csr(ISA32_RV64IMACFD, "csrrci",(uint32_t) 0x007073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRCI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";if(zimm !=0LL) { cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & "+std::to_string(~(((etiss_uint64)(zimm))))+"ULL);\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrci"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrc_rd_rs1_csr
static InstructionDefinition csrrc_rd_rs1_csr(ISA32_RV64IMACFD, "csrrc",(uint32_t) 0x003073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRC\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";if(rs1 !=0LL) { cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & ~(xrs1));\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrs_rd_rs1_csr
static InstructionDefinition csrrs_rd_rs1_csr(ISA32_RV64IMACFD, "csrrs",(uint32_t) 0x002073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRS\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";if(rs1 !=0LL) { cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | xrs1);\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrs"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrw_rd_rs1_csr
static InstructionDefinition csrrw_rd_rs1_csr(ISA32_RV64IMACFD, "csrrw",(uint32_t) 0x001073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrwi_rd_zimm_csr
static InstructionDefinition csrrwi_rd_zimm_csr(ISA32_RV64IMACFD, "csrrwi",(uint32_t) 0x005073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRWI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="RV64IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, "+std::to_string((etiss_uint64)(zimm))+"ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrwi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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