RV64IMACFD_RV32MInstr.cpp File Reference

#include "RV64IMACFDArch.h"
#include "RV64IMACFDFuncs.h"

Include dependency graph for RV64IMACFD_RV32MInstr.cpp:

Go to the source code of this file.

Variables
static InstructionDefinition	div_rd_rs1_rs2 (ISA32_RV64IMACFD, "div",(uint64_t) 0x2004033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2984);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2904);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";{ cp.code()+="etiss_coverage_count(1, 2983);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2911);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";{ cp.code()+="etiss_coverage_count(1, 2974);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 2926);\n";cp.code()+="etiss_coverage_count(1, 2927);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
static InstructionDefinition	divu_rd_rs1_rs2 (ISA32_RV64IMACFD, "divu",(uint64_t) 0x2005033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3026);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2985);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";{ cp.code()+="etiss_coverage_count(1, 3025);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2992);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
static InstructionDefinition	rem_rd_rs1_rs2 (ISA32_RV64IMACFD, "rem",(uint64_t) 0x2006033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3027);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";{ cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";{ cp.code()+="etiss_coverage_count(1, 3097);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 3049);\n";cp.code()+="etiss_coverage_count(1, 3050);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
static InstructionDefinition	remu_rd_rs1_rs2 (ISA32_RV64IMACFD, "remu",(uint64_t) 0x2007033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3155);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3111);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";{ cp.code()+="etiss_coverage_count(1, 3154);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3118);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})

Variable Documentation

div_rd_rs1_rs2

InstructionDefinition div_rd_rs1_rs2(ISA32_RV64IMACFD, "div",(uint64_t) 0x2004033,(uint64_t) 0xfe00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n"); cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2984);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2904);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";{ cp.code()+="etiss_coverage_count(1, 2983);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2911);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";{ cp.code()+="etiss_coverage_count(1, 2974);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 2926);\n";cp.code()+="etiss_coverage_count(1, 2927);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; std::stringstream ss; ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  , "div"  , (uint64_t)  0x2004033, (uint64_t)  0xfe00707f, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2984);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2904);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";{ cp.code()+="etiss_coverage_count(1, 2983);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2911);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";{ cp.code()+="etiss_coverage_count(1, 2974);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 2926);\n";cp.code()+="etiss_coverage_count(1, 2927);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}    )

static

divu_rd_rs1_rs2

InstructionDefinition divu_rd_rs1_rs2(ISA32_RV64IMACFD, "divu",(uint64_t) 0x2005033,(uint64_t) 0xfe00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n"); cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3026);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2985);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";{ cp.code()+="etiss_coverage_count(1, 3025);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2992);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; std::stringstream ss; ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  , "divu"  , (uint64_t)  0x2005033, (uint64_t)  0xfe00707f, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3026);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2985);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";{ cp.code()+="etiss_coverage_count(1, 3025);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2992);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}    )

static

rem_rd_rs1_rs2

InstructionDefinition rem_rd_rs1_rs2(ISA32_RV64IMACFD, "rem",(uint64_t) 0x2006033,(uint64_t) 0xfe00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n"); cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3027);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";{ cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";{ cp.code()+="etiss_coverage_count(1, 3097);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 3049);\n";cp.code()+="etiss_coverage_count(1, 3050);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; std::stringstream ss; ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  , "rem"  , (uint64_t)  0x2006033, (uint64_t)  0xfe00707f, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3027);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";{ cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";{ cp.code()+="etiss_coverage_count(1, 3097);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 3049);\n";cp.code()+="etiss_coverage_count(1, 3050);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}    )

static

remu_rd_rs1_rs2

InstructionDefinition remu_rd_rs1_rs2(ISA32_RV64IMACFD, "remu",(uint64_t) 0x2007033,(uint64_t) 0xfe00707f,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n"); cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3155);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3111);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";{ cp.code()+="etiss_coverage_count(1, 3154);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3118);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0,[](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0; std::stringstream ss; ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]"); return ss.str();}) ( ISA32_RV64IMACFD  , "remu"  , (uint64_t)  0x2007033, (uint64_t)  0xfe00707f, [] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3155);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3111);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";{ cp.code()+="etiss_coverage_count(1, 3154);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3118);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}  , 0  , [] (BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}    )

static