ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32MInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // DIV -------------------------------------------------------------------------
16 static InstructionDefinition div_rd_rs1_rs2 (
17  ISA32_RV64IMACFD,
18  "div",
19  (uint32_t) 0x2004033,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//DIV\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 if ((rd % 32ULL) != 0LL) { // conditional
55 { // block
56 cp.code() += "{ // block\n";
57 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
58 { // block
59 cp.code() += "{ // block\n";
60 etiss_uint64 MMIN = 9223372036854775808ULL;
61 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
62 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
63 cp.code() += "} // conditional\n";
64 cp.code() += "else { // conditional\n";
65 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
66 cp.code() += "} // conditional\n";
67 cp.code() += "} // block\n";
68 } // block
69 cp.code() += "} // conditional\n";
70 cp.code() += "else { // conditional\n";
71 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
72 cp.code() += "} // conditional\n";
73 cp.code() += "} // block\n";
74 } // block
75 } // conditional
76 cp.code() += "} // block\n";
77 } // block
78 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
79 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
80 // -----------------------------------------------------------------------------
81  cp.getAffectedRegisters().add("instructionPointer", 32);
82  }
83 
84  return true;
85  },
86  0,
87  [] (BitArray & ba, Instruction & instr)
88  {
89 // -----------------------------------------------------------------------------
90 etiss_uint8 rd = 0;
91 static BitArrayRange R_rd_0(11, 7);
92 rd += R_rd_0.read(ba) << 0;
93 etiss_uint8 rs1 = 0;
94 static BitArrayRange R_rs1_0(19, 15);
95 rs1 += R_rs1_0.read(ba) << 0;
96 etiss_uint8 rs2 = 0;
97 static BitArrayRange R_rs2_0(24, 20);
98 rs2 += R_rs2_0.read(ba) << 0;
99 
100 // -----------------------------------------------------------------------------
101 
102  std::stringstream ss;
103 // -----------------------------------------------------------------------------
104 ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
105 // -----------------------------------------------------------------------------
106  return ss.str();
107  }
108 );
109 
110 // DIVU ------------------------------------------------------------------------
111 static InstructionDefinition divu_rd_rs1_rs2 (
112  ISA32_RV64IMACFD,
113  "divu",
114  (uint32_t) 0x2005033,
115  (uint32_t) 0xfe00707f,
116  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
117  {
118 
119 // -----------------------------------------------------------------------------
120 
121 // -----------------------------------------------------------------------------
122 
123 // -----------------------------------------------------------------------------
124 etiss_uint8 rd = 0;
125 static BitArrayRange R_rd_0(11, 7);
126 rd += R_rd_0.read(ba) << 0;
127 etiss_uint8 rs1 = 0;
128 static BitArrayRange R_rs1_0(19, 15);
129 rs1 += R_rs1_0.read(ba) << 0;
130 etiss_uint8 rs2 = 0;
131 static BitArrayRange R_rs2_0(24, 20);
132 rs2 += R_rs2_0.read(ba) << 0;
133 
134 // -----------------------------------------------------------------------------
135 
136  {
137  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
138 
139  cp.code() = std::string("//DIVU\n");
140 
141 // -----------------------------------------------------------------------------
142 { // block
143 cp.code() += "{ // block\n";
144 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
145 cp.code() += "} // block\n";
146 } // block
147 { // block
148 cp.code() += "{ // block\n";
149 if ((rd % 32ULL) != 0LL) { // conditional
150 { // block
151 cp.code() += "{ // block\n";
152 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
153 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
154 cp.code() += "} // conditional\n";
155 cp.code() += "else { // conditional\n";
156 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
157 cp.code() += "} // conditional\n";
158 cp.code() += "} // block\n";
159 } // block
160 } // conditional
161 cp.code() += "} // block\n";
162 } // block
163 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
164 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
165 // -----------------------------------------------------------------------------
166  cp.getAffectedRegisters().add("instructionPointer", 32);
167  }
168 
169  return true;
170  },
171  0,
172  [] (BitArray & ba, Instruction & instr)
173  {
174 // -----------------------------------------------------------------------------
175 etiss_uint8 rd = 0;
176 static BitArrayRange R_rd_0(11, 7);
177 rd += R_rd_0.read(ba) << 0;
178 etiss_uint8 rs1 = 0;
179 static BitArrayRange R_rs1_0(19, 15);
180 rs1 += R_rs1_0.read(ba) << 0;
181 etiss_uint8 rs2 = 0;
182 static BitArrayRange R_rs2_0(24, 20);
183 rs2 += R_rs2_0.read(ba) << 0;
184 
185 // -----------------------------------------------------------------------------
186 
187  std::stringstream ss;
188 // -----------------------------------------------------------------------------
189 ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
190 // -----------------------------------------------------------------------------
191  return ss.str();
192  }
193 );
194 
195 // REM -------------------------------------------------------------------------
196 static InstructionDefinition rem_rd_rs1_rs2 (
197  ISA32_RV64IMACFD,
198  "rem",
199  (uint32_t) 0x2006033,
200  (uint32_t) 0xfe00707f,
201  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
202  {
203 
204 // -----------------------------------------------------------------------------
205 
206 // -----------------------------------------------------------------------------
207 
208 // -----------------------------------------------------------------------------
209 etiss_uint8 rd = 0;
210 static BitArrayRange R_rd_0(11, 7);
211 rd += R_rd_0.read(ba) << 0;
212 etiss_uint8 rs1 = 0;
213 static BitArrayRange R_rs1_0(19, 15);
214 rs1 += R_rs1_0.read(ba) << 0;
215 etiss_uint8 rs2 = 0;
216 static BitArrayRange R_rs2_0(24, 20);
217 rs2 += R_rs2_0.read(ba) << 0;
218 
219 // -----------------------------------------------------------------------------
220 
221  {
222  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
223 
224  cp.code() = std::string("//REM\n");
225 
226 // -----------------------------------------------------------------------------
227 { // block
228 cp.code() += "{ // block\n";
229 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
230 cp.code() += "} // block\n";
231 } // block
232 { // block
233 cp.code() += "{ // block\n";
234 if ((rd % 32ULL) != 0LL) { // conditional
235 { // block
236 cp.code() += "{ // block\n";
237 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
238 { // block
239 cp.code() += "{ // block\n";
240 etiss_uint64 MMIN = 9223372036854775808ULL;
241 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
242 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
243 cp.code() += "} // conditional\n";
244 cp.code() += "else { // conditional\n";
245 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
246 cp.code() += "} // conditional\n";
247 cp.code() += "} // block\n";
248 } // block
249 cp.code() += "} // conditional\n";
250 cp.code() += "else { // conditional\n";
251 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
252 cp.code() += "} // conditional\n";
253 cp.code() += "} // block\n";
254 } // block
255 } // conditional
256 cp.code() += "} // block\n";
257 } // block
258 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
259 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
260 // -----------------------------------------------------------------------------
261  cp.getAffectedRegisters().add("instructionPointer", 32);
262  }
263 
264  return true;
265  },
266  0,
267  [] (BitArray & ba, Instruction & instr)
268  {
269 // -----------------------------------------------------------------------------
270 etiss_uint8 rd = 0;
271 static BitArrayRange R_rd_0(11, 7);
272 rd += R_rd_0.read(ba) << 0;
273 etiss_uint8 rs1 = 0;
274 static BitArrayRange R_rs1_0(19, 15);
275 rs1 += R_rs1_0.read(ba) << 0;
276 etiss_uint8 rs2 = 0;
277 static BitArrayRange R_rs2_0(24, 20);
278 rs2 += R_rs2_0.read(ba) << 0;
279 
280 // -----------------------------------------------------------------------------
281 
282  std::stringstream ss;
283 // -----------------------------------------------------------------------------
284 ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
285 // -----------------------------------------------------------------------------
286  return ss.str();
287  }
288 );
289 
290 // REMU ------------------------------------------------------------------------
291 static InstructionDefinition remu_rd_rs1_rs2 (
292  ISA32_RV64IMACFD,
293  "remu",
294  (uint32_t) 0x2007033,
295  (uint32_t) 0xfe00707f,
296  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
297  {
298 
299 // -----------------------------------------------------------------------------
300 
301 // -----------------------------------------------------------------------------
302 
303 // -----------------------------------------------------------------------------
304 etiss_uint8 rd = 0;
305 static BitArrayRange R_rd_0(11, 7);
306 rd += R_rd_0.read(ba) << 0;
307 etiss_uint8 rs1 = 0;
308 static BitArrayRange R_rs1_0(19, 15);
309 rs1 += R_rs1_0.read(ba) << 0;
310 etiss_uint8 rs2 = 0;
311 static BitArrayRange R_rs2_0(24, 20);
312 rs2 += R_rs2_0.read(ba) << 0;
313 
314 // -----------------------------------------------------------------------------
315 
316  {
317  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
318 
319  cp.code() = std::string("//REMU\n");
320 
321 // -----------------------------------------------------------------------------
322 { // block
323 cp.code() += "{ // block\n";
324 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
325 cp.code() += "} // block\n";
326 } // block
327 { // block
328 cp.code() += "{ // block\n";
329 if ((rd % 32ULL) != 0LL) { // conditional
330 { // block
331 cp.code() += "{ // block\n";
332 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
333 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
334 cp.code() += "} // conditional\n";
335 cp.code() += "else { // conditional\n";
336 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
337 cp.code() += "} // conditional\n";
338 cp.code() += "} // block\n";
339 } // block
340 } // conditional
341 cp.code() += "} // block\n";
342 } // block
343 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
344 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
345 // -----------------------------------------------------------------------------
346  cp.getAffectedRegisters().add("instructionPointer", 32);
347  }
348 
349  return true;
350  },
351  0,
352  [] (BitArray & ba, Instruction & instr)
353  {
354 // -----------------------------------------------------------------------------
355 etiss_uint8 rd = 0;
356 static BitArrayRange R_rd_0(11, 7);
357 rd += R_rd_0.read(ba) << 0;
358 etiss_uint8 rs1 = 0;
359 static BitArrayRange R_rs1_0(19, 15);
360 rs1 += R_rs1_0.read(ba) << 0;
361 etiss_uint8 rs2 = 0;
362 static BitArrayRange R_rs2_0(24, 20);
363 rs2 += R_rs2_0.read(ba) << 0;
364 
365 // -----------------------------------------------------------------------------
366 
367  std::stringstream ss;
368 // -----------------------------------------------------------------------------
369 ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
370 // -----------------------------------------------------------------------------
371  return ss.str();
372  }
373 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV64IMACFD, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";{ cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV64IMACFD, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";{ cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV64IMACFD, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV64IMACFD, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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