ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
Loading...
Searching...
No Matches
RV64IMACFD_RV32MInstr.cpp
Go to the documentation of this file.
1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// DIV -------------------------------------------------------------------------
16static InstructionDefinition div_rd_rs1_rs2 (
17 ISA32_RV64IMACFD,
18 "div",
19 (uint64_t) 0x2004033,
20 (uint64_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint8 rs2 = 0;
37static BitArrayRange R_rs2_0(24, 20);
38rs2 += R_rs2_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//DIV\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 76);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1189);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
54cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 2984);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_coverage_count(1, 2904);\n";
61if ((rd % 32ULL) != 0LL) { // conditional
62cp.code() += "etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";
63{ // block
64cp.code() += "etiss_coverage_count(1, 2983);\n";
65cp.code() += "{ // block\n";
66cp.code() += "etiss_coverage_count(1, 2911);\n";
67cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
68cp.code() += "etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";
69{ // block
70cp.code() += "etiss_coverage_count(1, 2974);\n";
71cp.code() += "{ // block\n";
72etiss_uint64 MMIN = 9223372036854775808ULL;
73cp.code() += "etiss_coverage_count(1, 2926);\n";
74cp.code() += "etiss_coverage_count(1, 2927);\n";
75cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
76cp.code() += "etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";
77cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
78cp.code() += "etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";
79cp.code() += "} // conditional\n";
80cp.code() += "else { // conditional\n";
81cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
82cp.code() += "etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";
83cp.code() += "} // conditional\n";
84cp.code() += "} // block\n";
85} // block
86cp.code() += "} // conditional\n";
87cp.code() += "else { // conditional\n";
88cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
89cp.code() += "etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";
90cp.code() += "} // conditional\n";
91cp.code() += "} // block\n";
92} // block
93} // conditional
94cp.code() += "} // block\n";
95} // block
96cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
97cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
98// -----------------------------------------------------------------------------
99 cp.getAffectedRegisters().add("instructionPointer", 32);
100 }
101
102 return true;
103 },
104 0,
105 [] (BitArray & ba, Instruction & instr)
106 {
107// -----------------------------------------------------------------------------
108etiss_uint8 rd = 0;
109static BitArrayRange R_rd_0(11, 7);
110rd += R_rd_0.read(ba) << 0;
111etiss_uint8 rs1 = 0;
112static BitArrayRange R_rs1_0(19, 15);
113rs1 += R_rs1_0.read(ba) << 0;
114etiss_uint8 rs2 = 0;
115static BitArrayRange R_rs2_0(24, 20);
116rs2 += R_rs2_0.read(ba) << 0;
117
118// -----------------------------------------------------------------------------
119
120 std::stringstream ss;
121// -----------------------------------------------------------------------------
122ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
123// -----------------------------------------------------------------------------
124 return ss.str();
125 }
126);
127
128// DIVU ------------------------------------------------------------------------
129static InstructionDefinition divu_rd_rs1_rs2 (
130 ISA32_RV64IMACFD,
131 "divu",
132 (uint64_t) 0x2005033,
133 (uint64_t) 0xfe00707f,
134 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
135 {
136
137// -----------------------------------------------------------------------------
138
139// -----------------------------------------------------------------------------
140
141// -----------------------------------------------------------------------------
142// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
143etiss_uint8 rd = 0;
144static BitArrayRange R_rd_0(11, 7);
145rd += R_rd_0.read(ba) << 0;
146etiss_uint8 rs1 = 0;
147static BitArrayRange R_rs1_0(19, 15);
148rs1 += R_rs1_0.read(ba) << 0;
149etiss_uint8 rs2 = 0;
150static BitArrayRange R_rs2_0(24, 20);
151rs2 += R_rs2_0.read(ba) << 0;
152
153// NOLINTEND(clang-diagnostic-unused-but-set-variable)
154// -----------------------------------------------------------------------------
155
156 {
157 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
158
159 cp.code() = std::string("//DIVU\n");
160
161// -----------------------------------------------------------------------------
162cp.code() += "etiss_coverage_count(1, 77);\n";
163{ // block
164cp.code() += "etiss_coverage_count(1, 1189);\n";
165cp.code() += "{ // block\n";
166cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
167cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
168cp.code() += "} // block\n";
169} // block
170{ // block
171cp.code() += "etiss_coverage_count(1, 3026);\n";
172cp.code() += "{ // block\n";
173cp.code() += "etiss_coverage_count(1, 2985);\n";
174if ((rd % 32ULL) != 0LL) { // conditional
175cp.code() += "etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";
176{ // block
177cp.code() += "etiss_coverage_count(1, 3025);\n";
178cp.code() += "{ // block\n";
179cp.code() += "etiss_coverage_count(1, 2992);\n";
180cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
181cp.code() += "etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";
182cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
183cp.code() += "etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";
184cp.code() += "} // conditional\n";
185cp.code() += "else { // conditional\n";
186cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
187cp.code() += "etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";
188cp.code() += "} // conditional\n";
189cp.code() += "} // block\n";
190} // block
191} // conditional
192cp.code() += "} // block\n";
193} // block
194cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
195cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
196// -----------------------------------------------------------------------------
197 cp.getAffectedRegisters().add("instructionPointer", 32);
198 }
199
200 return true;
201 },
202 0,
203 [] (BitArray & ba, Instruction & instr)
204 {
205// -----------------------------------------------------------------------------
206etiss_uint8 rd = 0;
207static BitArrayRange R_rd_0(11, 7);
208rd += R_rd_0.read(ba) << 0;
209etiss_uint8 rs1 = 0;
210static BitArrayRange R_rs1_0(19, 15);
211rs1 += R_rs1_0.read(ba) << 0;
212etiss_uint8 rs2 = 0;
213static BitArrayRange R_rs2_0(24, 20);
214rs2 += R_rs2_0.read(ba) << 0;
215
216// -----------------------------------------------------------------------------
217
218 std::stringstream ss;
219// -----------------------------------------------------------------------------
220ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
221// -----------------------------------------------------------------------------
222 return ss.str();
223 }
224);
225
226// REM -------------------------------------------------------------------------
227static InstructionDefinition rem_rd_rs1_rs2 (
228 ISA32_RV64IMACFD,
229 "rem",
230 (uint64_t) 0x2006033,
231 (uint64_t) 0xfe00707f,
232 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
233 {
234
235// -----------------------------------------------------------------------------
236
237// -----------------------------------------------------------------------------
238
239// -----------------------------------------------------------------------------
240// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
241etiss_uint8 rd = 0;
242static BitArrayRange R_rd_0(11, 7);
243rd += R_rd_0.read(ba) << 0;
244etiss_uint8 rs1 = 0;
245static BitArrayRange R_rs1_0(19, 15);
246rs1 += R_rs1_0.read(ba) << 0;
247etiss_uint8 rs2 = 0;
248static BitArrayRange R_rs2_0(24, 20);
249rs2 += R_rs2_0.read(ba) << 0;
250
251// NOLINTEND(clang-diagnostic-unused-but-set-variable)
252// -----------------------------------------------------------------------------
253
254 {
255 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
256
257 cp.code() = std::string("//REM\n");
258
259// -----------------------------------------------------------------------------
260cp.code() += "etiss_coverage_count(1, 78);\n";
261{ // block
262cp.code() += "etiss_coverage_count(1, 1189);\n";
263cp.code() += "{ // block\n";
264cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
265cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
266cp.code() += "} // block\n";
267} // block
268{ // block
269cp.code() += "etiss_coverage_count(1, 3110);\n";
270cp.code() += "{ // block\n";
271cp.code() += "etiss_coverage_count(1, 3027);\n";
272if ((rd % 32ULL) != 0LL) { // conditional
273cp.code() += "etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";
274{ // block
275cp.code() += "etiss_coverage_count(1, 3109);\n";
276cp.code() += "{ // block\n";
277cp.code() += "etiss_coverage_count(1, 3034);\n";
278cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
279cp.code() += "etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";
280{ // block
281cp.code() += "etiss_coverage_count(1, 3097);\n";
282cp.code() += "{ // block\n";
283etiss_uint64 MMIN = 9223372036854775808ULL;
284cp.code() += "etiss_coverage_count(1, 3049);\n";
285cp.code() += "etiss_coverage_count(1, 3050);\n";
286cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
287cp.code() += "etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";
288cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
289cp.code() += "etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";
290cp.code() += "} // conditional\n";
291cp.code() += "else { // conditional\n";
292cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
293cp.code() += "etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";
294cp.code() += "} // conditional\n";
295cp.code() += "} // block\n";
296} // block
297cp.code() += "} // conditional\n";
298cp.code() += "else { // conditional\n";
299cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
300cp.code() += "etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";
301cp.code() += "} // conditional\n";
302cp.code() += "} // block\n";
303} // block
304} // conditional
305cp.code() += "} // block\n";
306} // block
307cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
308cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
309// -----------------------------------------------------------------------------
310 cp.getAffectedRegisters().add("instructionPointer", 32);
311 }
312
313 return true;
314 },
315 0,
316 [] (BitArray & ba, Instruction & instr)
317 {
318// -----------------------------------------------------------------------------
319etiss_uint8 rd = 0;
320static BitArrayRange R_rd_0(11, 7);
321rd += R_rd_0.read(ba) << 0;
322etiss_uint8 rs1 = 0;
323static BitArrayRange R_rs1_0(19, 15);
324rs1 += R_rs1_0.read(ba) << 0;
325etiss_uint8 rs2 = 0;
326static BitArrayRange R_rs2_0(24, 20);
327rs2 += R_rs2_0.read(ba) << 0;
328
329// -----------------------------------------------------------------------------
330
331 std::stringstream ss;
332// -----------------------------------------------------------------------------
333ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
334// -----------------------------------------------------------------------------
335 return ss.str();
336 }
337);
338
339// REMU ------------------------------------------------------------------------
340static InstructionDefinition remu_rd_rs1_rs2 (
341 ISA32_RV64IMACFD,
342 "remu",
343 (uint64_t) 0x2007033,
344 (uint64_t) 0xfe00707f,
345 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
346 {
347
348// -----------------------------------------------------------------------------
349
350// -----------------------------------------------------------------------------
351
352// -----------------------------------------------------------------------------
353// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
354etiss_uint8 rd = 0;
355static BitArrayRange R_rd_0(11, 7);
356rd += R_rd_0.read(ba) << 0;
357etiss_uint8 rs1 = 0;
358static BitArrayRange R_rs1_0(19, 15);
359rs1 += R_rs1_0.read(ba) << 0;
360etiss_uint8 rs2 = 0;
361static BitArrayRange R_rs2_0(24, 20);
362rs2 += R_rs2_0.read(ba) << 0;
363
364// NOLINTEND(clang-diagnostic-unused-but-set-variable)
365// -----------------------------------------------------------------------------
366
367 {
368 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
369
370 cp.code() = std::string("//REMU\n");
371
372// -----------------------------------------------------------------------------
373cp.code() += "etiss_coverage_count(1, 79);\n";
374{ // block
375cp.code() += "etiss_coverage_count(1, 1189);\n";
376cp.code() += "{ // block\n";
377cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
378cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
379cp.code() += "} // block\n";
380} // block
381{ // block
382cp.code() += "etiss_coverage_count(1, 3155);\n";
383cp.code() += "{ // block\n";
384cp.code() += "etiss_coverage_count(1, 3111);\n";
385if ((rd % 32ULL) != 0LL) { // conditional
386cp.code() += "etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";
387{ // block
388cp.code() += "etiss_coverage_count(1, 3154);\n";
389cp.code() += "{ // block\n";
390cp.code() += "etiss_coverage_count(1, 3118);\n";
391cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
392cp.code() += "etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";
393cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
394cp.code() += "etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";
395cp.code() += "} // conditional\n";
396cp.code() += "else { // conditional\n";
397cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
398cp.code() += "etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";
399cp.code() += "} // conditional\n";
400cp.code() += "} // block\n";
401} // block
402} // conditional
403cp.code() += "} // block\n";
404} // block
405cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
406cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
407// -----------------------------------------------------------------------------
408 cp.getAffectedRegisters().add("instructionPointer", 32);
409 }
410
411 return true;
412 },
413 0,
414 [] (BitArray & ba, Instruction & instr)
415 {
416// -----------------------------------------------------------------------------
417etiss_uint8 rd = 0;
418static BitArrayRange R_rd_0(11, 7);
419rd += R_rd_0.read(ba) << 0;
420etiss_uint8 rs1 = 0;
421static BitArrayRange R_rs1_0(19, 15);
422rs1 += R_rs1_0.read(ba) << 0;
423etiss_uint8 rs2 = 0;
424static BitArrayRange R_rs2_0(24, 20);
425rs2 += R_rs2_0.read(ba) << 0;
426
427// -----------------------------------------------------------------------------
428
429 std::stringstream ss;
430// -----------------------------------------------------------------------------
431ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
432// -----------------------------------------------------------------------------
433 return ss.str();
434 }
435);
436// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV64IMACFD, "div",(uint64_t) 0x2004033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2984);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2904);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";{ cp.code()+="etiss_coverage_count(1, 2983);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2911);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";{ cp.code()+="etiss_coverage_count(1, 2974);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 2926);\n";cp.code()+="etiss_coverage_count(1, 2927);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV64IMACFD, "divu",(uint64_t) 0x2005033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3026);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2985);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";{ cp.code()+="etiss_coverage_count(1, 3025);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2992);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV64IMACFD, "remu",(uint64_t) 0x2007033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3155);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3111);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";{ cp.code()+="etiss_coverage_count(1, 3154);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3118);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV64IMACFD, "rem",(uint64_t) 0x2006033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3027);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";{ cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";{ cp.code()+="etiss_coverage_count(1, 3097);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 3049);\n";cp.code()+="etiss_coverage_count(1, 3050);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint64
uint64_t etiss_uint64
Definition types.h:58
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
Generated on Tue Apr 28 2026 08:32:26 for ETISS 0.11.2 by doxygen 1.9.8