ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32MInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // DIV -------------------------------------------------------------------------
16 static InstructionDefinition div_rd_rs1_rs2 (
17  ISA32_RV64IMACFD,
18  "div",
19  (uint32_t) 0x2004033,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//DIV\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 76);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 3044);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_coverage_count(1, 2964);\n";
59 if ((rd % 32ULL) != 0LL) { // conditional
60 cp.code() += "etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";
61 { // block
62 cp.code() += "etiss_coverage_count(1, 3043);\n";
63 cp.code() += "{ // block\n";
64 cp.code() += "etiss_coverage_count(1, 2971);\n";
65 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
66 cp.code() += "etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";
67 { // block
68 cp.code() += "etiss_coverage_count(1, 3034);\n";
69 cp.code() += "{ // block\n";
70 etiss_uint64 MMIN = 9223372036854775808ULL;
71 cp.code() += "etiss_coverage_count(1, 2986);\n";
72 cp.code() += "etiss_coverage_count(1, 2987);\n";
73 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
74 cp.code() += "etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";
75 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
76 cp.code() += "etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";
77 cp.code() += "} // conditional\n";
78 cp.code() += "else { // conditional\n";
79 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
80 cp.code() += "etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";
81 cp.code() += "} // conditional\n";
82 cp.code() += "} // block\n";
83 } // block
84 cp.code() += "} // conditional\n";
85 cp.code() += "else { // conditional\n";
86 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
87 cp.code() += "etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";
88 cp.code() += "} // conditional\n";
89 cp.code() += "} // block\n";
90 } // block
91 } // conditional
92 cp.code() += "} // block\n";
93 } // block
94 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
95 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
96 // -----------------------------------------------------------------------------
97  cp.getAffectedRegisters().add("instructionPointer", 32);
98  }
99 
100  return true;
101  },
102  0,
103  [] (BitArray & ba, Instruction & instr)
104  {
105 // -----------------------------------------------------------------------------
106 etiss_uint8 rd = 0;
107 static BitArrayRange R_rd_0(11, 7);
108 rd += R_rd_0.read(ba) << 0;
109 etiss_uint8 rs1 = 0;
110 static BitArrayRange R_rs1_0(19, 15);
111 rs1 += R_rs1_0.read(ba) << 0;
112 etiss_uint8 rs2 = 0;
113 static BitArrayRange R_rs2_0(24, 20);
114 rs2 += R_rs2_0.read(ba) << 0;
115 
116 // -----------------------------------------------------------------------------
117 
118  std::stringstream ss;
119 // -----------------------------------------------------------------------------
120 ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
121 // -----------------------------------------------------------------------------
122  return ss.str();
123  }
124 );
125 
126 // DIVU ------------------------------------------------------------------------
127 static InstructionDefinition divu_rd_rs1_rs2 (
128  ISA32_RV64IMACFD,
129  "divu",
130  (uint32_t) 0x2005033,
131  (uint32_t) 0xfe00707f,
132  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
133  {
134 
135 // -----------------------------------------------------------------------------
136 
137 // -----------------------------------------------------------------------------
138 
139 // -----------------------------------------------------------------------------
140 etiss_uint8 rd = 0;
141 static BitArrayRange R_rd_0(11, 7);
142 rd += R_rd_0.read(ba) << 0;
143 etiss_uint8 rs1 = 0;
144 static BitArrayRange R_rs1_0(19, 15);
145 rs1 += R_rs1_0.read(ba) << 0;
146 etiss_uint8 rs2 = 0;
147 static BitArrayRange R_rs2_0(24, 20);
148 rs2 += R_rs2_0.read(ba) << 0;
149 
150 // -----------------------------------------------------------------------------
151 
152  {
153  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
154 
155  cp.code() = std::string("//DIVU\n");
156 
157 // -----------------------------------------------------------------------------
158 cp.code() += "etiss_coverage_count(1, 77);\n";
159 { // block
160 cp.code() += "etiss_coverage_count(1, 1169);\n";
161 cp.code() += "{ // block\n";
162 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
163 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
164 cp.code() += "} // block\n";
165 } // block
166 { // block
167 cp.code() += "etiss_coverage_count(1, 3086);\n";
168 cp.code() += "{ // block\n";
169 cp.code() += "etiss_coverage_count(1, 3045);\n";
170 if ((rd % 32ULL) != 0LL) { // conditional
171 cp.code() += "etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";
172 { // block
173 cp.code() += "etiss_coverage_count(1, 3085);\n";
174 cp.code() += "{ // block\n";
175 cp.code() += "etiss_coverage_count(1, 3052);\n";
176 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
177 cp.code() += "etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";
178 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
179 cp.code() += "etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";
180 cp.code() += "} // conditional\n";
181 cp.code() += "else { // conditional\n";
182 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
183 cp.code() += "etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";
184 cp.code() += "} // conditional\n";
185 cp.code() += "} // block\n";
186 } // block
187 } // conditional
188 cp.code() += "} // block\n";
189 } // block
190 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
191 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
192 // -----------------------------------------------------------------------------
193  cp.getAffectedRegisters().add("instructionPointer", 32);
194  }
195 
196  return true;
197  },
198  0,
199  [] (BitArray & ba, Instruction & instr)
200  {
201 // -----------------------------------------------------------------------------
202 etiss_uint8 rd = 0;
203 static BitArrayRange R_rd_0(11, 7);
204 rd += R_rd_0.read(ba) << 0;
205 etiss_uint8 rs1 = 0;
206 static BitArrayRange R_rs1_0(19, 15);
207 rs1 += R_rs1_0.read(ba) << 0;
208 etiss_uint8 rs2 = 0;
209 static BitArrayRange R_rs2_0(24, 20);
210 rs2 += R_rs2_0.read(ba) << 0;
211 
212 // -----------------------------------------------------------------------------
213 
214  std::stringstream ss;
215 // -----------------------------------------------------------------------------
216 ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
217 // -----------------------------------------------------------------------------
218  return ss.str();
219  }
220 );
221 
222 // REM -------------------------------------------------------------------------
223 static InstructionDefinition rem_rd_rs1_rs2 (
224  ISA32_RV64IMACFD,
225  "rem",
226  (uint32_t) 0x2006033,
227  (uint32_t) 0xfe00707f,
228  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
229  {
230 
231 // -----------------------------------------------------------------------------
232 
233 // -----------------------------------------------------------------------------
234 
235 // -----------------------------------------------------------------------------
236 etiss_uint8 rd = 0;
237 static BitArrayRange R_rd_0(11, 7);
238 rd += R_rd_0.read(ba) << 0;
239 etiss_uint8 rs1 = 0;
240 static BitArrayRange R_rs1_0(19, 15);
241 rs1 += R_rs1_0.read(ba) << 0;
242 etiss_uint8 rs2 = 0;
243 static BitArrayRange R_rs2_0(24, 20);
244 rs2 += R_rs2_0.read(ba) << 0;
245 
246 // -----------------------------------------------------------------------------
247 
248  {
249  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
250 
251  cp.code() = std::string("//REM\n");
252 
253 // -----------------------------------------------------------------------------
254 cp.code() += "etiss_coverage_count(1, 78);\n";
255 { // block
256 cp.code() += "etiss_coverage_count(1, 1169);\n";
257 cp.code() += "{ // block\n";
258 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
259 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
260 cp.code() += "} // block\n";
261 } // block
262 { // block
263 cp.code() += "etiss_coverage_count(1, 3170);\n";
264 cp.code() += "{ // block\n";
265 cp.code() += "etiss_coverage_count(1, 3087);\n";
266 if ((rd % 32ULL) != 0LL) { // conditional
267 cp.code() += "etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";
268 { // block
269 cp.code() += "etiss_coverage_count(1, 3169);\n";
270 cp.code() += "{ // block\n";
271 cp.code() += "etiss_coverage_count(1, 3094);\n";
272 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
273 cp.code() += "etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";
274 { // block
275 cp.code() += "etiss_coverage_count(1, 3157);\n";
276 cp.code() += "{ // block\n";
277 etiss_uint64 MMIN = 9223372036854775808ULL;
278 cp.code() += "etiss_coverage_count(1, 3109);\n";
279 cp.code() += "etiss_coverage_count(1, 3110);\n";
280 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
281 cp.code() += "etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";
282 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
283 cp.code() += "etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";
284 cp.code() += "} // conditional\n";
285 cp.code() += "else { // conditional\n";
286 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
287 cp.code() += "etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";
288 cp.code() += "} // conditional\n";
289 cp.code() += "} // block\n";
290 } // block
291 cp.code() += "} // conditional\n";
292 cp.code() += "else { // conditional\n";
293 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
294 cp.code() += "etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";
295 cp.code() += "} // conditional\n";
296 cp.code() += "} // block\n";
297 } // block
298 } // conditional
299 cp.code() += "} // block\n";
300 } // block
301 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
302 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
303 // -----------------------------------------------------------------------------
304  cp.getAffectedRegisters().add("instructionPointer", 32);
305  }
306 
307  return true;
308  },
309  0,
310  [] (BitArray & ba, Instruction & instr)
311  {
312 // -----------------------------------------------------------------------------
313 etiss_uint8 rd = 0;
314 static BitArrayRange R_rd_0(11, 7);
315 rd += R_rd_0.read(ba) << 0;
316 etiss_uint8 rs1 = 0;
317 static BitArrayRange R_rs1_0(19, 15);
318 rs1 += R_rs1_0.read(ba) << 0;
319 etiss_uint8 rs2 = 0;
320 static BitArrayRange R_rs2_0(24, 20);
321 rs2 += R_rs2_0.read(ba) << 0;
322 
323 // -----------------------------------------------------------------------------
324 
325  std::stringstream ss;
326 // -----------------------------------------------------------------------------
327 ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
328 // -----------------------------------------------------------------------------
329  return ss.str();
330  }
331 );
332 
333 // REMU ------------------------------------------------------------------------
334 static InstructionDefinition remu_rd_rs1_rs2 (
335  ISA32_RV64IMACFD,
336  "remu",
337  (uint32_t) 0x2007033,
338  (uint32_t) 0xfe00707f,
339  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
340  {
341 
342 // -----------------------------------------------------------------------------
343 
344 // -----------------------------------------------------------------------------
345 
346 // -----------------------------------------------------------------------------
347 etiss_uint8 rd = 0;
348 static BitArrayRange R_rd_0(11, 7);
349 rd += R_rd_0.read(ba) << 0;
350 etiss_uint8 rs1 = 0;
351 static BitArrayRange R_rs1_0(19, 15);
352 rs1 += R_rs1_0.read(ba) << 0;
353 etiss_uint8 rs2 = 0;
354 static BitArrayRange R_rs2_0(24, 20);
355 rs2 += R_rs2_0.read(ba) << 0;
356 
357 // -----------------------------------------------------------------------------
358 
359  {
360  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
361 
362  cp.code() = std::string("//REMU\n");
363 
364 // -----------------------------------------------------------------------------
365 cp.code() += "etiss_coverage_count(1, 79);\n";
366 { // block
367 cp.code() += "etiss_coverage_count(1, 1169);\n";
368 cp.code() += "{ // block\n";
369 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
370 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
371 cp.code() += "} // block\n";
372 } // block
373 { // block
374 cp.code() += "etiss_coverage_count(1, 3215);\n";
375 cp.code() += "{ // block\n";
376 cp.code() += "etiss_coverage_count(1, 3171);\n";
377 if ((rd % 32ULL) != 0LL) { // conditional
378 cp.code() += "etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";
379 { // block
380 cp.code() += "etiss_coverage_count(1, 3214);\n";
381 cp.code() += "{ // block\n";
382 cp.code() += "etiss_coverage_count(1, 3178);\n";
383 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
384 cp.code() += "etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";
385 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
386 cp.code() += "etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";
387 cp.code() += "} // conditional\n";
388 cp.code() += "else { // conditional\n";
389 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
390 cp.code() += "etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";
391 cp.code() += "} // conditional\n";
392 cp.code() += "} // block\n";
393 } // block
394 } // conditional
395 cp.code() += "} // block\n";
396 } // block
397 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
398 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
399 // -----------------------------------------------------------------------------
400  cp.getAffectedRegisters().add("instructionPointer", 32);
401  }
402 
403  return true;
404  },
405  0,
406  [] (BitArray & ba, Instruction & instr)
407  {
408 // -----------------------------------------------------------------------------
409 etiss_uint8 rd = 0;
410 static BitArrayRange R_rd_0(11, 7);
411 rd += R_rd_0.read(ba) << 0;
412 etiss_uint8 rs1 = 0;
413 static BitArrayRange R_rs1_0(19, 15);
414 rs1 += R_rs1_0.read(ba) << 0;
415 etiss_uint8 rs2 = 0;
416 static BitArrayRange R_rs2_0(24, 20);
417 rs2 += R_rs2_0.read(ba) << 0;
418 
419 // -----------------------------------------------------------------------------
420 
421  std::stringstream ss;
422 // -----------------------------------------------------------------------------
423 ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
424 // -----------------------------------------------------------------------------
425  return ss.str();
426  }
427 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV64IMACFD, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3044);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2964);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";{ cp.code()+="etiss_coverage_count(1, 3043);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2971);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";{ cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 2986);\n";cp.code()+="etiss_coverage_count(1, 2987);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV64IMACFD, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3215);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3171);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";{ cp.code()+="etiss_coverage_count(1, 3214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3178);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV64IMACFD, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3086);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3045);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";{ cp.code()+="etiss_coverage_count(1, 3085);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3052);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV64IMACFD, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3170);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3087);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";{ cp.code()+="etiss_coverage_count(1, 3169);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3094);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";{ cp.code()+="etiss_coverage_count(1, 3157);\n";cp.code()+="{ // block\n";etiss_uint64 MMIN=9223372036854775808ULL;cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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