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| static InstructionDefinition | fld_rd_rs1_imm (ISA32_RV64IMACFD, "fld",(uint32_t) 0x003007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="etiss_coverage_count(1, 118);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5067);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5038, 5037, 5033, 5032, 5030, 5036, 5034);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 5045, 5044, 5042, 5041);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5054, 5052, 5051, 5053);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();}) |
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| static InstructionDefinition | fsd_imm_rs1_rs2 (ISA32_RV64IMACFD, "fsd",(uint32_t) 0x003027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="etiss_coverage_count(1, 119);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5088);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5078, 5077, 5073, 5072, 5070, 5076, 5074);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5087, 5081, 5080, 5086, 5084, 5083);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fmadd_d_rd_rm_rs1_rs2_rs3 (ISA32_RV64IMACFD, "fmadd_d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_D\n");cp.code()+="etiss_coverage_count(1, 120);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5146);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5109, 5108, 5094, 5092, 5091, 5099, 5097, 5096, 5104, 5102, 5101, 5105, 5107, 5106);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5118, 5116, 5115, 5117);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5133, 5132);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5145, 5134, 5144, 5138, 5135, 5139, 5142, 5140, 5143);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();}) |
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| static InstructionDefinition | fmsub_d_rd_rm_rs1_rs2_rs3 (ISA32_RV64IMACFD, "fmsub_d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_D\n");cp.code()+="etiss_coverage_count(1, 121);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5204);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5167, 5166, 5152, 5150, 5149, 5157, 5155, 5154, 5162, 5160, 5159, 5163, 5165, 5164);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5176, 5174, 5173, 5175);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5191, 5190);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5203, 5192, 5202, 5196, 5193, 5197, 5200, 5198, 5201);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();}) |
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| static InstructionDefinition | fnmadd_d_rd_rm_rs1_rs2_rs3 (ISA32_RV64IMACFD, "fnmadd_d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_D\n");cp.code()+="etiss_coverage_count(1, 122);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5262);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5225, 5224, 5210, 5208, 5207, 5215, 5213, 5212, 5220, 5218, 5217, 5221, 5223, 5222);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5234, 5232, 5231, 5233);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5249, 5248);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5261, 5250, 5260, 5254, 5251, 5255, 5258, 5256, 5259);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();}) |
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| static InstructionDefinition | fnmsub_d_rd_rm_rs1_rs2_rs3 (ISA32_RV64IMACFD, "fnmsub_d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_D\n");cp.code()+="etiss_coverage_count(1, 123);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5283, 5282, 5268, 5266, 5265, 5273, 5271, 5270, 5278, 5276, 5275, 5279, 5281, 5280);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5292, 5290, 5289, 5291);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5307, 5306);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5319, 5308, 5318, 5312, 5309, 5313, 5316, 5314, 5317);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();}) |
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| static InstructionDefinition | fadd_d_rd_rm_rs1_rs2 (ISA32_RV64IMACFD, "fadd_d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_D\n");cp.code()+="etiss_coverage_count(1, 124);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5335, 5334, 5326, 5324, 5323, 5331, 5329, 5328, 5333, 5332);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5344, 5342, 5341, 5343);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5359, 5358);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5371, 5360, 5370, 5364, 5361, 5365, 5368, 5366, 5369);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fsub_d_rd_rm_rs1_rs2 (ISA32_RV64IMACFD, "fsub_d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_D\n");cp.code()+="etiss_coverage_count(1, 125);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5424);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5387, 5386, 5378, 5376, 5375, 5383, 5381, 5380, 5385, 5384);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5396, 5394, 5393, 5395);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5411, 5410);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5423, 5412, 5422, 5416, 5413, 5417, 5420, 5418, 5421);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fmul_d_rd_rm_rs1_rs2 (ISA32_RV64IMACFD, "fmul_d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_D\n");cp.code()+="etiss_coverage_count(1, 126);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5476);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5439, 5438, 5430, 5428, 5427, 5435, 5433, 5432, 5437, 5436);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5448, 5446, 5445, 5447);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5463, 5462);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5475, 5464, 5474, 5468, 5465, 5469, 5472, 5470, 5473);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fdiv_d_rd_rm_rs1_rs2 (ISA32_RV64IMACFD, "fdiv_d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_D\n");cp.code()+="etiss_coverage_count(1, 127);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5528);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5491, 5490, 5482, 5480, 5479, 5487, 5485, 5484, 5489, 5488);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5500, 5498, 5497, 5499);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5515, 5514);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5527, 5516, 5526, 5520, 5517, 5521, 5524, 5522, 5525);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fsqrt_d_rd_rm_rs1 (ISA32_RV64IMACFD, "fsqrt_d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_D\n");cp.code()+="etiss_coverage_count(1, 128);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5575);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(7, 5538, 5537, 5534, 5532, 5531, 5536, 5535);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5547, 5545, 5544, 5546);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5562, 5561);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5574, 5563, 5573, 5567, 5564, 5568, 5571, 5569, 5572);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fsgnj_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fsgnj_d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_D\n");cp.code()+="etiss_coverage_count(1, 129);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5612);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL)) << 63) | ((((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="etiss_coverage_count(12, 5590, 5589, 5582, 5579, 5578, 5580, 5581, 5588, 5585, 5584, 5586, 5587);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5599, 5597, 5596, 5598);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fsgnjn_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fsgnjn_d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_D\n");cp.code()+="etiss_coverage_count(1, 130);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5650);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL))) << 63) | ((((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="etiss_coverage_count(13, 5628, 5627, 5620, 5619, 5616, 5615, 5617, 5618, 5626, 5623, 5622, 5624, 5625);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5637, 5635, 5634, 5636);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fsgnjx_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fsgnjx_d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_D\n");cp.code()+="etiss_coverage_count(1, 131);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5691);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) & 9223372036854775808ULL);\n";cp.code()+="etiss_coverage_count(10, 5669, 5668, 5656, 5654, 5653, 5666, 5661, 5659, 5658, 5667);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5678, 5676, 5675, 5677);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fmin_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fmin_d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_D\n");cp.code()+="etiss_coverage_count(1, 132);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5742);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 0LL);\n";cp.code()+="etiss_coverage_count(9, 5705, 5704, 5697, 5695, 5694, 5702, 5700, 5699, 5703);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5714, 5712, 5711, 5713);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5729, 5728);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5741, 5730, 5740, 5734, 5731, 5735, 5738, 5736, 5739);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fmax_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fmax_d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_D\n");cp.code()+="etiss_coverage_count(1, 133);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5793);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 1ULL);\n";cp.code()+="etiss_coverage_count(9, 5756, 5755, 5748, 5746, 5745, 5753, 5751, 5750, 5754);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5765, 5763, 5762, 5764);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5780, 5779);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5792, 5781, 5791, 5785, 5782, 5786, 5789, 5787, 5790);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_s_d_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_s_d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_D\n");cp.code()+="etiss_coverage_count(1, 134);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5812);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(5, 5800, 5799, 5797, 5796, 5798);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL + res;\n";cp.code()+="etiss_coverage_count(5, 5811, 5803, 5802, 5810, 5809);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_d_s_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_d_s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_S\n");cp.code()+="etiss_coverage_count(1, 135);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5843);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 5820, 5819, 5817, 5816, 5815, 5818);\n";{ cp.code()+="etiss_coverage_count(1, 5830);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5829, 5827, 5826, 5828);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | feq_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "feq_d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_D\n");cp.code()+="etiss_coverage_count(1, 136);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5909);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5846, 5845);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 0LL);\n";cp.code()+="etiss_coverage_count(8, 5860, 5851, 5859, 5854, 5853, 5857, 5856, 5858);\n";cp.code()+="etiss_coverage_count(1, 5880);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5886, 5883, 5881, 5884, 5885);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5893, 5891, 5890, 5888, 5892);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5896, 5895);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5908, 5897, 5907, 5901, 5898, 5902, 5905, 5903, 5906);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | flt_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "flt_d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_D\n");cp.code()+="etiss_coverage_count(1, 137);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5975);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5912, 5911);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 2ULL);\n";cp.code()+="etiss_coverage_count(8, 5926, 5917, 5925, 5920, 5919, 5923, 5922, 5924);\n";cp.code()+="etiss_coverage_count(1, 5946);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5952, 5949, 5947, 5950, 5951);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5959, 5957, 5956, 5954, 5958);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5962, 5961);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5974, 5963, 5973, 5967, 5964, 5968, 5971, 5969, 5972);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fle_d_rd_rs1_rs2 (ISA32_RV64IMACFD, "fle_d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_D\n");cp.code()+="etiss_coverage_count(1, 138);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6041);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5978, 5977);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 1ULL);\n";cp.code()+="etiss_coverage_count(8, 5992, 5983, 5991, 5986, 5985, 5989, 5988, 5990);\n";cp.code()+="etiss_coverage_count(1, 6012);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6018, 6015, 6013, 6016, 6017);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6025, 6023, 6022, 6020, 6024);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6028, 6027);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6040, 6029, 6039, 6033, 6030, 6034, 6037, 6035, 6038);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();}) |
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| static InstructionDefinition | fclass_d_rd_rs1 (ISA32_RV64IMACFD, "fclass_d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_D\n");cp.code()+="etiss_coverage_count(1, 139);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6054);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(8, 6053, 6046, 6045, 6043, 6052, 6051, 6049, 6048);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_w_d_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_w_d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_D\n");cp.code()+="etiss_coverage_count(1, 140);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6112);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6057, 6056);\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6069, 6062, 6068, 6065, 6064, 6066, 6067);\n";cp.code()+="etiss_coverage_count(1, 6083);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6089, 6086, 6084, 6087, 6088);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6096, 6094, 6093, 6091, 6095);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6099, 6098);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6111, 6100, 6110, 6104, 6101, 6105, 6108, 6106, 6109);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_wu_d_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_wu_d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_D\n");cp.code()+="etiss_coverage_count(1, 141);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6173);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6115, 6114);\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6127, 6120, 6126, 6123, 6122, 6124, 6125);\n";cp.code()+="etiss_coverage_count(1, 6141);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6147, 6144, 6142, 6145, 6146);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(7, 6157, 6152, 6151, 6149, 6156, 6154, 6153);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6160, 6159);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6172, 6161, 6171, 6165, 6162, 6166, 6169, 6167, 6170);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_d_w_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_d_w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_W\n");cp.code()+="etiss_coverage_count(1, 142);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6206);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6184, 6183, 6180, 6179, 6178, 6176, 6181, 6182);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6193, 6191, 6190, 6192);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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| static InstructionDefinition | fcvt_d_wu_rd_rm_rs1 (ISA32_RV64IMACFD, "fcvt_d_wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_WU\n");cp.code()+="etiss_coverage_count(1, 143);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6239);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6217, 6216, 6213, 6212, 6211, 6209, 6214, 6215);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6226, 6224, 6223, 6225);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();}) |
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