ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_RV32DInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// FLD -------------------------------------------------------------------------
16static InstructionDefinition fld_rd_rs1_imm (
17 ISA32_RV64IMACFD,
18 "fld",
19 (uint32_t) 0x003007,
20 (uint32_t) 0x00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint16 imm = 0;
37static BitArrayRange R_imm_0(31, 20);
38imm += R_imm_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//FLD\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 118);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1169);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
54cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 5067);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
61cp.code() += "etiss_coverage_count(7, 5038, 5037, 5033, 5032, 5030, 5036, 5034);\n";
62cp.code() += "etiss_uint64 mem_val_0;\n";
63cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
64cp.code() += "if (cpu->exception) { // conditional\n";
65{ // procedure
66cp.code() += "{ // procedure\n";
67cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
68cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
69cp.code() += "} // procedure\n";
70} // procedure
71cp.code() += "} // conditional\n";
72cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
73cp.code() += "etiss_coverage_count(4, 5045, 5044, 5042, 5041);\n";
74cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
75cp.code() += "etiss_coverage_count(4, 5054, 5052, 5051, 5053);\n";
76cp.code() += "} // block\n";
77} // block
78cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
79cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
80// -----------------------------------------------------------------------------
81 cp.getAffectedRegisters().add("instructionPointer", 32);
82 }
83 {
84 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
85
86 cp.code() = std::string("//FLD\n");
87
88// -----------------------------------------------------------------------------
89cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
90// -----------------------------------------------------------------------------
91 }
92
93 return true;
94 },
95 0,
96 [] (BitArray & ba, Instruction & instr)
97 {
98// -----------------------------------------------------------------------------
99etiss_uint8 rd = 0;
100static BitArrayRange R_rd_0(11, 7);
101rd += R_rd_0.read(ba) << 0;
102etiss_uint8 rs1 = 0;
103static BitArrayRange R_rs1_0(19, 15);
104rs1 += R_rs1_0.read(ba) << 0;
105etiss_uint16 imm = 0;
106static BitArrayRange R_imm_0(31, 20);
107imm += R_imm_0.read(ba) << 0;
108
109// -----------------------------------------------------------------------------
110
111 std::stringstream ss;
112// -----------------------------------------------------------------------------
113ss << "fld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
114// -----------------------------------------------------------------------------
115 return ss.str();
116 }
117);
118
119// FSD -------------------------------------------------------------------------
120static InstructionDefinition fsd_imm_rs1_rs2 (
121 ISA32_RV64IMACFD,
122 "fsd",
123 (uint32_t) 0x003027,
124 (uint32_t) 0x00707f,
125 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
126 {
127
128// -----------------------------------------------------------------------------
129
130// -----------------------------------------------------------------------------
131
132// -----------------------------------------------------------------------------
133// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
134etiss_uint16 imm = 0;
135static BitArrayRange R_imm_0(11, 7);
136imm += R_imm_0.read(ba) << 0;
137etiss_uint8 rs1 = 0;
138static BitArrayRange R_rs1_0(19, 15);
139rs1 += R_rs1_0.read(ba) << 0;
140etiss_uint8 rs2 = 0;
141static BitArrayRange R_rs2_0(24, 20);
142rs2 += R_rs2_0.read(ba) << 0;
143static BitArrayRange R_imm_5(31, 25);
144imm += R_imm_5.read(ba) << 5;
145
146// NOLINTEND(clang-diagnostic-unused-but-set-variable)
147// -----------------------------------------------------------------------------
148
149 {
150 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
151
152 cp.code() = std::string("//FSD\n");
153
154// -----------------------------------------------------------------------------
155cp.code() += "etiss_coverage_count(1, 119);\n";
156{ // block
157cp.code() += "etiss_coverage_count(1, 1169);\n";
158cp.code() += "{ // block\n";
159cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
160cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
161cp.code() += "} // block\n";
162} // block
163{ // block
164cp.code() += "etiss_coverage_count(1, 5088);\n";
165cp.code() += "{ // block\n";
166cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
167cp.code() += "etiss_coverage_count(7, 5078, 5077, 5073, 5072, 5070, 5076, 5074);\n";
168cp.code() += "etiss_uint64 mem_val_0;\n";
169cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
170cp.code() += "etiss_coverage_count(6, 5087, 5081, 5080, 5086, 5084, 5083);\n";
171cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
172cp.code() += "if (cpu->exception) { // conditional\n";
173{ // procedure
174cp.code() += "{ // procedure\n";
175cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
176cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
177cp.code() += "} // procedure\n";
178} // procedure
179cp.code() += "} // conditional\n";
180cp.code() += "} // block\n";
181} // block
182cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
183cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
184// -----------------------------------------------------------------------------
185 cp.getAffectedRegisters().add("instructionPointer", 32);
186 }
187 {
188 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
189
190 cp.code() = std::string("//FSD\n");
191
192// -----------------------------------------------------------------------------
193cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
194// -----------------------------------------------------------------------------
195 }
196
197 return true;
198 },
199 0,
200 [] (BitArray & ba, Instruction & instr)
201 {
202// -----------------------------------------------------------------------------
203etiss_uint16 imm = 0;
204static BitArrayRange R_imm_0(11, 7);
205imm += R_imm_0.read(ba) << 0;
206etiss_uint8 rs1 = 0;
207static BitArrayRange R_rs1_0(19, 15);
208rs1 += R_rs1_0.read(ba) << 0;
209etiss_uint8 rs2 = 0;
210static BitArrayRange R_rs2_0(24, 20);
211rs2 += R_rs2_0.read(ba) << 0;
212static BitArrayRange R_imm_5(31, 25);
213imm += R_imm_5.read(ba) << 5;
214
215// -----------------------------------------------------------------------------
216
217 std::stringstream ss;
218// -----------------------------------------------------------------------------
219ss << "fsd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
220// -----------------------------------------------------------------------------
221 return ss.str();
222 }
223);
224
225// FMADD_D ---------------------------------------------------------------------
226static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 (
227 ISA32_RV64IMACFD,
228 "fmadd_d",
229 (uint32_t) 0x2000043,
230 (uint32_t) 0x600007f,
231 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
232 {
233
234// -----------------------------------------------------------------------------
235
236// -----------------------------------------------------------------------------
237
238// -----------------------------------------------------------------------------
239// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
240etiss_uint8 rd = 0;
241static BitArrayRange R_rd_0(11, 7);
242rd += R_rd_0.read(ba) << 0;
243etiss_uint8 rm = 0;
244static BitArrayRange R_rm_0(14, 12);
245rm += R_rm_0.read(ba) << 0;
246etiss_uint8 rs1 = 0;
247static BitArrayRange R_rs1_0(19, 15);
248rs1 += R_rs1_0.read(ba) << 0;
249etiss_uint8 rs2 = 0;
250static BitArrayRange R_rs2_0(24, 20);
251rs2 += R_rs2_0.read(ba) << 0;
252etiss_uint8 rs3 = 0;
253static BitArrayRange R_rs3_0(31, 27);
254rs3 += R_rs3_0.read(ba) << 0;
255
256// NOLINTEND(clang-diagnostic-unused-but-set-variable)
257// -----------------------------------------------------------------------------
258
259 {
260 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
261
262 cp.code() = std::string("//FMADD_D\n");
263
264// -----------------------------------------------------------------------------
265cp.code() += "etiss_coverage_count(1, 120);\n";
266{ // block
267cp.code() += "etiss_coverage_count(1, 1169);\n";
268cp.code() += "{ // block\n";
269cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
270cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
271cp.code() += "} // block\n";
272} // block
273{ // block
274cp.code() += "etiss_coverage_count(1, 5146);\n";
275cp.code() += "{ // block\n";
276cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
277cp.code() += "etiss_coverage_count(14, 5109, 5108, 5094, 5092, 5091, 5099, 5097, 5096, 5104, 5102, 5101, 5105, 5107, 5106);\n";
278cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
279cp.code() += "etiss_coverage_count(4, 5118, 5116, 5115, 5117);\n";
280cp.code() += "etiss_uint32 flags = fget_flags();\n";
281cp.code() += "etiss_coverage_count(2, 5133, 5132);\n";
282cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
283cp.code() += "etiss_coverage_count(9, 5145, 5134, 5144, 5138, 5135, 5139, 5142, 5140, 5143);\n";
284cp.code() += "} // block\n";
285} // block
286cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
287cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
288// -----------------------------------------------------------------------------
289 cp.getAffectedRegisters().add("instructionPointer", 32);
290 }
291
292 return true;
293 },
294 0,
295 [] (BitArray & ba, Instruction & instr)
296 {
297// -----------------------------------------------------------------------------
298etiss_uint8 rd = 0;
299static BitArrayRange R_rd_0(11, 7);
300rd += R_rd_0.read(ba) << 0;
301etiss_uint8 rm = 0;
302static BitArrayRange R_rm_0(14, 12);
303rm += R_rm_0.read(ba) << 0;
304etiss_uint8 rs1 = 0;
305static BitArrayRange R_rs1_0(19, 15);
306rs1 += R_rs1_0.read(ba) << 0;
307etiss_uint8 rs2 = 0;
308static BitArrayRange R_rs2_0(24, 20);
309rs2 += R_rs2_0.read(ba) << 0;
310etiss_uint8 rs3 = 0;
311static BitArrayRange R_rs3_0(31, 27);
312rs3 += R_rs3_0.read(ba) << 0;
313
314// -----------------------------------------------------------------------------
315
316 std::stringstream ss;
317// -----------------------------------------------------------------------------
318ss << "fmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
319// -----------------------------------------------------------------------------
320 return ss.str();
321 }
322);
323
324// FMSUB_D ---------------------------------------------------------------------
325static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 (
326 ISA32_RV64IMACFD,
327 "fmsub_d",
328 (uint32_t) 0x2000047,
329 (uint32_t) 0x600007f,
330 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
331 {
332
333// -----------------------------------------------------------------------------
334
335// -----------------------------------------------------------------------------
336
337// -----------------------------------------------------------------------------
338// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
339etiss_uint8 rd = 0;
340static BitArrayRange R_rd_0(11, 7);
341rd += R_rd_0.read(ba) << 0;
342etiss_uint8 rm = 0;
343static BitArrayRange R_rm_0(14, 12);
344rm += R_rm_0.read(ba) << 0;
345etiss_uint8 rs1 = 0;
346static BitArrayRange R_rs1_0(19, 15);
347rs1 += R_rs1_0.read(ba) << 0;
348etiss_uint8 rs2 = 0;
349static BitArrayRange R_rs2_0(24, 20);
350rs2 += R_rs2_0.read(ba) << 0;
351etiss_uint8 rs3 = 0;
352static BitArrayRange R_rs3_0(31, 27);
353rs3 += R_rs3_0.read(ba) << 0;
354
355// NOLINTEND(clang-diagnostic-unused-but-set-variable)
356// -----------------------------------------------------------------------------
357
358 {
359 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
360
361 cp.code() = std::string("//FMSUB_D\n");
362
363// -----------------------------------------------------------------------------
364cp.code() += "etiss_coverage_count(1, 121);\n";
365{ // block
366cp.code() += "etiss_coverage_count(1, 1169);\n";
367cp.code() += "{ // block\n";
368cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
369cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
370cp.code() += "} // block\n";
371} // block
372{ // block
373cp.code() += "etiss_coverage_count(1, 5204);\n";
374cp.code() += "{ // block\n";
375cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
376cp.code() += "etiss_coverage_count(14, 5167, 5166, 5152, 5150, 5149, 5157, 5155, 5154, 5162, 5160, 5159, 5163, 5165, 5164);\n";
377cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
378cp.code() += "etiss_coverage_count(4, 5176, 5174, 5173, 5175);\n";
379cp.code() += "etiss_uint32 flags = fget_flags();\n";
380cp.code() += "etiss_coverage_count(2, 5191, 5190);\n";
381cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
382cp.code() += "etiss_coverage_count(9, 5203, 5192, 5202, 5196, 5193, 5197, 5200, 5198, 5201);\n";
383cp.code() += "} // block\n";
384} // block
385cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
386cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
387// -----------------------------------------------------------------------------
388 cp.getAffectedRegisters().add("instructionPointer", 32);
389 }
390
391 return true;
392 },
393 0,
394 [] (BitArray & ba, Instruction & instr)
395 {
396// -----------------------------------------------------------------------------
397etiss_uint8 rd = 0;
398static BitArrayRange R_rd_0(11, 7);
399rd += R_rd_0.read(ba) << 0;
400etiss_uint8 rm = 0;
401static BitArrayRange R_rm_0(14, 12);
402rm += R_rm_0.read(ba) << 0;
403etiss_uint8 rs1 = 0;
404static BitArrayRange R_rs1_0(19, 15);
405rs1 += R_rs1_0.read(ba) << 0;
406etiss_uint8 rs2 = 0;
407static BitArrayRange R_rs2_0(24, 20);
408rs2 += R_rs2_0.read(ba) << 0;
409etiss_uint8 rs3 = 0;
410static BitArrayRange R_rs3_0(31, 27);
411rs3 += R_rs3_0.read(ba) << 0;
412
413// -----------------------------------------------------------------------------
414
415 std::stringstream ss;
416// -----------------------------------------------------------------------------
417ss << "fmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
418// -----------------------------------------------------------------------------
419 return ss.str();
420 }
421);
422
423// FNMADD_D --------------------------------------------------------------------
424static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 (
425 ISA32_RV64IMACFD,
426 "fnmadd_d",
427 (uint32_t) 0x200004f,
428 (uint32_t) 0x600007f,
429 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
430 {
431
432// -----------------------------------------------------------------------------
433
434// -----------------------------------------------------------------------------
435
436// -----------------------------------------------------------------------------
437// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
438etiss_uint8 rd = 0;
439static BitArrayRange R_rd_0(11, 7);
440rd += R_rd_0.read(ba) << 0;
441etiss_uint8 rm = 0;
442static BitArrayRange R_rm_0(14, 12);
443rm += R_rm_0.read(ba) << 0;
444etiss_uint8 rs1 = 0;
445static BitArrayRange R_rs1_0(19, 15);
446rs1 += R_rs1_0.read(ba) << 0;
447etiss_uint8 rs2 = 0;
448static BitArrayRange R_rs2_0(24, 20);
449rs2 += R_rs2_0.read(ba) << 0;
450etiss_uint8 rs3 = 0;
451static BitArrayRange R_rs3_0(31, 27);
452rs3 += R_rs3_0.read(ba) << 0;
453
454// NOLINTEND(clang-diagnostic-unused-but-set-variable)
455// -----------------------------------------------------------------------------
456
457 {
458 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
459
460 cp.code() = std::string("//FNMADD_D\n");
461
462// -----------------------------------------------------------------------------
463cp.code() += "etiss_coverage_count(1, 122);\n";
464{ // block
465cp.code() += "etiss_coverage_count(1, 1169);\n";
466cp.code() += "{ // block\n";
467cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
468cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
469cp.code() += "} // block\n";
470} // block
471{ // block
472cp.code() += "etiss_coverage_count(1, 5262);\n";
473cp.code() += "{ // block\n";
474cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
475cp.code() += "etiss_coverage_count(14, 5225, 5224, 5210, 5208, 5207, 5215, 5213, 5212, 5220, 5218, 5217, 5221, 5223, 5222);\n";
476cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
477cp.code() += "etiss_coverage_count(4, 5234, 5232, 5231, 5233);\n";
478cp.code() += "etiss_uint32 flags = fget_flags();\n";
479cp.code() += "etiss_coverage_count(2, 5249, 5248);\n";
480cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
481cp.code() += "etiss_coverage_count(9, 5261, 5250, 5260, 5254, 5251, 5255, 5258, 5256, 5259);\n";
482cp.code() += "} // block\n";
483} // block
484cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
485cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
486// -----------------------------------------------------------------------------
487 cp.getAffectedRegisters().add("instructionPointer", 32);
488 }
489
490 return true;
491 },
492 0,
493 [] (BitArray & ba, Instruction & instr)
494 {
495// -----------------------------------------------------------------------------
496etiss_uint8 rd = 0;
497static BitArrayRange R_rd_0(11, 7);
498rd += R_rd_0.read(ba) << 0;
499etiss_uint8 rm = 0;
500static BitArrayRange R_rm_0(14, 12);
501rm += R_rm_0.read(ba) << 0;
502etiss_uint8 rs1 = 0;
503static BitArrayRange R_rs1_0(19, 15);
504rs1 += R_rs1_0.read(ba) << 0;
505etiss_uint8 rs2 = 0;
506static BitArrayRange R_rs2_0(24, 20);
507rs2 += R_rs2_0.read(ba) << 0;
508etiss_uint8 rs3 = 0;
509static BitArrayRange R_rs3_0(31, 27);
510rs3 += R_rs3_0.read(ba) << 0;
511
512// -----------------------------------------------------------------------------
513
514 std::stringstream ss;
515// -----------------------------------------------------------------------------
516ss << "fnmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
517// -----------------------------------------------------------------------------
518 return ss.str();
519 }
520);
521
522// FNMSUB_D --------------------------------------------------------------------
523static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 (
524 ISA32_RV64IMACFD,
525 "fnmsub_d",
526 (uint32_t) 0x200004b,
527 (uint32_t) 0x600007f,
528 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
529 {
530
531// -----------------------------------------------------------------------------
532
533// -----------------------------------------------------------------------------
534
535// -----------------------------------------------------------------------------
536// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
537etiss_uint8 rd = 0;
538static BitArrayRange R_rd_0(11, 7);
539rd += R_rd_0.read(ba) << 0;
540etiss_uint8 rm = 0;
541static BitArrayRange R_rm_0(14, 12);
542rm += R_rm_0.read(ba) << 0;
543etiss_uint8 rs1 = 0;
544static BitArrayRange R_rs1_0(19, 15);
545rs1 += R_rs1_0.read(ba) << 0;
546etiss_uint8 rs2 = 0;
547static BitArrayRange R_rs2_0(24, 20);
548rs2 += R_rs2_0.read(ba) << 0;
549etiss_uint8 rs3 = 0;
550static BitArrayRange R_rs3_0(31, 27);
551rs3 += R_rs3_0.read(ba) << 0;
552
553// NOLINTEND(clang-diagnostic-unused-but-set-variable)
554// -----------------------------------------------------------------------------
555
556 {
557 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
558
559 cp.code() = std::string("//FNMSUB_D\n");
560
561// -----------------------------------------------------------------------------
562cp.code() += "etiss_coverage_count(1, 123);\n";
563{ // block
564cp.code() += "etiss_coverage_count(1, 1169);\n";
565cp.code() += "{ // block\n";
566cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
567cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
568cp.code() += "} // block\n";
569} // block
570{ // block
571cp.code() += "etiss_coverage_count(1, 5320);\n";
572cp.code() += "{ // block\n";
573cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
574cp.code() += "etiss_coverage_count(14, 5283, 5282, 5268, 5266, 5265, 5273, 5271, 5270, 5278, 5276, 5275, 5279, 5281, 5280);\n";
575cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
576cp.code() += "etiss_coverage_count(4, 5292, 5290, 5289, 5291);\n";
577cp.code() += "etiss_uint32 flags = fget_flags();\n";
578cp.code() += "etiss_coverage_count(2, 5307, 5306);\n";
579cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
580cp.code() += "etiss_coverage_count(9, 5319, 5308, 5318, 5312, 5309, 5313, 5316, 5314, 5317);\n";
581cp.code() += "} // block\n";
582} // block
583cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
584cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
585// -----------------------------------------------------------------------------
586 cp.getAffectedRegisters().add("instructionPointer", 32);
587 }
588
589 return true;
590 },
591 0,
592 [] (BitArray & ba, Instruction & instr)
593 {
594// -----------------------------------------------------------------------------
595etiss_uint8 rd = 0;
596static BitArrayRange R_rd_0(11, 7);
597rd += R_rd_0.read(ba) << 0;
598etiss_uint8 rm = 0;
599static BitArrayRange R_rm_0(14, 12);
600rm += R_rm_0.read(ba) << 0;
601etiss_uint8 rs1 = 0;
602static BitArrayRange R_rs1_0(19, 15);
603rs1 += R_rs1_0.read(ba) << 0;
604etiss_uint8 rs2 = 0;
605static BitArrayRange R_rs2_0(24, 20);
606rs2 += R_rs2_0.read(ba) << 0;
607etiss_uint8 rs3 = 0;
608static BitArrayRange R_rs3_0(31, 27);
609rs3 += R_rs3_0.read(ba) << 0;
610
611// -----------------------------------------------------------------------------
612
613 std::stringstream ss;
614// -----------------------------------------------------------------------------
615ss << "fnmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
616// -----------------------------------------------------------------------------
617 return ss.str();
618 }
619);
620
621// FADD_D ----------------------------------------------------------------------
622static InstructionDefinition fadd_d_rd_rm_rs1_rs2 (
623 ISA32_RV64IMACFD,
624 "fadd_d",
625 (uint32_t) 0x2000053,
626 (uint32_t) 0xfe00007f,
627 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
628 {
629
630// -----------------------------------------------------------------------------
631
632// -----------------------------------------------------------------------------
633
634// -----------------------------------------------------------------------------
635// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
636etiss_uint8 rd = 0;
637static BitArrayRange R_rd_0(11, 7);
638rd += R_rd_0.read(ba) << 0;
639etiss_uint8 rm = 0;
640static BitArrayRange R_rm_0(14, 12);
641rm += R_rm_0.read(ba) << 0;
642etiss_uint8 rs1 = 0;
643static BitArrayRange R_rs1_0(19, 15);
644rs1 += R_rs1_0.read(ba) << 0;
645etiss_uint8 rs2 = 0;
646static BitArrayRange R_rs2_0(24, 20);
647rs2 += R_rs2_0.read(ba) << 0;
648
649// NOLINTEND(clang-diagnostic-unused-but-set-variable)
650// -----------------------------------------------------------------------------
651
652 {
653 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
654
655 cp.code() = std::string("//FADD_D\n");
656
657// -----------------------------------------------------------------------------
658cp.code() += "etiss_coverage_count(1, 124);\n";
659{ // block
660cp.code() += "etiss_coverage_count(1, 1169);\n";
661cp.code() += "{ // block\n";
662cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
663cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
664cp.code() += "} // block\n";
665} // block
666{ // block
667cp.code() += "etiss_coverage_count(1, 5372);\n";
668cp.code() += "{ // block\n";
669cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
670cp.code() += "etiss_coverage_count(10, 5335, 5334, 5326, 5324, 5323, 5331, 5329, 5328, 5333, 5332);\n";
671cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
672cp.code() += "etiss_coverage_count(4, 5344, 5342, 5341, 5343);\n";
673cp.code() += "etiss_uint32 flags = fget_flags();\n";
674cp.code() += "etiss_coverage_count(2, 5359, 5358);\n";
675cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
676cp.code() += "etiss_coverage_count(9, 5371, 5360, 5370, 5364, 5361, 5365, 5368, 5366, 5369);\n";
677cp.code() += "} // block\n";
678} // block
679cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
680cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
681// -----------------------------------------------------------------------------
682 cp.getAffectedRegisters().add("instructionPointer", 32);
683 }
684
685 return true;
686 },
687 0,
688 [] (BitArray & ba, Instruction & instr)
689 {
690// -----------------------------------------------------------------------------
691etiss_uint8 rd = 0;
692static BitArrayRange R_rd_0(11, 7);
693rd += R_rd_0.read(ba) << 0;
694etiss_uint8 rm = 0;
695static BitArrayRange R_rm_0(14, 12);
696rm += R_rm_0.read(ba) << 0;
697etiss_uint8 rs1 = 0;
698static BitArrayRange R_rs1_0(19, 15);
699rs1 += R_rs1_0.read(ba) << 0;
700etiss_uint8 rs2 = 0;
701static BitArrayRange R_rs2_0(24, 20);
702rs2 += R_rs2_0.read(ba) << 0;
703
704// -----------------------------------------------------------------------------
705
706 std::stringstream ss;
707// -----------------------------------------------------------------------------
708ss << "fadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
709// -----------------------------------------------------------------------------
710 return ss.str();
711 }
712);
713
714// FSUB_D ----------------------------------------------------------------------
715static InstructionDefinition fsub_d_rd_rm_rs1_rs2 (
716 ISA32_RV64IMACFD,
717 "fsub_d",
718 (uint32_t) 0xa000053,
719 (uint32_t) 0xfe00007f,
720 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
721 {
722
723// -----------------------------------------------------------------------------
724
725// -----------------------------------------------------------------------------
726
727// -----------------------------------------------------------------------------
728// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
729etiss_uint8 rd = 0;
730static BitArrayRange R_rd_0(11, 7);
731rd += R_rd_0.read(ba) << 0;
732etiss_uint8 rm = 0;
733static BitArrayRange R_rm_0(14, 12);
734rm += R_rm_0.read(ba) << 0;
735etiss_uint8 rs1 = 0;
736static BitArrayRange R_rs1_0(19, 15);
737rs1 += R_rs1_0.read(ba) << 0;
738etiss_uint8 rs2 = 0;
739static BitArrayRange R_rs2_0(24, 20);
740rs2 += R_rs2_0.read(ba) << 0;
741
742// NOLINTEND(clang-diagnostic-unused-but-set-variable)
743// -----------------------------------------------------------------------------
744
745 {
746 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
747
748 cp.code() = std::string("//FSUB_D\n");
749
750// -----------------------------------------------------------------------------
751cp.code() += "etiss_coverage_count(1, 125);\n";
752{ // block
753cp.code() += "etiss_coverage_count(1, 1169);\n";
754cp.code() += "{ // block\n";
755cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
756cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
757cp.code() += "} // block\n";
758} // block
759{ // block
760cp.code() += "etiss_coverage_count(1, 5424);\n";
761cp.code() += "{ // block\n";
762cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
763cp.code() += "etiss_coverage_count(10, 5387, 5386, 5378, 5376, 5375, 5383, 5381, 5380, 5385, 5384);\n";
764cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
765cp.code() += "etiss_coverage_count(4, 5396, 5394, 5393, 5395);\n";
766cp.code() += "etiss_uint32 flags = fget_flags();\n";
767cp.code() += "etiss_coverage_count(2, 5411, 5410);\n";
768cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
769cp.code() += "etiss_coverage_count(9, 5423, 5412, 5422, 5416, 5413, 5417, 5420, 5418, 5421);\n";
770cp.code() += "} // block\n";
771} // block
772cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
773cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
774// -----------------------------------------------------------------------------
775 cp.getAffectedRegisters().add("instructionPointer", 32);
776 }
777
778 return true;
779 },
780 0,
781 [] (BitArray & ba, Instruction & instr)
782 {
783// -----------------------------------------------------------------------------
784etiss_uint8 rd = 0;
785static BitArrayRange R_rd_0(11, 7);
786rd += R_rd_0.read(ba) << 0;
787etiss_uint8 rm = 0;
788static BitArrayRange R_rm_0(14, 12);
789rm += R_rm_0.read(ba) << 0;
790etiss_uint8 rs1 = 0;
791static BitArrayRange R_rs1_0(19, 15);
792rs1 += R_rs1_0.read(ba) << 0;
793etiss_uint8 rs2 = 0;
794static BitArrayRange R_rs2_0(24, 20);
795rs2 += R_rs2_0.read(ba) << 0;
796
797// -----------------------------------------------------------------------------
798
799 std::stringstream ss;
800// -----------------------------------------------------------------------------
801ss << "fsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
802// -----------------------------------------------------------------------------
803 return ss.str();
804 }
805);
806
807// FMUL_D ----------------------------------------------------------------------
808static InstructionDefinition fmul_d_rd_rm_rs1_rs2 (
809 ISA32_RV64IMACFD,
810 "fmul_d",
811 (uint32_t) 0x12000053,
812 (uint32_t) 0xfe00007f,
813 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
814 {
815
816// -----------------------------------------------------------------------------
817
818// -----------------------------------------------------------------------------
819
820// -----------------------------------------------------------------------------
821// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
822etiss_uint8 rd = 0;
823static BitArrayRange R_rd_0(11, 7);
824rd += R_rd_0.read(ba) << 0;
825etiss_uint8 rm = 0;
826static BitArrayRange R_rm_0(14, 12);
827rm += R_rm_0.read(ba) << 0;
828etiss_uint8 rs1 = 0;
829static BitArrayRange R_rs1_0(19, 15);
830rs1 += R_rs1_0.read(ba) << 0;
831etiss_uint8 rs2 = 0;
832static BitArrayRange R_rs2_0(24, 20);
833rs2 += R_rs2_0.read(ba) << 0;
834
835// NOLINTEND(clang-diagnostic-unused-but-set-variable)
836// -----------------------------------------------------------------------------
837
838 {
839 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
840
841 cp.code() = std::string("//FMUL_D\n");
842
843// -----------------------------------------------------------------------------
844cp.code() += "etiss_coverage_count(1, 126);\n";
845{ // block
846cp.code() += "etiss_coverage_count(1, 1169);\n";
847cp.code() += "{ // block\n";
848cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
849cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
850cp.code() += "} // block\n";
851} // block
852{ // block
853cp.code() += "etiss_coverage_count(1, 5476);\n";
854cp.code() += "{ // block\n";
855cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
856cp.code() += "etiss_coverage_count(10, 5439, 5438, 5430, 5428, 5427, 5435, 5433, 5432, 5437, 5436);\n";
857cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
858cp.code() += "etiss_coverage_count(4, 5448, 5446, 5445, 5447);\n";
859cp.code() += "etiss_uint32 flags = fget_flags();\n";
860cp.code() += "etiss_coverage_count(2, 5463, 5462);\n";
861cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
862cp.code() += "etiss_coverage_count(9, 5475, 5464, 5474, 5468, 5465, 5469, 5472, 5470, 5473);\n";
863cp.code() += "} // block\n";
864} // block
865cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
866cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
867// -----------------------------------------------------------------------------
868 cp.getAffectedRegisters().add("instructionPointer", 32);
869 }
870
871 return true;
872 },
873 0,
874 [] (BitArray & ba, Instruction & instr)
875 {
876// -----------------------------------------------------------------------------
877etiss_uint8 rd = 0;
878static BitArrayRange R_rd_0(11, 7);
879rd += R_rd_0.read(ba) << 0;
880etiss_uint8 rm = 0;
881static BitArrayRange R_rm_0(14, 12);
882rm += R_rm_0.read(ba) << 0;
883etiss_uint8 rs1 = 0;
884static BitArrayRange R_rs1_0(19, 15);
885rs1 += R_rs1_0.read(ba) << 0;
886etiss_uint8 rs2 = 0;
887static BitArrayRange R_rs2_0(24, 20);
888rs2 += R_rs2_0.read(ba) << 0;
889
890// -----------------------------------------------------------------------------
891
892 std::stringstream ss;
893// -----------------------------------------------------------------------------
894ss << "fmul_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
895// -----------------------------------------------------------------------------
896 return ss.str();
897 }
898);
899
900// FDIV_D ----------------------------------------------------------------------
901static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 (
902 ISA32_RV64IMACFD,
903 "fdiv_d",
904 (uint32_t) 0x1a000053,
905 (uint32_t) 0xfe00007f,
906 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
907 {
908
909// -----------------------------------------------------------------------------
910
911// -----------------------------------------------------------------------------
912
913// -----------------------------------------------------------------------------
914// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
915etiss_uint8 rd = 0;
916static BitArrayRange R_rd_0(11, 7);
917rd += R_rd_0.read(ba) << 0;
918etiss_uint8 rm = 0;
919static BitArrayRange R_rm_0(14, 12);
920rm += R_rm_0.read(ba) << 0;
921etiss_uint8 rs1 = 0;
922static BitArrayRange R_rs1_0(19, 15);
923rs1 += R_rs1_0.read(ba) << 0;
924etiss_uint8 rs2 = 0;
925static BitArrayRange R_rs2_0(24, 20);
926rs2 += R_rs2_0.read(ba) << 0;
927
928// NOLINTEND(clang-diagnostic-unused-but-set-variable)
929// -----------------------------------------------------------------------------
930
931 {
932 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
933
934 cp.code() = std::string("//FDIV_D\n");
935
936// -----------------------------------------------------------------------------
937cp.code() += "etiss_coverage_count(1, 127);\n";
938{ // block
939cp.code() += "etiss_coverage_count(1, 1169);\n";
940cp.code() += "{ // block\n";
941cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
942cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
943cp.code() += "} // block\n";
944} // block
945{ // block
946cp.code() += "etiss_coverage_count(1, 5528);\n";
947cp.code() += "{ // block\n";
948cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
949cp.code() += "etiss_coverage_count(10, 5491, 5490, 5482, 5480, 5479, 5487, 5485, 5484, 5489, 5488);\n";
950cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
951cp.code() += "etiss_coverage_count(4, 5500, 5498, 5497, 5499);\n";
952cp.code() += "etiss_uint32 flags = fget_flags();\n";
953cp.code() += "etiss_coverage_count(2, 5515, 5514);\n";
954cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
955cp.code() += "etiss_coverage_count(9, 5527, 5516, 5526, 5520, 5517, 5521, 5524, 5522, 5525);\n";
956cp.code() += "} // block\n";
957} // block
958cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
959cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
960// -----------------------------------------------------------------------------
961 cp.getAffectedRegisters().add("instructionPointer", 32);
962 }
963
964 return true;
965 },
966 0,
967 [] (BitArray & ba, Instruction & instr)
968 {
969// -----------------------------------------------------------------------------
970etiss_uint8 rd = 0;
971static BitArrayRange R_rd_0(11, 7);
972rd += R_rd_0.read(ba) << 0;
973etiss_uint8 rm = 0;
974static BitArrayRange R_rm_0(14, 12);
975rm += R_rm_0.read(ba) << 0;
976etiss_uint8 rs1 = 0;
977static BitArrayRange R_rs1_0(19, 15);
978rs1 += R_rs1_0.read(ba) << 0;
979etiss_uint8 rs2 = 0;
980static BitArrayRange R_rs2_0(24, 20);
981rs2 += R_rs2_0.read(ba) << 0;
982
983// -----------------------------------------------------------------------------
984
985 std::stringstream ss;
986// -----------------------------------------------------------------------------
987ss << "fdiv_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
988// -----------------------------------------------------------------------------
989 return ss.str();
990 }
991);
992
993// FSQRT_D ---------------------------------------------------------------------
994static InstructionDefinition fsqrt_d_rd_rm_rs1 (
995 ISA32_RV64IMACFD,
996 "fsqrt_d",
997 (uint32_t) 0x5a000053,
998 (uint32_t) 0xfff0007f,
999 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1000 {
1001
1002// -----------------------------------------------------------------------------
1003
1004// -----------------------------------------------------------------------------
1005
1006// -----------------------------------------------------------------------------
1007// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1008etiss_uint8 rd = 0;
1009static BitArrayRange R_rd_0(11, 7);
1010rd += R_rd_0.read(ba) << 0;
1011etiss_uint8 rm = 0;
1012static BitArrayRange R_rm_0(14, 12);
1013rm += R_rm_0.read(ba) << 0;
1014etiss_uint8 rs1 = 0;
1015static BitArrayRange R_rs1_0(19, 15);
1016rs1 += R_rs1_0.read(ba) << 0;
1017
1018// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1019// -----------------------------------------------------------------------------
1020
1021 {
1022 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1023
1024 cp.code() = std::string("//FSQRT_D\n");
1025
1026// -----------------------------------------------------------------------------
1027cp.code() += "etiss_coverage_count(1, 128);\n";
1028{ // block
1029cp.code() += "etiss_coverage_count(1, 1169);\n";
1030cp.code() += "{ // block\n";
1031cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1032cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1033cp.code() += "} // block\n";
1034} // block
1035{ // block
1036cp.code() += "etiss_coverage_count(1, 5575);\n";
1037cp.code() += "{ // block\n";
1038cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1039cp.code() += "etiss_coverage_count(7, 5538, 5537, 5534, 5532, 5531, 5536, 5535);\n";
1040cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1041cp.code() += "etiss_coverage_count(4, 5547, 5545, 5544, 5546);\n";
1042cp.code() += "etiss_uint32 flags = fget_flags();\n";
1043cp.code() += "etiss_coverage_count(2, 5562, 5561);\n";
1044cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1045cp.code() += "etiss_coverage_count(9, 5574, 5563, 5573, 5567, 5564, 5568, 5571, 5569, 5572);\n";
1046cp.code() += "} // block\n";
1047} // block
1048cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1049cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1050// -----------------------------------------------------------------------------
1051 cp.getAffectedRegisters().add("instructionPointer", 32);
1052 }
1053
1054 return true;
1055 },
1056 0,
1057 [] (BitArray & ba, Instruction & instr)
1058 {
1059// -----------------------------------------------------------------------------
1060etiss_uint8 rd = 0;
1061static BitArrayRange R_rd_0(11, 7);
1062rd += R_rd_0.read(ba) << 0;
1063etiss_uint8 rm = 0;
1064static BitArrayRange R_rm_0(14, 12);
1065rm += R_rm_0.read(ba) << 0;
1066etiss_uint8 rs1 = 0;
1067static BitArrayRange R_rs1_0(19, 15);
1068rs1 += R_rs1_0.read(ba) << 0;
1069
1070// -----------------------------------------------------------------------------
1071
1072 std::stringstream ss;
1073// -----------------------------------------------------------------------------
1074ss << "fsqrt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1075// -----------------------------------------------------------------------------
1076 return ss.str();
1077 }
1078);
1079
1080// FSGNJ_D ---------------------------------------------------------------------
1081static InstructionDefinition fsgnj_d_rd_rs1_rs2 (
1082 ISA32_RV64IMACFD,
1083 "fsgnj_d",
1084 (uint32_t) 0x22000053,
1085 (uint32_t) 0xfe00707f,
1086 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1087 {
1088
1089// -----------------------------------------------------------------------------
1090
1091// -----------------------------------------------------------------------------
1092
1093// -----------------------------------------------------------------------------
1094// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1095etiss_uint8 rd = 0;
1096static BitArrayRange R_rd_0(11, 7);
1097rd += R_rd_0.read(ba) << 0;
1098etiss_uint8 rs1 = 0;
1099static BitArrayRange R_rs1_0(19, 15);
1100rs1 += R_rs1_0.read(ba) << 0;
1101etiss_uint8 rs2 = 0;
1102static BitArrayRange R_rs2_0(24, 20);
1103rs2 += R_rs2_0.read(ba) << 0;
1104
1105// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1106// -----------------------------------------------------------------------------
1107
1108 {
1109 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1110
1111 cp.code() = std::string("//FSGNJ_D\n");
1112
1113// -----------------------------------------------------------------------------
1114cp.code() += "etiss_coverage_count(1, 129);\n";
1115{ // block
1116cp.code() += "etiss_coverage_count(1, 1169);\n";
1117cp.code() += "{ // block\n";
1118cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1119cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1120cp.code() += "} // block\n";
1121} // block
1122{ // block
1123cp.code() += "etiss_coverage_count(1, 5612);\n";
1124cp.code() += "{ // block\n";
1125cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 0x1ULL)) << 63) | (((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) & 0x7fffffffffffffffULL)));\n";
1126cp.code() += "etiss_coverage_count(12, 5590, 5589, 5582, 5579, 5578, 5580, 5581, 5588, 5585, 5584, 5586, 5587);\n";
1127cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1128cp.code() += "etiss_coverage_count(4, 5599, 5597, 5596, 5598);\n";
1129cp.code() += "} // block\n";
1130} // block
1131cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1132cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1133// -----------------------------------------------------------------------------
1134 cp.getAffectedRegisters().add("instructionPointer", 32);
1135 }
1136
1137 return true;
1138 },
1139 0,
1140 [] (BitArray & ba, Instruction & instr)
1141 {
1142// -----------------------------------------------------------------------------
1143etiss_uint8 rd = 0;
1144static BitArrayRange R_rd_0(11, 7);
1145rd += R_rd_0.read(ba) << 0;
1146etiss_uint8 rs1 = 0;
1147static BitArrayRange R_rs1_0(19, 15);
1148rs1 += R_rs1_0.read(ba) << 0;
1149etiss_uint8 rs2 = 0;
1150static BitArrayRange R_rs2_0(24, 20);
1151rs2 += R_rs2_0.read(ba) << 0;
1152
1153// -----------------------------------------------------------------------------
1154
1155 std::stringstream ss;
1156// -----------------------------------------------------------------------------
1157ss << "fsgnj_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1158// -----------------------------------------------------------------------------
1159 return ss.str();
1160 }
1161);
1162
1163// FSGNJN_D --------------------------------------------------------------------
1164static InstructionDefinition fsgnjn_d_rd_rs1_rs2 (
1165 ISA32_RV64IMACFD,
1166 "fsgnjn_d",
1167 (uint32_t) 0x22001053,
1168 (uint32_t) 0xfe00707f,
1169 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1170 {
1171
1172// -----------------------------------------------------------------------------
1173
1174// -----------------------------------------------------------------------------
1175
1176// -----------------------------------------------------------------------------
1177// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1178etiss_uint8 rd = 0;
1179static BitArrayRange R_rd_0(11, 7);
1180rd += R_rd_0.read(ba) << 0;
1181etiss_uint8 rs1 = 0;
1182static BitArrayRange R_rs1_0(19, 15);
1183rs1 += R_rs1_0.read(ba) << 0;
1184etiss_uint8 rs2 = 0;
1185static BitArrayRange R_rs2_0(24, 20);
1186rs2 += R_rs2_0.read(ba) << 0;
1187
1188// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1189// -----------------------------------------------------------------------------
1190
1191 {
1192 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1193
1194 cp.code() = std::string("//FSGNJN_D\n");
1195
1196// -----------------------------------------------------------------------------
1197cp.code() += "etiss_coverage_count(1, 130);\n";
1198{ // block
1199cp.code() += "etiss_coverage_count(1, 1169);\n";
1200cp.code() += "{ // block\n";
1201cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1202cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1203cp.code() += "} // block\n";
1204} // block
1205{ // block
1206cp.code() += "etiss_coverage_count(1, 5650);\n";
1207cp.code() += "{ // block\n";
1208cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 0x1ULL))) << 63) | (((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) & 0x7fffffffffffffffULL)));\n";
1209cp.code() += "etiss_coverage_count(13, 5628, 5627, 5620, 5619, 5616, 5615, 5617, 5618, 5626, 5623, 5622, 5624, 5625);\n";
1210cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1211cp.code() += "etiss_coverage_count(4, 5637, 5635, 5634, 5636);\n";
1212cp.code() += "} // block\n";
1213} // block
1214cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1215cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1216// -----------------------------------------------------------------------------
1217 cp.getAffectedRegisters().add("instructionPointer", 32);
1218 }
1219
1220 return true;
1221 },
1222 0,
1223 [] (BitArray & ba, Instruction & instr)
1224 {
1225// -----------------------------------------------------------------------------
1226etiss_uint8 rd = 0;
1227static BitArrayRange R_rd_0(11, 7);
1228rd += R_rd_0.read(ba) << 0;
1229etiss_uint8 rs1 = 0;
1230static BitArrayRange R_rs1_0(19, 15);
1231rs1 += R_rs1_0.read(ba) << 0;
1232etiss_uint8 rs2 = 0;
1233static BitArrayRange R_rs2_0(24, 20);
1234rs2 += R_rs2_0.read(ba) << 0;
1235
1236// -----------------------------------------------------------------------------
1237
1238 std::stringstream ss;
1239// -----------------------------------------------------------------------------
1240ss << "fsgnjn_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1241// -----------------------------------------------------------------------------
1242 return ss.str();
1243 }
1244);
1245
1246// FSGNJX_D --------------------------------------------------------------------
1247static InstructionDefinition fsgnjx_d_rd_rs1_rs2 (
1248 ISA32_RV64IMACFD,
1249 "fsgnjx_d",
1250 (uint32_t) 0x22002053,
1251 (uint32_t) 0xfe00707f,
1252 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1253 {
1254
1255// -----------------------------------------------------------------------------
1256
1257// -----------------------------------------------------------------------------
1258
1259// -----------------------------------------------------------------------------
1260// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1261etiss_uint8 rd = 0;
1262static BitArrayRange R_rd_0(11, 7);
1263rd += R_rd_0.read(ba) << 0;
1264etiss_uint8 rs1 = 0;
1265static BitArrayRange R_rs1_0(19, 15);
1266rs1 += R_rs1_0.read(ba) << 0;
1267etiss_uint8 rs2 = 0;
1268static BitArrayRange R_rs2_0(24, 20);
1269rs2 += R_rs2_0.read(ba) << 0;
1270
1271// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1272// -----------------------------------------------------------------------------
1273
1274 {
1275 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1276
1277 cp.code() = std::string("//FSGNJX_D\n");
1278
1279// -----------------------------------------------------------------------------
1280cp.code() += "etiss_coverage_count(1, 131);\n";
1281{ // block
1282cp.code() += "etiss_coverage_count(1, 1169);\n";
1283cp.code() += "{ // block\n";
1284cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1285cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1286cp.code() += "} // block\n";
1287} // block
1288{ // block
1289cp.code() += "etiss_coverage_count(1, 5691);\n";
1290cp.code() += "{ // block\n";
1291cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
1292cp.code() += "etiss_coverage_count(10, 5669, 5668, 5656, 5654, 5653, 5666, 5661, 5659, 5658, 5667);\n";
1293cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1294cp.code() += "etiss_coverage_count(4, 5678, 5676, 5675, 5677);\n";
1295cp.code() += "} // block\n";
1296} // block
1297cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1298cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1299// -----------------------------------------------------------------------------
1300 cp.getAffectedRegisters().add("instructionPointer", 32);
1301 }
1302
1303 return true;
1304 },
1305 0,
1306 [] (BitArray & ba, Instruction & instr)
1307 {
1308// -----------------------------------------------------------------------------
1309etiss_uint8 rd = 0;
1310static BitArrayRange R_rd_0(11, 7);
1311rd += R_rd_0.read(ba) << 0;
1312etiss_uint8 rs1 = 0;
1313static BitArrayRange R_rs1_0(19, 15);
1314rs1 += R_rs1_0.read(ba) << 0;
1315etiss_uint8 rs2 = 0;
1316static BitArrayRange R_rs2_0(24, 20);
1317rs2 += R_rs2_0.read(ba) << 0;
1318
1319// -----------------------------------------------------------------------------
1320
1321 std::stringstream ss;
1322// -----------------------------------------------------------------------------
1323ss << "fsgnjx_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1324// -----------------------------------------------------------------------------
1325 return ss.str();
1326 }
1327);
1328
1329// FMIN_D ----------------------------------------------------------------------
1330static InstructionDefinition fmin_d_rd_rs1_rs2 (
1331 ISA32_RV64IMACFD,
1332 "fmin_d",
1333 (uint32_t) 0x2a000053,
1334 (uint32_t) 0xfe00707f,
1335 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1336 {
1337
1338// -----------------------------------------------------------------------------
1339
1340// -----------------------------------------------------------------------------
1341
1342// -----------------------------------------------------------------------------
1343// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1344etiss_uint8 rd = 0;
1345static BitArrayRange R_rd_0(11, 7);
1346rd += R_rd_0.read(ba) << 0;
1347etiss_uint8 rs1 = 0;
1348static BitArrayRange R_rs1_0(19, 15);
1349rs1 += R_rs1_0.read(ba) << 0;
1350etiss_uint8 rs2 = 0;
1351static BitArrayRange R_rs2_0(24, 20);
1352rs2 += R_rs2_0.read(ba) << 0;
1353
1354// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1355// -----------------------------------------------------------------------------
1356
1357 {
1358 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1359
1360 cp.code() = std::string("//FMIN_D\n");
1361
1362// -----------------------------------------------------------------------------
1363cp.code() += "etiss_coverage_count(1, 132);\n";
1364{ // block
1365cp.code() += "etiss_coverage_count(1, 1169);\n";
1366cp.code() += "{ // block\n";
1367cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1368cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1369cp.code() += "} // block\n";
1370} // block
1371{ // block
1372cp.code() += "etiss_coverage_count(1, 5742);\n";
1373cp.code() += "{ // block\n";
1374cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0LL);\n";
1375cp.code() += "etiss_coverage_count(9, 5705, 5704, 5697, 5695, 5694, 5702, 5700, 5699, 5703);\n";
1376cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1377cp.code() += "etiss_coverage_count(4, 5714, 5712, 5711, 5713);\n";
1378cp.code() += "etiss_uint32 flags = fget_flags();\n";
1379cp.code() += "etiss_coverage_count(2, 5729, 5728);\n";
1380cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1381cp.code() += "etiss_coverage_count(9, 5741, 5730, 5740, 5734, 5731, 5735, 5738, 5736, 5739);\n";
1382cp.code() += "} // block\n";
1383} // block
1384cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1385cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1386// -----------------------------------------------------------------------------
1387 cp.getAffectedRegisters().add("instructionPointer", 32);
1388 }
1389
1390 return true;
1391 },
1392 0,
1393 [] (BitArray & ba, Instruction & instr)
1394 {
1395// -----------------------------------------------------------------------------
1396etiss_uint8 rd = 0;
1397static BitArrayRange R_rd_0(11, 7);
1398rd += R_rd_0.read(ba) << 0;
1399etiss_uint8 rs1 = 0;
1400static BitArrayRange R_rs1_0(19, 15);
1401rs1 += R_rs1_0.read(ba) << 0;
1402etiss_uint8 rs2 = 0;
1403static BitArrayRange R_rs2_0(24, 20);
1404rs2 += R_rs2_0.read(ba) << 0;
1405
1406// -----------------------------------------------------------------------------
1407
1408 std::stringstream ss;
1409// -----------------------------------------------------------------------------
1410ss << "fmin_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1411// -----------------------------------------------------------------------------
1412 return ss.str();
1413 }
1414);
1415
1416// FMAX_D ----------------------------------------------------------------------
1417static InstructionDefinition fmax_d_rd_rs1_rs2 (
1418 ISA32_RV64IMACFD,
1419 "fmax_d",
1420 (uint32_t) 0x2a001053,
1421 (uint32_t) 0xfe00707f,
1422 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1423 {
1424
1425// -----------------------------------------------------------------------------
1426
1427// -----------------------------------------------------------------------------
1428
1429// -----------------------------------------------------------------------------
1430// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1431etiss_uint8 rd = 0;
1432static BitArrayRange R_rd_0(11, 7);
1433rd += R_rd_0.read(ba) << 0;
1434etiss_uint8 rs1 = 0;
1435static BitArrayRange R_rs1_0(19, 15);
1436rs1 += R_rs1_0.read(ba) << 0;
1437etiss_uint8 rs2 = 0;
1438static BitArrayRange R_rs2_0(24, 20);
1439rs2 += R_rs2_0.read(ba) << 0;
1440
1441// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1442// -----------------------------------------------------------------------------
1443
1444 {
1445 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1446
1447 cp.code() = std::string("//FMAX_D\n");
1448
1449// -----------------------------------------------------------------------------
1450cp.code() += "etiss_coverage_count(1, 133);\n";
1451{ // block
1452cp.code() += "etiss_coverage_count(1, 1169);\n";
1453cp.code() += "{ // block\n";
1454cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1455cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1456cp.code() += "} // block\n";
1457} // block
1458{ // block
1459cp.code() += "etiss_coverage_count(1, 5793);\n";
1460cp.code() += "{ // block\n";
1461cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
1462cp.code() += "etiss_coverage_count(9, 5756, 5755, 5748, 5746, 5745, 5753, 5751, 5750, 5754);\n";
1463cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1464cp.code() += "etiss_coverage_count(4, 5765, 5763, 5762, 5764);\n";
1465cp.code() += "etiss_uint32 flags = fget_flags();\n";
1466cp.code() += "etiss_coverage_count(2, 5780, 5779);\n";
1467cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1468cp.code() += "etiss_coverage_count(9, 5792, 5781, 5791, 5785, 5782, 5786, 5789, 5787, 5790);\n";
1469cp.code() += "} // block\n";
1470} // block
1471cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1472cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1473// -----------------------------------------------------------------------------
1474 cp.getAffectedRegisters().add("instructionPointer", 32);
1475 }
1476
1477 return true;
1478 },
1479 0,
1480 [] (BitArray & ba, Instruction & instr)
1481 {
1482// -----------------------------------------------------------------------------
1483etiss_uint8 rd = 0;
1484static BitArrayRange R_rd_0(11, 7);
1485rd += R_rd_0.read(ba) << 0;
1486etiss_uint8 rs1 = 0;
1487static BitArrayRange R_rs1_0(19, 15);
1488rs1 += R_rs1_0.read(ba) << 0;
1489etiss_uint8 rs2 = 0;
1490static BitArrayRange R_rs2_0(24, 20);
1491rs2 += R_rs2_0.read(ba) << 0;
1492
1493// -----------------------------------------------------------------------------
1494
1495 std::stringstream ss;
1496// -----------------------------------------------------------------------------
1497ss << "fmax_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1498// -----------------------------------------------------------------------------
1499 return ss.str();
1500 }
1501);
1502
1503// FCVT_S_D --------------------------------------------------------------------
1504static InstructionDefinition fcvt_s_d_rd_rm_rs1 (
1505 ISA32_RV64IMACFD,
1506 "fcvt_s_d",
1507 (uint32_t) 0x40100053,
1508 (uint32_t) 0xfff0007f,
1509 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1510 {
1511
1512// -----------------------------------------------------------------------------
1513
1514// -----------------------------------------------------------------------------
1515
1516// -----------------------------------------------------------------------------
1517// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1518etiss_uint8 rd = 0;
1519static BitArrayRange R_rd_0(11, 7);
1520rd += R_rd_0.read(ba) << 0;
1521etiss_uint8 rm = 0;
1522static BitArrayRange R_rm_0(14, 12);
1523rm += R_rm_0.read(ba) << 0;
1524etiss_uint8 rs1 = 0;
1525static BitArrayRange R_rs1_0(19, 15);
1526rs1 += R_rs1_0.read(ba) << 0;
1527
1528// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1529// -----------------------------------------------------------------------------
1530
1531 {
1532 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1533
1534 cp.code() = std::string("//FCVT_S_D\n");
1535
1536// -----------------------------------------------------------------------------
1537cp.code() += "etiss_coverage_count(1, 134);\n";
1538{ // block
1539cp.code() += "etiss_coverage_count(1, 1169);\n";
1540cp.code() += "{ // block\n";
1541cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1542cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1543cp.code() += "} // block\n";
1544} // block
1545{ // block
1546cp.code() += "etiss_coverage_count(1, 5812);\n";
1547cp.code() += "{ // block\n";
1548cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
1549cp.code() += "etiss_coverage_count(5, 5800, 5799, 5797, 5796, 5798);\n";
1550cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n";
1551cp.code() += "etiss_coverage_count(5, 5811, 5803, 5802, 5810, 5809);\n";
1552cp.code() += "} // block\n";
1553} // block
1554cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1555cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1556// -----------------------------------------------------------------------------
1557 cp.getAffectedRegisters().add("instructionPointer", 32);
1558 }
1559
1560 return true;
1561 },
1562 0,
1563 [] (BitArray & ba, Instruction & instr)
1564 {
1565// -----------------------------------------------------------------------------
1566etiss_uint8 rd = 0;
1567static BitArrayRange R_rd_0(11, 7);
1568rd += R_rd_0.read(ba) << 0;
1569etiss_uint8 rm = 0;
1570static BitArrayRange R_rm_0(14, 12);
1571rm += R_rm_0.read(ba) << 0;
1572etiss_uint8 rs1 = 0;
1573static BitArrayRange R_rs1_0(19, 15);
1574rs1 += R_rs1_0.read(ba) << 0;
1575
1576// -----------------------------------------------------------------------------
1577
1578 std::stringstream ss;
1579// -----------------------------------------------------------------------------
1580ss << "fcvt_s_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1581// -----------------------------------------------------------------------------
1582 return ss.str();
1583 }
1584);
1585
1586// FCVT_D_S --------------------------------------------------------------------
1587static InstructionDefinition fcvt_d_s_rd_rm_rs1 (
1588 ISA32_RV64IMACFD,
1589 "fcvt_d_s",
1590 (uint32_t) 0x42000053,
1591 (uint32_t) 0xfff0007f,
1592 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1593 {
1594
1595// -----------------------------------------------------------------------------
1596
1597// -----------------------------------------------------------------------------
1598
1599// -----------------------------------------------------------------------------
1600// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1601etiss_uint8 rd = 0;
1602static BitArrayRange R_rd_0(11, 7);
1603rd += R_rd_0.read(ba) << 0;
1604etiss_uint8 rm = 0;
1605static BitArrayRange R_rm_0(14, 12);
1606rm += R_rm_0.read(ba) << 0;
1607etiss_uint8 rs1 = 0;
1608static BitArrayRange R_rs1_0(19, 15);
1609rs1 += R_rs1_0.read(ba) << 0;
1610
1611// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1612// -----------------------------------------------------------------------------
1613
1614 {
1615 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1616
1617 cp.code() = std::string("//FCVT_D_S\n");
1618
1619// -----------------------------------------------------------------------------
1620cp.code() += "etiss_coverage_count(1, 135);\n";
1621{ // block
1622cp.code() += "etiss_coverage_count(1, 1169);\n";
1623cp.code() += "{ // block\n";
1624cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1625cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1626cp.code() += "} // block\n";
1627} // block
1628{ // block
1629cp.code() += "etiss_coverage_count(1, 5843);\n";
1630cp.code() += "{ // block\n";
1631cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
1632cp.code() += "etiss_coverage_count(6, 5820, 5819, 5817, 5816, 5815, 5818);\n";
1633{ // block
1634cp.code() += "etiss_coverage_count(1, 5830);\n";
1635cp.code() += "{ // block\n";
1636cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1637cp.code() += "etiss_coverage_count(4, 5829, 5827, 5826, 5828);\n";
1638cp.code() += "} // block\n";
1639} // block
1640cp.code() += "} // block\n";
1641} // block
1642cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1643cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1644// -----------------------------------------------------------------------------
1645 cp.getAffectedRegisters().add("instructionPointer", 32);
1646 }
1647
1648 return true;
1649 },
1650 0,
1651 [] (BitArray & ba, Instruction & instr)
1652 {
1653// -----------------------------------------------------------------------------
1654etiss_uint8 rd = 0;
1655static BitArrayRange R_rd_0(11, 7);
1656rd += R_rd_0.read(ba) << 0;
1657etiss_uint8 rm = 0;
1658static BitArrayRange R_rm_0(14, 12);
1659rm += R_rm_0.read(ba) << 0;
1660etiss_uint8 rs1 = 0;
1661static BitArrayRange R_rs1_0(19, 15);
1662rs1 += R_rs1_0.read(ba) << 0;
1663
1664// -----------------------------------------------------------------------------
1665
1666 std::stringstream ss;
1667// -----------------------------------------------------------------------------
1668ss << "fcvt_d_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1669// -----------------------------------------------------------------------------
1670 return ss.str();
1671 }
1672);
1673
1674// FEQ_D -----------------------------------------------------------------------
1675static InstructionDefinition feq_d_rd_rs1_rs2 (
1676 ISA32_RV64IMACFD,
1677 "feq_d",
1678 (uint32_t) 0xa2002053,
1679 (uint32_t) 0xfe00707f,
1680 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1681 {
1682
1683// -----------------------------------------------------------------------------
1684
1685// -----------------------------------------------------------------------------
1686
1687// -----------------------------------------------------------------------------
1688// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1689etiss_uint8 rd = 0;
1690static BitArrayRange R_rd_0(11, 7);
1691rd += R_rd_0.read(ba) << 0;
1692etiss_uint8 rs1 = 0;
1693static BitArrayRange R_rs1_0(19, 15);
1694rs1 += R_rs1_0.read(ba) << 0;
1695etiss_uint8 rs2 = 0;
1696static BitArrayRange R_rs2_0(24, 20);
1697rs2 += R_rs2_0.read(ba) << 0;
1698
1699// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1700// -----------------------------------------------------------------------------
1701
1702 {
1703 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1704
1705 cp.code() = std::string("//FEQ_D\n");
1706
1707// -----------------------------------------------------------------------------
1708cp.code() += "etiss_coverage_count(1, 136);\n";
1709{ // block
1710cp.code() += "etiss_coverage_count(1, 1169);\n";
1711cp.code() += "{ // block\n";
1712cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1713cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1714cp.code() += "} // block\n";
1715} // block
1716{ // block
1717cp.code() += "etiss_coverage_count(1, 5909);\n";
1718cp.code() += "{ // block\n";
1719cp.code() += "etiss_uint64 res = 0LL;\n";
1720cp.code() += "etiss_coverage_count(2, 5846, 5845);\n";
1721cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0LL);\n";
1722cp.code() += "etiss_coverage_count(8, 5860, 5851, 5859, 5854, 5853, 5857, 5856, 5858);\n";
1723cp.code() += "etiss_coverage_count(1, 5880);\n";
1724if ((rd % 32ULL) != 0LL) { // conditional
1725cp.code() += "etiss_coverage_count(5, 5886, 5883, 5881, 5884, 5885);\n";
1726cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1727cp.code() += "etiss_coverage_count(5, 5893, 5891, 5890, 5888, 5892);\n";
1728} // conditional
1729cp.code() += "etiss_uint32 flags = fget_flags();\n";
1730cp.code() += "etiss_coverage_count(2, 5896, 5895);\n";
1731cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1732cp.code() += "etiss_coverage_count(9, 5908, 5897, 5907, 5901, 5898, 5902, 5905, 5903, 5906);\n";
1733cp.code() += "} // block\n";
1734} // block
1735cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1736cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1737// -----------------------------------------------------------------------------
1738 cp.getAffectedRegisters().add("instructionPointer", 32);
1739 }
1740
1741 return true;
1742 },
1743 0,
1744 [] (BitArray & ba, Instruction & instr)
1745 {
1746// -----------------------------------------------------------------------------
1747etiss_uint8 rd = 0;
1748static BitArrayRange R_rd_0(11, 7);
1749rd += R_rd_0.read(ba) << 0;
1750etiss_uint8 rs1 = 0;
1751static BitArrayRange R_rs1_0(19, 15);
1752rs1 += R_rs1_0.read(ba) << 0;
1753etiss_uint8 rs2 = 0;
1754static BitArrayRange R_rs2_0(24, 20);
1755rs2 += R_rs2_0.read(ba) << 0;
1756
1757// -----------------------------------------------------------------------------
1758
1759 std::stringstream ss;
1760// -----------------------------------------------------------------------------
1761ss << "feq_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1762// -----------------------------------------------------------------------------
1763 return ss.str();
1764 }
1765);
1766
1767// FLT_D -----------------------------------------------------------------------
1768static InstructionDefinition flt_d_rd_rs1_rs2 (
1769 ISA32_RV64IMACFD,
1770 "flt_d",
1771 (uint32_t) 0xa2001053,
1772 (uint32_t) 0xfe00707f,
1773 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1774 {
1775
1776// -----------------------------------------------------------------------------
1777
1778// -----------------------------------------------------------------------------
1779
1780// -----------------------------------------------------------------------------
1781// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1782etiss_uint8 rd = 0;
1783static BitArrayRange R_rd_0(11, 7);
1784rd += R_rd_0.read(ba) << 0;
1785etiss_uint8 rs1 = 0;
1786static BitArrayRange R_rs1_0(19, 15);
1787rs1 += R_rs1_0.read(ba) << 0;
1788etiss_uint8 rs2 = 0;
1789static BitArrayRange R_rs2_0(24, 20);
1790rs2 += R_rs2_0.read(ba) << 0;
1791
1792// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1793// -----------------------------------------------------------------------------
1794
1795 {
1796 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1797
1798 cp.code() = std::string("//FLT_D\n");
1799
1800// -----------------------------------------------------------------------------
1801cp.code() += "etiss_coverage_count(1, 137);\n";
1802{ // block
1803cp.code() += "etiss_coverage_count(1, 1169);\n";
1804cp.code() += "{ // block\n";
1805cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1806cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1807cp.code() += "} // block\n";
1808} // block
1809{ // block
1810cp.code() += "etiss_coverage_count(1, 5975);\n";
1811cp.code() += "{ // block\n";
1812cp.code() += "etiss_uint64 res = 0LL;\n";
1813cp.code() += "etiss_coverage_count(2, 5912, 5911);\n";
1814cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n";
1815cp.code() += "etiss_coverage_count(8, 5926, 5917, 5925, 5920, 5919, 5923, 5922, 5924);\n";
1816cp.code() += "etiss_coverage_count(1, 5946);\n";
1817if ((rd % 32ULL) != 0LL) { // conditional
1818cp.code() += "etiss_coverage_count(5, 5952, 5949, 5947, 5950, 5951);\n";
1819cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1820cp.code() += "etiss_coverage_count(5, 5959, 5957, 5956, 5954, 5958);\n";
1821} // conditional
1822cp.code() += "etiss_uint32 flags = fget_flags();\n";
1823cp.code() += "etiss_coverage_count(2, 5962, 5961);\n";
1824cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1825cp.code() += "etiss_coverage_count(9, 5974, 5963, 5973, 5967, 5964, 5968, 5971, 5969, 5972);\n";
1826cp.code() += "} // block\n";
1827} // block
1828cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1829cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1830// -----------------------------------------------------------------------------
1831 cp.getAffectedRegisters().add("instructionPointer", 32);
1832 }
1833
1834 return true;
1835 },
1836 0,
1837 [] (BitArray & ba, Instruction & instr)
1838 {
1839// -----------------------------------------------------------------------------
1840etiss_uint8 rd = 0;
1841static BitArrayRange R_rd_0(11, 7);
1842rd += R_rd_0.read(ba) << 0;
1843etiss_uint8 rs1 = 0;
1844static BitArrayRange R_rs1_0(19, 15);
1845rs1 += R_rs1_0.read(ba) << 0;
1846etiss_uint8 rs2 = 0;
1847static BitArrayRange R_rs2_0(24, 20);
1848rs2 += R_rs2_0.read(ba) << 0;
1849
1850// -----------------------------------------------------------------------------
1851
1852 std::stringstream ss;
1853// -----------------------------------------------------------------------------
1854ss << "flt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1855// -----------------------------------------------------------------------------
1856 return ss.str();
1857 }
1858);
1859
1860// FLE_D -----------------------------------------------------------------------
1861static InstructionDefinition fle_d_rd_rs1_rs2 (
1862 ISA32_RV64IMACFD,
1863 "fle_d",
1864 (uint32_t) 0xa2000053,
1865 (uint32_t) 0xfe00707f,
1866 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1867 {
1868
1869// -----------------------------------------------------------------------------
1870
1871// -----------------------------------------------------------------------------
1872
1873// -----------------------------------------------------------------------------
1874// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1875etiss_uint8 rd = 0;
1876static BitArrayRange R_rd_0(11, 7);
1877rd += R_rd_0.read(ba) << 0;
1878etiss_uint8 rs1 = 0;
1879static BitArrayRange R_rs1_0(19, 15);
1880rs1 += R_rs1_0.read(ba) << 0;
1881etiss_uint8 rs2 = 0;
1882static BitArrayRange R_rs2_0(24, 20);
1883rs2 += R_rs2_0.read(ba) << 0;
1884
1885// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1886// -----------------------------------------------------------------------------
1887
1888 {
1889 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1890
1891 cp.code() = std::string("//FLE_D\n");
1892
1893// -----------------------------------------------------------------------------
1894cp.code() += "etiss_coverage_count(1, 138);\n";
1895{ // block
1896cp.code() += "etiss_coverage_count(1, 1169);\n";
1897cp.code() += "{ // block\n";
1898cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1899cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1900cp.code() += "} // block\n";
1901} // block
1902{ // block
1903cp.code() += "etiss_coverage_count(1, 6041);\n";
1904cp.code() += "{ // block\n";
1905cp.code() += "etiss_uint64 res = 0LL;\n";
1906cp.code() += "etiss_coverage_count(2, 5978, 5977);\n";
1907cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n";
1908cp.code() += "etiss_coverage_count(8, 5992, 5983, 5991, 5986, 5985, 5989, 5988, 5990);\n";
1909cp.code() += "etiss_coverage_count(1, 6012);\n";
1910if ((rd % 32ULL) != 0LL) { // conditional
1911cp.code() += "etiss_coverage_count(5, 6018, 6015, 6013, 6016, 6017);\n";
1912cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1913cp.code() += "etiss_coverage_count(5, 6025, 6023, 6022, 6020, 6024);\n";
1914} // conditional
1915cp.code() += "etiss_uint32 flags = fget_flags();\n";
1916cp.code() += "etiss_coverage_count(2, 6028, 6027);\n";
1917cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1918cp.code() += "etiss_coverage_count(9, 6040, 6029, 6039, 6033, 6030, 6034, 6037, 6035, 6038);\n";
1919cp.code() += "} // block\n";
1920} // block
1921cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1922cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1923// -----------------------------------------------------------------------------
1924 cp.getAffectedRegisters().add("instructionPointer", 32);
1925 }
1926
1927 return true;
1928 },
1929 0,
1930 [] (BitArray & ba, Instruction & instr)
1931 {
1932// -----------------------------------------------------------------------------
1933etiss_uint8 rd = 0;
1934static BitArrayRange R_rd_0(11, 7);
1935rd += R_rd_0.read(ba) << 0;
1936etiss_uint8 rs1 = 0;
1937static BitArrayRange R_rs1_0(19, 15);
1938rs1 += R_rs1_0.read(ba) << 0;
1939etiss_uint8 rs2 = 0;
1940static BitArrayRange R_rs2_0(24, 20);
1941rs2 += R_rs2_0.read(ba) << 0;
1942
1943// -----------------------------------------------------------------------------
1944
1945 std::stringstream ss;
1946// -----------------------------------------------------------------------------
1947ss << "fle_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1948// -----------------------------------------------------------------------------
1949 return ss.str();
1950 }
1951);
1952
1953// FCLASS_D --------------------------------------------------------------------
1954static InstructionDefinition fclass_d_rd_rs1 (
1955 ISA32_RV64IMACFD,
1956 "fclass_d",
1957 (uint32_t) 0xe2001053,
1958 (uint32_t) 0xfff0707f,
1959 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1960 {
1961
1962// -----------------------------------------------------------------------------
1963
1964// -----------------------------------------------------------------------------
1965
1966// -----------------------------------------------------------------------------
1967// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1968etiss_uint8 rd = 0;
1969static BitArrayRange R_rd_0(11, 7);
1970rd += R_rd_0.read(ba) << 0;
1971etiss_uint8 rs1 = 0;
1972static BitArrayRange R_rs1_0(19, 15);
1973rs1 += R_rs1_0.read(ba) << 0;
1974
1975// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1976// -----------------------------------------------------------------------------
1977
1978 {
1979 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1980
1981 cp.code() = std::string("//FCLASS_D\n");
1982
1983// -----------------------------------------------------------------------------
1984cp.code() += "etiss_coverage_count(1, 139);\n";
1985{ // block
1986cp.code() += "etiss_coverage_count(1, 1169);\n";
1987cp.code() += "{ // block\n";
1988cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1989cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1990cp.code() += "} // block\n";
1991} // block
1992{ // block
1993cp.code() += "etiss_coverage_count(1, 6054);\n";
1994cp.code() += "{ // block\n";
1995cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
1996cp.code() += "etiss_coverage_count(8, 6053, 6046, 6045, 6043, 6052, 6051, 6049, 6048);\n";
1997cp.code() += "} // block\n";
1998} // block
1999cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2000cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2001// -----------------------------------------------------------------------------
2002 cp.getAffectedRegisters().add("instructionPointer", 32);
2003 }
2004
2005 return true;
2006 },
2007 0,
2008 [] (BitArray & ba, Instruction & instr)
2009 {
2010// -----------------------------------------------------------------------------
2011etiss_uint8 rd = 0;
2012static BitArrayRange R_rd_0(11, 7);
2013rd += R_rd_0.read(ba) << 0;
2014etiss_uint8 rs1 = 0;
2015static BitArrayRange R_rs1_0(19, 15);
2016rs1 += R_rs1_0.read(ba) << 0;
2017
2018// -----------------------------------------------------------------------------
2019
2020 std::stringstream ss;
2021// -----------------------------------------------------------------------------
2022ss << "fclass_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2023// -----------------------------------------------------------------------------
2024 return ss.str();
2025 }
2026);
2027
2028// FCVT_W_D --------------------------------------------------------------------
2029static InstructionDefinition fcvt_w_d_rd_rm_rs1 (
2030 ISA32_RV64IMACFD,
2031 "fcvt_w_d",
2032 (uint32_t) 0xc2000053,
2033 (uint32_t) 0xfff0007f,
2034 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2035 {
2036
2037// -----------------------------------------------------------------------------
2038
2039// -----------------------------------------------------------------------------
2040
2041// -----------------------------------------------------------------------------
2042// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2043etiss_uint8 rd = 0;
2044static BitArrayRange R_rd_0(11, 7);
2045rd += R_rd_0.read(ba) << 0;
2046etiss_uint8 rm = 0;
2047static BitArrayRange R_rm_0(14, 12);
2048rm += R_rm_0.read(ba) << 0;
2049etiss_uint8 rs1 = 0;
2050static BitArrayRange R_rs1_0(19, 15);
2051rs1 += R_rs1_0.read(ba) << 0;
2052
2053// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2054// -----------------------------------------------------------------------------
2055
2056 {
2057 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2058
2059 cp.code() = std::string("//FCVT_W_D\n");
2060
2061// -----------------------------------------------------------------------------
2062cp.code() += "etiss_coverage_count(1, 140);\n";
2063{ // block
2064cp.code() += "etiss_coverage_count(1, 1169);\n";
2065cp.code() += "{ // block\n";
2066cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2067cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2068cp.code() += "} // block\n";
2069} // block
2070{ // block
2071cp.code() += "etiss_coverage_count(1, 6112);\n";
2072cp.code() += "{ // block\n";
2073cp.code() += "etiss_int32 res = 0LL;\n";
2074cp.code() += "etiss_coverage_count(2, 6057, 6056);\n";
2075cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0LL, " + std::to_string(rm) + "ULL);\n";
2076cp.code() += "etiss_coverage_count(7, 6069, 6062, 6068, 6065, 6064, 6066, 6067);\n";
2077cp.code() += "etiss_coverage_count(1, 6083);\n";
2078if ((rd % 32ULL) != 0LL) { // conditional
2079cp.code() += "etiss_coverage_count(5, 6089, 6086, 6084, 6087, 6088);\n";
2080cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2081cp.code() += "etiss_coverage_count(5, 6096, 6094, 6093, 6091, 6095);\n";
2082} // conditional
2083cp.code() += "etiss_uint32 flags = fget_flags();\n";
2084cp.code() += "etiss_coverage_count(2, 6099, 6098);\n";
2085cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2086cp.code() += "etiss_coverage_count(9, 6111, 6100, 6110, 6104, 6101, 6105, 6108, 6106, 6109);\n";
2087cp.code() += "} // block\n";
2088} // block
2089cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2090cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2091// -----------------------------------------------------------------------------
2092 cp.getAffectedRegisters().add("instructionPointer", 32);
2093 }
2094
2095 return true;
2096 },
2097 0,
2098 [] (BitArray & ba, Instruction & instr)
2099 {
2100// -----------------------------------------------------------------------------
2101etiss_uint8 rd = 0;
2102static BitArrayRange R_rd_0(11, 7);
2103rd += R_rd_0.read(ba) << 0;
2104etiss_uint8 rm = 0;
2105static BitArrayRange R_rm_0(14, 12);
2106rm += R_rm_0.read(ba) << 0;
2107etiss_uint8 rs1 = 0;
2108static BitArrayRange R_rs1_0(19, 15);
2109rs1 += R_rs1_0.read(ba) << 0;
2110
2111// -----------------------------------------------------------------------------
2112
2113 std::stringstream ss;
2114// -----------------------------------------------------------------------------
2115ss << "fcvt_w_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2116// -----------------------------------------------------------------------------
2117 return ss.str();
2118 }
2119);
2120
2121// FCVT_WU_D -------------------------------------------------------------------
2122static InstructionDefinition fcvt_wu_d_rd_rm_rs1 (
2123 ISA32_RV64IMACFD,
2124 "fcvt_wu_d",
2125 (uint32_t) 0xc2100053,
2126 (uint32_t) 0xfff0007f,
2127 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2128 {
2129
2130// -----------------------------------------------------------------------------
2131
2132// -----------------------------------------------------------------------------
2133
2134// -----------------------------------------------------------------------------
2135// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2136etiss_uint8 rd = 0;
2137static BitArrayRange R_rd_0(11, 7);
2138rd += R_rd_0.read(ba) << 0;
2139etiss_uint8 rm = 0;
2140static BitArrayRange R_rm_0(14, 12);
2141rm += R_rm_0.read(ba) << 0;
2142etiss_uint8 rs1 = 0;
2143static BitArrayRange R_rs1_0(19, 15);
2144rs1 += R_rs1_0.read(ba) << 0;
2145
2146// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2147// -----------------------------------------------------------------------------
2148
2149 {
2150 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2151
2152 cp.code() = std::string("//FCVT_WU_D\n");
2153
2154// -----------------------------------------------------------------------------
2155cp.code() += "etiss_coverage_count(1, 141);\n";
2156{ // block
2157cp.code() += "etiss_coverage_count(1, 1169);\n";
2158cp.code() += "{ // block\n";
2159cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2160cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2161cp.code() += "} // block\n";
2162} // block
2163{ // block
2164cp.code() += "etiss_coverage_count(1, 6173);\n";
2165cp.code() += "{ // block\n";
2166cp.code() += "etiss_uint32 res = 0LL;\n";
2167cp.code() += "etiss_coverage_count(2, 6115, 6114);\n";
2168cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n";
2169cp.code() += "etiss_coverage_count(7, 6127, 6120, 6126, 6123, 6122, 6124, 6125);\n";
2170cp.code() += "etiss_coverage_count(1, 6141);\n";
2171if ((rd % 32ULL) != 0LL) { // conditional
2172cp.code() += "etiss_coverage_count(5, 6147, 6144, 6142, 6145, 6146);\n";
2173cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
2174cp.code() += "etiss_coverage_count(7, 6157, 6152, 6151, 6149, 6156, 6154, 6153);\n";
2175} // conditional
2176cp.code() += "etiss_uint32 flags = fget_flags();\n";
2177cp.code() += "etiss_coverage_count(2, 6160, 6159);\n";
2178cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2179cp.code() += "etiss_coverage_count(9, 6172, 6161, 6171, 6165, 6162, 6166, 6169, 6167, 6170);\n";
2180cp.code() += "} // block\n";
2181} // block
2182cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2183cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2184// -----------------------------------------------------------------------------
2185 cp.getAffectedRegisters().add("instructionPointer", 32);
2186 }
2187
2188 return true;
2189 },
2190 0,
2191 [] (BitArray & ba, Instruction & instr)
2192 {
2193// -----------------------------------------------------------------------------
2194etiss_uint8 rd = 0;
2195static BitArrayRange R_rd_0(11, 7);
2196rd += R_rd_0.read(ba) << 0;
2197etiss_uint8 rm = 0;
2198static BitArrayRange R_rm_0(14, 12);
2199rm += R_rm_0.read(ba) << 0;
2200etiss_uint8 rs1 = 0;
2201static BitArrayRange R_rs1_0(19, 15);
2202rs1 += R_rs1_0.read(ba) << 0;
2203
2204// -----------------------------------------------------------------------------
2205
2206 std::stringstream ss;
2207// -----------------------------------------------------------------------------
2208ss << "fcvt_wu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2209// -----------------------------------------------------------------------------
2210 return ss.str();
2211 }
2212);
2213
2214// FCVT_D_W --------------------------------------------------------------------
2215static InstructionDefinition fcvt_d_w_rd_rm_rs1 (
2216 ISA32_RV64IMACFD,
2217 "fcvt_d_w",
2218 (uint32_t) 0xd2000053,
2219 (uint32_t) 0xfff0007f,
2220 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2221 {
2222
2223// -----------------------------------------------------------------------------
2224
2225// -----------------------------------------------------------------------------
2226
2227// -----------------------------------------------------------------------------
2228// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2229etiss_uint8 rd = 0;
2230static BitArrayRange R_rd_0(11, 7);
2231rd += R_rd_0.read(ba) << 0;
2232etiss_uint8 rm = 0;
2233static BitArrayRange R_rm_0(14, 12);
2234rm += R_rm_0.read(ba) << 0;
2235etiss_uint8 rs1 = 0;
2236static BitArrayRange R_rs1_0(19, 15);
2237rs1 += R_rs1_0.read(ba) << 0;
2238
2239// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2240// -----------------------------------------------------------------------------
2241
2242 {
2243 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2244
2245 cp.code() = std::string("//FCVT_D_W\n");
2246
2247// -----------------------------------------------------------------------------
2248cp.code() += "etiss_coverage_count(1, 142);\n";
2249{ // block
2250cp.code() += "etiss_coverage_count(1, 1169);\n";
2251cp.code() += "{ // block\n";
2252cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2253cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2254cp.code() += "} // block\n";
2255} // block
2256{ // block
2257cp.code() += "etiss_coverage_count(1, 6206);\n";
2258cp.code() += "{ // block\n";
2259cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
2260cp.code() += "etiss_coverage_count(8, 6184, 6183, 6180, 6179, 6178, 6176, 6181, 6182);\n";
2261cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2262cp.code() += "etiss_coverage_count(4, 6193, 6191, 6190, 6192);\n";
2263cp.code() += "} // block\n";
2264} // block
2265cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2266cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2267// -----------------------------------------------------------------------------
2268 cp.getAffectedRegisters().add("instructionPointer", 32);
2269 }
2270
2271 return true;
2272 },
2273 0,
2274 [] (BitArray & ba, Instruction & instr)
2275 {
2276// -----------------------------------------------------------------------------
2277etiss_uint8 rd = 0;
2278static BitArrayRange R_rd_0(11, 7);
2279rd += R_rd_0.read(ba) << 0;
2280etiss_uint8 rm = 0;
2281static BitArrayRange R_rm_0(14, 12);
2282rm += R_rm_0.read(ba) << 0;
2283etiss_uint8 rs1 = 0;
2284static BitArrayRange R_rs1_0(19, 15);
2285rs1 += R_rs1_0.read(ba) << 0;
2286
2287// -----------------------------------------------------------------------------
2288
2289 std::stringstream ss;
2290// -----------------------------------------------------------------------------
2291ss << "fcvt_d_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2292// -----------------------------------------------------------------------------
2293 return ss.str();
2294 }
2295);
2296
2297// FCVT_D_WU -------------------------------------------------------------------
2298static InstructionDefinition fcvt_d_wu_rd_rm_rs1 (
2299 ISA32_RV64IMACFD,
2300 "fcvt_d_wu",
2301 (uint32_t) 0xd2100053,
2302 (uint32_t) 0xfff0007f,
2303 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2304 {
2305
2306// -----------------------------------------------------------------------------
2307
2308// -----------------------------------------------------------------------------
2309
2310// -----------------------------------------------------------------------------
2311// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2312etiss_uint8 rd = 0;
2313static BitArrayRange R_rd_0(11, 7);
2314rd += R_rd_0.read(ba) << 0;
2315etiss_uint8 rm = 0;
2316static BitArrayRange R_rm_0(14, 12);
2317rm += R_rm_0.read(ba) << 0;
2318etiss_uint8 rs1 = 0;
2319static BitArrayRange R_rs1_0(19, 15);
2320rs1 += R_rs1_0.read(ba) << 0;
2321
2322// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2323// -----------------------------------------------------------------------------
2324
2325 {
2326 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2327
2328 cp.code() = std::string("//FCVT_D_WU\n");
2329
2330// -----------------------------------------------------------------------------
2331cp.code() += "etiss_coverage_count(1, 143);\n";
2332{ // block
2333cp.code() += "etiss_coverage_count(1, 1169);\n";
2334cp.code() += "{ // block\n";
2335cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2336cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2337cp.code() += "} // block\n";
2338} // block
2339{ // block
2340cp.code() += "etiss_coverage_count(1, 6239);\n";
2341cp.code() += "{ // block\n";
2342cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2343cp.code() += "etiss_coverage_count(8, 6217, 6216, 6213, 6212, 6211, 6209, 6214, 6215);\n";
2344cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2345cp.code() += "etiss_coverage_count(4, 6226, 6224, 6223, 6225);\n";
2346cp.code() += "} // block\n";
2347} // block
2348cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2349cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2350// -----------------------------------------------------------------------------
2351 cp.getAffectedRegisters().add("instructionPointer", 32);
2352 }
2353
2354 return true;
2355 },
2356 0,
2357 [] (BitArray & ba, Instruction & instr)
2358 {
2359// -----------------------------------------------------------------------------
2360etiss_uint8 rd = 0;
2361static BitArrayRange R_rd_0(11, 7);
2362rd += R_rd_0.read(ba) << 0;
2363etiss_uint8 rm = 0;
2364static BitArrayRange R_rm_0(14, 12);
2365rm += R_rm_0.read(ba) << 0;
2366etiss_uint8 rs1 = 0;
2367static BitArrayRange R_rs1_0(19, 15);
2368rs1 += R_rs1_0.read(ba) << 0;
2369
2370// -----------------------------------------------------------------------------
2371
2372 std::stringstream ss;
2373// -----------------------------------------------------------------------------
2374ss << "fcvt_d_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2375// -----------------------------------------------------------------------------
2376 return ss.str();
2377 }
2378);
2379// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fmin_d_rd_rs1_rs2
static InstructionDefinition fmin_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fmin_d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_D\n");cp.code()+="etiss_coverage_count(1, 132);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5742);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 0LL);\n";cp.code()+="etiss_coverage_count(9, 5705, 5704, 5697, 5695, 5694, 5702, 5700, 5699, 5703);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5714, 5712, 5711, 5713);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5729, 5728);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5741, 5730, 5740, 5734, 5731, 5735, 5738, 5736, 5739);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fle_d_rd_rs1_rs2
static InstructionDefinition fle_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fle_d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_D\n");cp.code()+="etiss_coverage_count(1, 138);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6041);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5978, 5977);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 1ULL);\n";cp.code()+="etiss_coverage_count(8, 5992, 5983, 5991, 5986, 5985, 5989, 5988, 5990);\n";cp.code()+="etiss_coverage_count(1, 6012);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6018, 6015, 6013, 6016, 6017);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6025, 6023, 6022, 6020, 6024);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6028, 6027);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6040, 6029, 6039, 6033, 6030, 6034, 6037, 6035, 6038);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_w_d_rd_rm_rs1
static InstructionDefinition fcvt_w_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_w_d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_D\n");cp.code()+="etiss_coverage_count(1, 140);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6112);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6057, 6056);\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6069, 6062, 6068, 6065, 6064, 6066, 6067);\n";cp.code()+="etiss_coverage_count(1, 6083);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6089, 6086, 6084, 6087, 6088);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6096, 6094, 6093, 6091, 6095);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6099, 6098);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6111, 6100, 6110, 6104, 6101, 6105, 6108, 6106, 6109);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_d_rd_rm_rs1
static InstructionDefinition fcvt_s_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_D\n");cp.code()+="etiss_coverage_count(1, 134);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5812);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(5, 5800, 5799, 5797, 5796, 5798);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL + res;\n";cp.code()+="etiss_coverage_count(5, 5811, 5803, 5802, 5810, 5809);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fdiv_d_rd_rm_rs1_rs2
static InstructionDefinition fdiv_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fdiv_d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_D\n");cp.code()+="etiss_coverage_count(1, 127);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5528);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5491, 5490, 5482, 5480, 5479, 5487, 5485, 5484, 5489, 5488);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5500, 5498, 5497, 5499);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5515, 5514);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5527, 5516, 5526, 5520, 5517, 5521, 5524, 5522, 5525);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_d_w_rd_rm_rs1
static InstructionDefinition fcvt_d_w_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_W\n");cp.code()+="etiss_coverage_count(1, 142);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6206);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6184, 6183, 6180, 6179, 6178, 6176, 6181, 6182);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6193, 6191, 6190, 6192);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmul_d_rd_rm_rs1_rs2
static InstructionDefinition fmul_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fmul_d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_D\n");cp.code()+="etiss_coverage_count(1, 126);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5476);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5439, 5438, 5430, 5428, 5427, 5435, 5433, 5432, 5437, 5436);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5448, 5446, 5445, 5447);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5463, 5462);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5475, 5464, 5474, 5468, 5465, 5469, 5472, 5470, 5473);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsqrt_d_rd_rm_rs1
static InstructionDefinition fsqrt_d_rd_rm_rs1(ISA32_RV64IMACFD, "fsqrt_d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_D\n");cp.code()+="etiss_coverage_count(1, 128);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5575);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(7, 5538, 5537, 5534, 5532, 5531, 5536, 5535);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5547, 5545, 5544, 5546);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5562, 5561);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5574, 5563, 5573, 5567, 5564, 5568, 5571, 5569, 5572);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsub_d_rd_rm_rs1_rs2
static InstructionDefinition fsub_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fsub_d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_D\n");cp.code()+="etiss_coverage_count(1, 125);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5424);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5387, 5386, 5378, 5376, 5375, 5383, 5381, 5380, 5385, 5384);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5396, 5394, 5393, 5395);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5411, 5410);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5423, 5412, 5422, 5416, 5413, 5417, 5420, 5418, 5421);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjn_d_rd_rs1_rs2
static InstructionDefinition fsgnjn_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnjn_d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_D\n");cp.code()+="etiss_coverage_count(1, 130);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5650);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 0x1ULL))) << 63) | (((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) & 0x7fffffffffffffffULL)));\n";cp.code()+="etiss_coverage_count(13, 5628, 5627, 5620, 5619, 5616, 5615, 5617, 5618, 5626, 5623, 5622, 5624, 5625);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5637, 5635, 5634, 5636);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_wu_d_rd_rm_rs1
static InstructionDefinition fcvt_wu_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_wu_d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_D\n");cp.code()+="etiss_coverage_count(1, 141);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6173);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6115, 6114);\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6127, 6120, 6126, 6123, 6122, 6124, 6125);\n";cp.code()+="etiss_coverage_count(1, 6141);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6147, 6144, 6142, 6145, 6146);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(7, 6157, 6152, 6151, 6149, 6156, 6154, 6153);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6160, 6159);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6172, 6161, 6171, 6165, 6162, 6166, 6169, 6167, 6170);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsd_imm_rs1_rs2
static InstructionDefinition fsd_imm_rs1_rs2(ISA32_RV64IMACFD, "fsd",(uint32_t) 0x003027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="etiss_coverage_count(1, 119);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5088);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5078, 5077, 5073, 5072, 5070, 5076, 5074);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5087, 5081, 5080, 5086, 5084, 5083);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fmadd_d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_D\n");cp.code()+="etiss_coverage_count(1, 120);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5146);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5109, 5108, 5094, 5092, 5091, 5099, 5097, 5096, 5104, 5102, 5101, 5105, 5107, 5106);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5118, 5116, 5115, 5117);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5133, 5132);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5145, 5134, 5144, 5138, 5135, 5139, 5142, 5140, 5143);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fadd_d_rd_rm_rs1_rs2
static InstructionDefinition fadd_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fadd_d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_D\n");cp.code()+="etiss_coverage_count(1, 124);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5335, 5334, 5326, 5324, 5323, 5331, 5329, 5328, 5333, 5332);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5344, 5342, 5341, 5343);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5359, 5358);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5371, 5360, 5370, 5364, 5361, 5365, 5368, 5366, 5369);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
flt_d_rd_rs1_rs2
static InstructionDefinition flt_d_rd_rs1_rs2(ISA32_RV64IMACFD, "flt_d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_D\n");cp.code()+="etiss_coverage_count(1, 137);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5975);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5912, 5911);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 2ULL);\n";cp.code()+="etiss_coverage_count(8, 5926, 5917, 5925, 5920, 5919, 5923, 5922, 5924);\n";cp.code()+="etiss_coverage_count(1, 5946);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5952, 5949, 5947, 5950, 5951);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5959, 5957, 5956, 5954, 5958);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5962, 5961);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5974, 5963, 5973, 5967, 5964, 5968, 5971, 5969, 5972);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fmsub_d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_D\n");cp.code()+="etiss_coverage_count(1, 121);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5204);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5167, 5166, 5152, 5150, 5149, 5157, 5155, 5154, 5162, 5160, 5159, 5163, 5165, 5164);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5176, 5174, 5173, 5175);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5191, 5190);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5203, 5192, 5202, 5196, 5193, 5197, 5200, 5198, 5201);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fnmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fnmadd_d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_D\n");cp.code()+="etiss_coverage_count(1, 122);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5262);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5225, 5224, 5210, 5208, 5207, 5215, 5213, 5212, 5220, 5218, 5217, 5221, 5223, 5222);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5234, 5232, 5231, 5233);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5249, 5248);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5261, 5250, 5260, 5254, 5251, 5255, 5258, 5256, 5259);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
feq_d_rd_rs1_rs2
static InstructionDefinition feq_d_rd_rs1_rs2(ISA32_RV64IMACFD, "feq_d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_D\n");cp.code()+="etiss_coverage_count(1, 136);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5909);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5846, 5845);\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 0LL);\n";cp.code()+="etiss_coverage_count(8, 5860, 5851, 5859, 5854, 5853, 5857, 5856, 5858);\n";cp.code()+="etiss_coverage_count(1, 5880);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5886, 5883, 5881, 5884, 5885);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5893, 5891, 5890, 5888, 5892);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5896, 5895);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5908, 5897, 5907, 5901, 5898, 5902, 5905, 5903, 5906);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjx_d_rd_rs1_rs2
static InstructionDefinition fsgnjx_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnjx_d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_D\n");cp.code()+="etiss_coverage_count(1, 131);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5691);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) & 9223372036854775808ULL);\n";cp.code()+="etiss_coverage_count(10, 5669, 5668, 5656, 5654, 5653, 5666, 5661, 5659, 5658, 5667);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5678, 5676, 5675, 5677);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnj_d_rd_rs1_rs2
static InstructionDefinition fsgnj_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnj_d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_D\n");cp.code()+="etiss_coverage_count(1, 129);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5612);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 0x1ULL)) << 63) | (((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) & 0x7fffffffffffffffULL)));\n";cp.code()+="etiss_coverage_count(12, 5590, 5589, 5582, 5579, 5578, 5580, 5581, 5588, 5585, 5584, 5586, 5587);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5599, 5597, 5596, 5598);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fld_rd_rs1_imm
static InstructionDefinition fld_rd_rs1_imm(ISA32_RV64IMACFD, "fld",(uint32_t) 0x003007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="etiss_coverage_count(1, 118);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5067);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5038, 5037, 5033, 5032, 5030, 5036, 5034);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 5045, 5044, 5042, 5041);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5054, 5052, 5051, 5053);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fnmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fnmsub_d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_D\n");cp.code()+="etiss_coverage_count(1, 123);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5283, 5282, 5268, 5266, 5265, 5273, 5271, 5270, 5278, 5276, 5275, 5279, 5281, 5280);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5292, 5290, 5289, 5291);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5307, 5306);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5319, 5308, 5318, 5312, 5309, 5313, 5316, 5314, 5317);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fclass_d_rd_rs1
static InstructionDefinition fclass_d_rd_rs1(ISA32_RV64IMACFD, "fclass_d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_D\n");cp.code()+="etiss_coverage_count(1, 139);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6054);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(8, 6053, 6046, 6045, 6043, 6052, 6051, 6049, 6048);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_wu_rd_rm_rs1
static InstructionDefinition fcvt_d_wu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_WU\n");cp.code()+="etiss_coverage_count(1, 143);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6239);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6217, 6216, 6213, 6212, 6211, 6209, 6214, 6215);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6226, 6224, 6223, 6225);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_s_rd_rm_rs1
static InstructionDefinition fcvt_d_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_S\n");cp.code()+="etiss_coverage_count(1, 135);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5843);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 5820, 5819, 5817, 5816, 5815, 5818);\n";{ cp.code()+="etiss_coverage_count(1, 5830);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5829, 5827, 5826, 5828);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmax_d_rd_rs1_rs2
static InstructionDefinition fmax_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fmax_d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_D\n");cp.code()+="etiss_coverage_count(1, 133);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5793);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 1ULL);\n";cp.code()+="etiss_coverage_count(9, 5756, 5755, 5748, 5746, 5745, 5753, 5751, 5750, 5754);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5765, 5763, 5762, 5764);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5780, 5779);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5792, 5781, 5791, 5785, 5782, 5786, 5789, 5787, 5790);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:51
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_uint16
uint16_t etiss_uint16
Definition types.h:52
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:364
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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