ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32DInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FLD -------------------------------------------------------------------------
16 static InstructionDefinition fld_rd_rs1_imm (
17  ISA32_RV64IMACFD,
18  "fld",
19  (uint32_t) 0x003007,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FLD\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
55 cp.code() += "etiss_uint64 mem_val_0;\n";
56 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
57 cp.code() += "if (cpu->exception) { // conditional\n";
58 { // procedure
59 cp.code() += "{ // procedure\n";
60 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
61 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
62 cp.code() += "} // procedure\n";
63 } // procedure
64 cp.code() += "} // conditional\n";
65 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
66 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
67 cp.code() += "} // block\n";
68 } // block
69 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
70 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
71 // -----------------------------------------------------------------------------
72  cp.getAffectedRegisters().add("instructionPointer", 32);
73  }
74  {
75  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
76 
77  cp.code() = std::string("//FLD\n");
78 
79 // -----------------------------------------------------------------------------
80 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
81 // -----------------------------------------------------------------------------
82  }
83 
84  return true;
85  },
86  0,
87  [] (BitArray & ba, Instruction & instr)
88  {
89 // -----------------------------------------------------------------------------
90 etiss_uint8 rd = 0;
91 static BitArrayRange R_rd_0(11, 7);
92 rd += R_rd_0.read(ba) << 0;
93 etiss_uint8 rs1 = 0;
94 static BitArrayRange R_rs1_0(19, 15);
95 rs1 += R_rs1_0.read(ba) << 0;
96 etiss_uint16 imm = 0;
97 static BitArrayRange R_imm_0(31, 20);
98 imm += R_imm_0.read(ba) << 0;
99 
100 // -----------------------------------------------------------------------------
101 
102  std::stringstream ss;
103 // -----------------------------------------------------------------------------
104 ss << "fld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
105 // -----------------------------------------------------------------------------
106  return ss.str();
107  }
108 );
109 
110 // FSD -------------------------------------------------------------------------
111 static InstructionDefinition fsd_imm_rs1_rs2 (
112  ISA32_RV64IMACFD,
113  "fsd",
114  (uint32_t) 0x003027,
115  (uint32_t) 0x00707f,
116  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
117  {
118 
119 // -----------------------------------------------------------------------------
120 
121 // -----------------------------------------------------------------------------
122 
123 // -----------------------------------------------------------------------------
124 etiss_uint16 imm = 0;
125 static BitArrayRange R_imm_0(11, 7);
126 imm += R_imm_0.read(ba) << 0;
127 etiss_uint8 rs1 = 0;
128 static BitArrayRange R_rs1_0(19, 15);
129 rs1 += R_rs1_0.read(ba) << 0;
130 etiss_uint8 rs2 = 0;
131 static BitArrayRange R_rs2_0(24, 20);
132 rs2 += R_rs2_0.read(ba) << 0;
133 static BitArrayRange R_imm_5(31, 25);
134 imm += R_imm_5.read(ba) << 5;
135 
136 // -----------------------------------------------------------------------------
137 
138  {
139  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
140 
141  cp.code() = std::string("//FSD\n");
142 
143 // -----------------------------------------------------------------------------
144 { // block
145 cp.code() += "{ // block\n";
146 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
147 cp.code() += "} // block\n";
148 } // block
149 { // block
150 cp.code() += "{ // block\n";
151 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
152 cp.code() += "etiss_uint64 mem_val_0;\n";
153 cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
154 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
155 cp.code() += "if (cpu->exception) { // conditional\n";
156 { // procedure
157 cp.code() += "{ // procedure\n";
158 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
159 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
160 cp.code() += "} // procedure\n";
161 } // procedure
162 cp.code() += "} // conditional\n";
163 cp.code() += "} // block\n";
164 } // block
165 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
166 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
167 // -----------------------------------------------------------------------------
168  cp.getAffectedRegisters().add("instructionPointer", 32);
169  }
170  {
171  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
172 
173  cp.code() = std::string("//FSD\n");
174 
175 // -----------------------------------------------------------------------------
176 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
177 // -----------------------------------------------------------------------------
178  }
179 
180  return true;
181  },
182  0,
183  [] (BitArray & ba, Instruction & instr)
184  {
185 // -----------------------------------------------------------------------------
186 etiss_uint16 imm = 0;
187 static BitArrayRange R_imm_0(11, 7);
188 imm += R_imm_0.read(ba) << 0;
189 etiss_uint8 rs1 = 0;
190 static BitArrayRange R_rs1_0(19, 15);
191 rs1 += R_rs1_0.read(ba) << 0;
192 etiss_uint8 rs2 = 0;
193 static BitArrayRange R_rs2_0(24, 20);
194 rs2 += R_rs2_0.read(ba) << 0;
195 static BitArrayRange R_imm_5(31, 25);
196 imm += R_imm_5.read(ba) << 5;
197 
198 // -----------------------------------------------------------------------------
199 
200  std::stringstream ss;
201 // -----------------------------------------------------------------------------
202 ss << "fsd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
203 // -----------------------------------------------------------------------------
204  return ss.str();
205  }
206 );
207 
208 // FMADD_D ---------------------------------------------------------------------
209 static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 (
210  ISA32_RV64IMACFD,
211  "fmadd_d",
212  (uint32_t) 0x2000043,
213  (uint32_t) 0x600007f,
214  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
215  {
216 
217 // -----------------------------------------------------------------------------
218 
219 // -----------------------------------------------------------------------------
220 
221 // -----------------------------------------------------------------------------
222 etiss_uint8 rd = 0;
223 static BitArrayRange R_rd_0(11, 7);
224 rd += R_rd_0.read(ba) << 0;
225 etiss_uint8 rm = 0;
226 static BitArrayRange R_rm_0(14, 12);
227 rm += R_rm_0.read(ba) << 0;
228 etiss_uint8 rs1 = 0;
229 static BitArrayRange R_rs1_0(19, 15);
230 rs1 += R_rs1_0.read(ba) << 0;
231 etiss_uint8 rs2 = 0;
232 static BitArrayRange R_rs2_0(24, 20);
233 rs2 += R_rs2_0.read(ba) << 0;
234 etiss_uint8 rs3 = 0;
235 static BitArrayRange R_rs3_0(31, 27);
236 rs3 += R_rs3_0.read(ba) << 0;
237 
238 // -----------------------------------------------------------------------------
239 
240  {
241  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
242 
243  cp.code() = std::string("//FMADD_D\n");
244 
245 // -----------------------------------------------------------------------------
246 { // block
247 cp.code() += "{ // block\n";
248 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
249 cp.code() += "} // block\n";
250 } // block
251 { // block
252 cp.code() += "{ // block\n";
253 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
254 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
255 cp.code() += "etiss_uint32 flags = fget_flags();\n";
256 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
257 cp.code() += "} // block\n";
258 } // block
259 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
260 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
261 // -----------------------------------------------------------------------------
262  cp.getAffectedRegisters().add("instructionPointer", 32);
263  }
264 
265  return true;
266  },
267  0,
268  [] (BitArray & ba, Instruction & instr)
269  {
270 // -----------------------------------------------------------------------------
271 etiss_uint8 rd = 0;
272 static BitArrayRange R_rd_0(11, 7);
273 rd += R_rd_0.read(ba) << 0;
274 etiss_uint8 rm = 0;
275 static BitArrayRange R_rm_0(14, 12);
276 rm += R_rm_0.read(ba) << 0;
277 etiss_uint8 rs1 = 0;
278 static BitArrayRange R_rs1_0(19, 15);
279 rs1 += R_rs1_0.read(ba) << 0;
280 etiss_uint8 rs2 = 0;
281 static BitArrayRange R_rs2_0(24, 20);
282 rs2 += R_rs2_0.read(ba) << 0;
283 etiss_uint8 rs3 = 0;
284 static BitArrayRange R_rs3_0(31, 27);
285 rs3 += R_rs3_0.read(ba) << 0;
286 
287 // -----------------------------------------------------------------------------
288 
289  std::stringstream ss;
290 // -----------------------------------------------------------------------------
291 ss << "fmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
292 // -----------------------------------------------------------------------------
293  return ss.str();
294  }
295 );
296 
297 // FMSUB_D ---------------------------------------------------------------------
298 static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 (
299  ISA32_RV64IMACFD,
300  "fmsub_d",
301  (uint32_t) 0x2000047,
302  (uint32_t) 0x600007f,
303  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
304  {
305 
306 // -----------------------------------------------------------------------------
307 
308 // -----------------------------------------------------------------------------
309 
310 // -----------------------------------------------------------------------------
311 etiss_uint8 rd = 0;
312 static BitArrayRange R_rd_0(11, 7);
313 rd += R_rd_0.read(ba) << 0;
314 etiss_uint8 rm = 0;
315 static BitArrayRange R_rm_0(14, 12);
316 rm += R_rm_0.read(ba) << 0;
317 etiss_uint8 rs1 = 0;
318 static BitArrayRange R_rs1_0(19, 15);
319 rs1 += R_rs1_0.read(ba) << 0;
320 etiss_uint8 rs2 = 0;
321 static BitArrayRange R_rs2_0(24, 20);
322 rs2 += R_rs2_0.read(ba) << 0;
323 etiss_uint8 rs3 = 0;
324 static BitArrayRange R_rs3_0(31, 27);
325 rs3 += R_rs3_0.read(ba) << 0;
326 
327 // -----------------------------------------------------------------------------
328 
329  {
330  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
331 
332  cp.code() = std::string("//FMSUB_D\n");
333 
334 // -----------------------------------------------------------------------------
335 { // block
336 cp.code() += "{ // block\n";
337 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
338 cp.code() += "} // block\n";
339 } // block
340 { // block
341 cp.code() += "{ // block\n";
342 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
343 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
344 cp.code() += "etiss_uint32 flags = fget_flags();\n";
345 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
346 cp.code() += "} // block\n";
347 } // block
348 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
349 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
350 // -----------------------------------------------------------------------------
351  cp.getAffectedRegisters().add("instructionPointer", 32);
352  }
353 
354  return true;
355  },
356  0,
357  [] (BitArray & ba, Instruction & instr)
358  {
359 // -----------------------------------------------------------------------------
360 etiss_uint8 rd = 0;
361 static BitArrayRange R_rd_0(11, 7);
362 rd += R_rd_0.read(ba) << 0;
363 etiss_uint8 rm = 0;
364 static BitArrayRange R_rm_0(14, 12);
365 rm += R_rm_0.read(ba) << 0;
366 etiss_uint8 rs1 = 0;
367 static BitArrayRange R_rs1_0(19, 15);
368 rs1 += R_rs1_0.read(ba) << 0;
369 etiss_uint8 rs2 = 0;
370 static BitArrayRange R_rs2_0(24, 20);
371 rs2 += R_rs2_0.read(ba) << 0;
372 etiss_uint8 rs3 = 0;
373 static BitArrayRange R_rs3_0(31, 27);
374 rs3 += R_rs3_0.read(ba) << 0;
375 
376 // -----------------------------------------------------------------------------
377 
378  std::stringstream ss;
379 // -----------------------------------------------------------------------------
380 ss << "fmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
381 // -----------------------------------------------------------------------------
382  return ss.str();
383  }
384 );
385 
386 // FNMADD_D --------------------------------------------------------------------
387 static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 (
388  ISA32_RV64IMACFD,
389  "fnmadd_d",
390  (uint32_t) 0x200004f,
391  (uint32_t) 0x600007f,
392  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
393  {
394 
395 // -----------------------------------------------------------------------------
396 
397 // -----------------------------------------------------------------------------
398 
399 // -----------------------------------------------------------------------------
400 etiss_uint8 rd = 0;
401 static BitArrayRange R_rd_0(11, 7);
402 rd += R_rd_0.read(ba) << 0;
403 etiss_uint8 rm = 0;
404 static BitArrayRange R_rm_0(14, 12);
405 rm += R_rm_0.read(ba) << 0;
406 etiss_uint8 rs1 = 0;
407 static BitArrayRange R_rs1_0(19, 15);
408 rs1 += R_rs1_0.read(ba) << 0;
409 etiss_uint8 rs2 = 0;
410 static BitArrayRange R_rs2_0(24, 20);
411 rs2 += R_rs2_0.read(ba) << 0;
412 etiss_uint8 rs3 = 0;
413 static BitArrayRange R_rs3_0(31, 27);
414 rs3 += R_rs3_0.read(ba) << 0;
415 
416 // -----------------------------------------------------------------------------
417 
418  {
419  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
420 
421  cp.code() = std::string("//FNMADD_D\n");
422 
423 // -----------------------------------------------------------------------------
424 { // block
425 cp.code() += "{ // block\n";
426 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
427 cp.code() += "} // block\n";
428 } // block
429 { // block
430 cp.code() += "{ // block\n";
431 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
432 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
433 cp.code() += "etiss_uint32 flags = fget_flags();\n";
434 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
435 cp.code() += "} // block\n";
436 } // block
437 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
438 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
439 // -----------------------------------------------------------------------------
440  cp.getAffectedRegisters().add("instructionPointer", 32);
441  }
442 
443  return true;
444  },
445  0,
446  [] (BitArray & ba, Instruction & instr)
447  {
448 // -----------------------------------------------------------------------------
449 etiss_uint8 rd = 0;
450 static BitArrayRange R_rd_0(11, 7);
451 rd += R_rd_0.read(ba) << 0;
452 etiss_uint8 rm = 0;
453 static BitArrayRange R_rm_0(14, 12);
454 rm += R_rm_0.read(ba) << 0;
455 etiss_uint8 rs1 = 0;
456 static BitArrayRange R_rs1_0(19, 15);
457 rs1 += R_rs1_0.read(ba) << 0;
458 etiss_uint8 rs2 = 0;
459 static BitArrayRange R_rs2_0(24, 20);
460 rs2 += R_rs2_0.read(ba) << 0;
461 etiss_uint8 rs3 = 0;
462 static BitArrayRange R_rs3_0(31, 27);
463 rs3 += R_rs3_0.read(ba) << 0;
464 
465 // -----------------------------------------------------------------------------
466 
467  std::stringstream ss;
468 // -----------------------------------------------------------------------------
469 ss << "fnmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
470 // -----------------------------------------------------------------------------
471  return ss.str();
472  }
473 );
474 
475 // FNMSUB_D --------------------------------------------------------------------
476 static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 (
477  ISA32_RV64IMACFD,
478  "fnmsub_d",
479  (uint32_t) 0x200004b,
480  (uint32_t) 0x600007f,
481  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
482  {
483 
484 // -----------------------------------------------------------------------------
485 
486 // -----------------------------------------------------------------------------
487 
488 // -----------------------------------------------------------------------------
489 etiss_uint8 rd = 0;
490 static BitArrayRange R_rd_0(11, 7);
491 rd += R_rd_0.read(ba) << 0;
492 etiss_uint8 rm = 0;
493 static BitArrayRange R_rm_0(14, 12);
494 rm += R_rm_0.read(ba) << 0;
495 etiss_uint8 rs1 = 0;
496 static BitArrayRange R_rs1_0(19, 15);
497 rs1 += R_rs1_0.read(ba) << 0;
498 etiss_uint8 rs2 = 0;
499 static BitArrayRange R_rs2_0(24, 20);
500 rs2 += R_rs2_0.read(ba) << 0;
501 etiss_uint8 rs3 = 0;
502 static BitArrayRange R_rs3_0(31, 27);
503 rs3 += R_rs3_0.read(ba) << 0;
504 
505 // -----------------------------------------------------------------------------
506 
507  {
508  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
509 
510  cp.code() = std::string("//FNMSUB_D\n");
511 
512 // -----------------------------------------------------------------------------
513 { // block
514 cp.code() += "{ // block\n";
515 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
516 cp.code() += "} // block\n";
517 } // block
518 { // block
519 cp.code() += "{ // block\n";
520 cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
521 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
522 cp.code() += "etiss_uint32 flags = fget_flags();\n";
523 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
524 cp.code() += "} // block\n";
525 } // block
526 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
527 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
528 // -----------------------------------------------------------------------------
529  cp.getAffectedRegisters().add("instructionPointer", 32);
530  }
531 
532  return true;
533  },
534  0,
535  [] (BitArray & ba, Instruction & instr)
536  {
537 // -----------------------------------------------------------------------------
538 etiss_uint8 rd = 0;
539 static BitArrayRange R_rd_0(11, 7);
540 rd += R_rd_0.read(ba) << 0;
541 etiss_uint8 rm = 0;
542 static BitArrayRange R_rm_0(14, 12);
543 rm += R_rm_0.read(ba) << 0;
544 etiss_uint8 rs1 = 0;
545 static BitArrayRange R_rs1_0(19, 15);
546 rs1 += R_rs1_0.read(ba) << 0;
547 etiss_uint8 rs2 = 0;
548 static BitArrayRange R_rs2_0(24, 20);
549 rs2 += R_rs2_0.read(ba) << 0;
550 etiss_uint8 rs3 = 0;
551 static BitArrayRange R_rs3_0(31, 27);
552 rs3 += R_rs3_0.read(ba) << 0;
553 
554 // -----------------------------------------------------------------------------
555 
556  std::stringstream ss;
557 // -----------------------------------------------------------------------------
558 ss << "fnmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
559 // -----------------------------------------------------------------------------
560  return ss.str();
561  }
562 );
563 
564 // FADD_D ----------------------------------------------------------------------
565 static InstructionDefinition fadd_d_rd_rm_rs1_rs2 (
566  ISA32_RV64IMACFD,
567  "fadd_d",
568  (uint32_t) 0x2000053,
569  (uint32_t) 0xfe00007f,
570  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
571  {
572 
573 // -----------------------------------------------------------------------------
574 
575 // -----------------------------------------------------------------------------
576 
577 // -----------------------------------------------------------------------------
578 etiss_uint8 rd = 0;
579 static BitArrayRange R_rd_0(11, 7);
580 rd += R_rd_0.read(ba) << 0;
581 etiss_uint8 rm = 0;
582 static BitArrayRange R_rm_0(14, 12);
583 rm += R_rm_0.read(ba) << 0;
584 etiss_uint8 rs1 = 0;
585 static BitArrayRange R_rs1_0(19, 15);
586 rs1 += R_rs1_0.read(ba) << 0;
587 etiss_uint8 rs2 = 0;
588 static BitArrayRange R_rs2_0(24, 20);
589 rs2 += R_rs2_0.read(ba) << 0;
590 
591 // -----------------------------------------------------------------------------
592 
593  {
594  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
595 
596  cp.code() = std::string("//FADD_D\n");
597 
598 // -----------------------------------------------------------------------------
599 { // block
600 cp.code() += "{ // block\n";
601 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
602 cp.code() += "} // block\n";
603 } // block
604 { // block
605 cp.code() += "{ // block\n";
606 cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
607 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
608 cp.code() += "etiss_uint32 flags = fget_flags();\n";
609 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
610 cp.code() += "} // block\n";
611 } // block
612 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
613 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
614 // -----------------------------------------------------------------------------
615  cp.getAffectedRegisters().add("instructionPointer", 32);
616  }
617 
618  return true;
619  },
620  0,
621  [] (BitArray & ba, Instruction & instr)
622  {
623 // -----------------------------------------------------------------------------
624 etiss_uint8 rd = 0;
625 static BitArrayRange R_rd_0(11, 7);
626 rd += R_rd_0.read(ba) << 0;
627 etiss_uint8 rm = 0;
628 static BitArrayRange R_rm_0(14, 12);
629 rm += R_rm_0.read(ba) << 0;
630 etiss_uint8 rs1 = 0;
631 static BitArrayRange R_rs1_0(19, 15);
632 rs1 += R_rs1_0.read(ba) << 0;
633 etiss_uint8 rs2 = 0;
634 static BitArrayRange R_rs2_0(24, 20);
635 rs2 += R_rs2_0.read(ba) << 0;
636 
637 // -----------------------------------------------------------------------------
638 
639  std::stringstream ss;
640 // -----------------------------------------------------------------------------
641 ss << "fadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
642 // -----------------------------------------------------------------------------
643  return ss.str();
644  }
645 );
646 
647 // FSUB_D ----------------------------------------------------------------------
648 static InstructionDefinition fsub_d_rd_rm_rs1_rs2 (
649  ISA32_RV64IMACFD,
650  "fsub_d",
651  (uint32_t) 0xa000053,
652  (uint32_t) 0xfe00007f,
653  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
654  {
655 
656 // -----------------------------------------------------------------------------
657 
658 // -----------------------------------------------------------------------------
659 
660 // -----------------------------------------------------------------------------
661 etiss_uint8 rd = 0;
662 static BitArrayRange R_rd_0(11, 7);
663 rd += R_rd_0.read(ba) << 0;
664 etiss_uint8 rm = 0;
665 static BitArrayRange R_rm_0(14, 12);
666 rm += R_rm_0.read(ba) << 0;
667 etiss_uint8 rs1 = 0;
668 static BitArrayRange R_rs1_0(19, 15);
669 rs1 += R_rs1_0.read(ba) << 0;
670 etiss_uint8 rs2 = 0;
671 static BitArrayRange R_rs2_0(24, 20);
672 rs2 += R_rs2_0.read(ba) << 0;
673 
674 // -----------------------------------------------------------------------------
675 
676  {
677  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
678 
679  cp.code() = std::string("//FSUB_D\n");
680 
681 // -----------------------------------------------------------------------------
682 { // block
683 cp.code() += "{ // block\n";
684 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
685 cp.code() += "} // block\n";
686 } // block
687 { // block
688 cp.code() += "{ // block\n";
689 cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
690 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
691 cp.code() += "etiss_uint32 flags = fget_flags();\n";
692 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
693 cp.code() += "} // block\n";
694 } // block
695 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
696 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
697 // -----------------------------------------------------------------------------
698  cp.getAffectedRegisters().add("instructionPointer", 32);
699  }
700 
701  return true;
702  },
703  0,
704  [] (BitArray & ba, Instruction & instr)
705  {
706 // -----------------------------------------------------------------------------
707 etiss_uint8 rd = 0;
708 static BitArrayRange R_rd_0(11, 7);
709 rd += R_rd_0.read(ba) << 0;
710 etiss_uint8 rm = 0;
711 static BitArrayRange R_rm_0(14, 12);
712 rm += R_rm_0.read(ba) << 0;
713 etiss_uint8 rs1 = 0;
714 static BitArrayRange R_rs1_0(19, 15);
715 rs1 += R_rs1_0.read(ba) << 0;
716 etiss_uint8 rs2 = 0;
717 static BitArrayRange R_rs2_0(24, 20);
718 rs2 += R_rs2_0.read(ba) << 0;
719 
720 // -----------------------------------------------------------------------------
721 
722  std::stringstream ss;
723 // -----------------------------------------------------------------------------
724 ss << "fsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
725 // -----------------------------------------------------------------------------
726  return ss.str();
727  }
728 );
729 
730 // FMUL_D ----------------------------------------------------------------------
731 static InstructionDefinition fmul_d_rd_rm_rs1_rs2 (
732  ISA32_RV64IMACFD,
733  "fmul_d",
734  (uint32_t) 0x12000053,
735  (uint32_t) 0xfe00007f,
736  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
737  {
738 
739 // -----------------------------------------------------------------------------
740 
741 // -----------------------------------------------------------------------------
742 
743 // -----------------------------------------------------------------------------
744 etiss_uint8 rd = 0;
745 static BitArrayRange R_rd_0(11, 7);
746 rd += R_rd_0.read(ba) << 0;
747 etiss_uint8 rm = 0;
748 static BitArrayRange R_rm_0(14, 12);
749 rm += R_rm_0.read(ba) << 0;
750 etiss_uint8 rs1 = 0;
751 static BitArrayRange R_rs1_0(19, 15);
752 rs1 += R_rs1_0.read(ba) << 0;
753 etiss_uint8 rs2 = 0;
754 static BitArrayRange R_rs2_0(24, 20);
755 rs2 += R_rs2_0.read(ba) << 0;
756 
757 // -----------------------------------------------------------------------------
758 
759  {
760  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
761 
762  cp.code() = std::string("//FMUL_D\n");
763 
764 // -----------------------------------------------------------------------------
765 { // block
766 cp.code() += "{ // block\n";
767 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
768 cp.code() += "} // block\n";
769 } // block
770 { // block
771 cp.code() += "{ // block\n";
772 cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
773 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
774 cp.code() += "etiss_uint32 flags = fget_flags();\n";
775 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
776 cp.code() += "} // block\n";
777 } // block
778 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
779 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
780 // -----------------------------------------------------------------------------
781  cp.getAffectedRegisters().add("instructionPointer", 32);
782  }
783 
784  return true;
785  },
786  0,
787  [] (BitArray & ba, Instruction & instr)
788  {
789 // -----------------------------------------------------------------------------
790 etiss_uint8 rd = 0;
791 static BitArrayRange R_rd_0(11, 7);
792 rd += R_rd_0.read(ba) << 0;
793 etiss_uint8 rm = 0;
794 static BitArrayRange R_rm_0(14, 12);
795 rm += R_rm_0.read(ba) << 0;
796 etiss_uint8 rs1 = 0;
797 static BitArrayRange R_rs1_0(19, 15);
798 rs1 += R_rs1_0.read(ba) << 0;
799 etiss_uint8 rs2 = 0;
800 static BitArrayRange R_rs2_0(24, 20);
801 rs2 += R_rs2_0.read(ba) << 0;
802 
803 // -----------------------------------------------------------------------------
804 
805  std::stringstream ss;
806 // -----------------------------------------------------------------------------
807 ss << "fmul_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
808 // -----------------------------------------------------------------------------
809  return ss.str();
810  }
811 );
812 
813 // FDIV_D ----------------------------------------------------------------------
814 static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 (
815  ISA32_RV64IMACFD,
816  "fdiv_d",
817  (uint32_t) 0x1a000053,
818  (uint32_t) 0xfe00007f,
819  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
820  {
821 
822 // -----------------------------------------------------------------------------
823 
824 // -----------------------------------------------------------------------------
825 
826 // -----------------------------------------------------------------------------
827 etiss_uint8 rd = 0;
828 static BitArrayRange R_rd_0(11, 7);
829 rd += R_rd_0.read(ba) << 0;
830 etiss_uint8 rm = 0;
831 static BitArrayRange R_rm_0(14, 12);
832 rm += R_rm_0.read(ba) << 0;
833 etiss_uint8 rs1 = 0;
834 static BitArrayRange R_rs1_0(19, 15);
835 rs1 += R_rs1_0.read(ba) << 0;
836 etiss_uint8 rs2 = 0;
837 static BitArrayRange R_rs2_0(24, 20);
838 rs2 += R_rs2_0.read(ba) << 0;
839 
840 // -----------------------------------------------------------------------------
841 
842  {
843  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
844 
845  cp.code() = std::string("//FDIV_D\n");
846 
847 // -----------------------------------------------------------------------------
848 { // block
849 cp.code() += "{ // block\n";
850 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
851 cp.code() += "} // block\n";
852 } // block
853 { // block
854 cp.code() += "{ // block\n";
855 cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
856 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
857 cp.code() += "etiss_uint32 flags = fget_flags();\n";
858 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
859 cp.code() += "} // block\n";
860 } // block
861 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
862 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
863 // -----------------------------------------------------------------------------
864  cp.getAffectedRegisters().add("instructionPointer", 32);
865  }
866 
867  return true;
868  },
869  0,
870  [] (BitArray & ba, Instruction & instr)
871  {
872 // -----------------------------------------------------------------------------
873 etiss_uint8 rd = 0;
874 static BitArrayRange R_rd_0(11, 7);
875 rd += R_rd_0.read(ba) << 0;
876 etiss_uint8 rm = 0;
877 static BitArrayRange R_rm_0(14, 12);
878 rm += R_rm_0.read(ba) << 0;
879 etiss_uint8 rs1 = 0;
880 static BitArrayRange R_rs1_0(19, 15);
881 rs1 += R_rs1_0.read(ba) << 0;
882 etiss_uint8 rs2 = 0;
883 static BitArrayRange R_rs2_0(24, 20);
884 rs2 += R_rs2_0.read(ba) << 0;
885 
886 // -----------------------------------------------------------------------------
887 
888  std::stringstream ss;
889 // -----------------------------------------------------------------------------
890 ss << "fdiv_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
891 // -----------------------------------------------------------------------------
892  return ss.str();
893  }
894 );
895 
896 // FSQRT_D ---------------------------------------------------------------------
897 static InstructionDefinition fsqrt_d_rd_rm_rs1 (
898  ISA32_RV64IMACFD,
899  "fsqrt_d",
900  (uint32_t) 0x5a000053,
901  (uint32_t) 0xfff0007f,
902  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
903  {
904 
905 // -----------------------------------------------------------------------------
906 
907 // -----------------------------------------------------------------------------
908 
909 // -----------------------------------------------------------------------------
910 etiss_uint8 rd = 0;
911 static BitArrayRange R_rd_0(11, 7);
912 rd += R_rd_0.read(ba) << 0;
913 etiss_uint8 rm = 0;
914 static BitArrayRange R_rm_0(14, 12);
915 rm += R_rm_0.read(ba) << 0;
916 etiss_uint8 rs1 = 0;
917 static BitArrayRange R_rs1_0(19, 15);
918 rs1 += R_rs1_0.read(ba) << 0;
919 
920 // -----------------------------------------------------------------------------
921 
922  {
923  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
924 
925  cp.code() = std::string("//FSQRT_D\n");
926 
927 // -----------------------------------------------------------------------------
928 { // block
929 cp.code() += "{ // block\n";
930 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
931 cp.code() += "} // block\n";
932 } // block
933 { // block
934 cp.code() += "{ // block\n";
935 cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
936 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
937 cp.code() += "etiss_uint32 flags = fget_flags();\n";
938 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
939 cp.code() += "} // block\n";
940 } // block
941 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
942 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
943 // -----------------------------------------------------------------------------
944  cp.getAffectedRegisters().add("instructionPointer", 32);
945  }
946 
947  return true;
948  },
949  0,
950  [] (BitArray & ba, Instruction & instr)
951  {
952 // -----------------------------------------------------------------------------
953 etiss_uint8 rd = 0;
954 static BitArrayRange R_rd_0(11, 7);
955 rd += R_rd_0.read(ba) << 0;
956 etiss_uint8 rm = 0;
957 static BitArrayRange R_rm_0(14, 12);
958 rm += R_rm_0.read(ba) << 0;
959 etiss_uint8 rs1 = 0;
960 static BitArrayRange R_rs1_0(19, 15);
961 rs1 += R_rs1_0.read(ba) << 0;
962 
963 // -----------------------------------------------------------------------------
964 
965  std::stringstream ss;
966 // -----------------------------------------------------------------------------
967 ss << "fsqrt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
968 // -----------------------------------------------------------------------------
969  return ss.str();
970  }
971 );
972 
973 // FSGNJ_D ---------------------------------------------------------------------
974 static InstructionDefinition fsgnj_d_rd_rs1_rs2 (
975  ISA32_RV64IMACFD,
976  "fsgnj_d",
977  (uint32_t) 0x22000053,
978  (uint32_t) 0xfe00707f,
979  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
980  {
981 
982 // -----------------------------------------------------------------------------
983 
984 // -----------------------------------------------------------------------------
985 
986 // -----------------------------------------------------------------------------
987 etiss_uint8 rd = 0;
988 static BitArrayRange R_rd_0(11, 7);
989 rd += R_rd_0.read(ba) << 0;
990 etiss_uint8 rs1 = 0;
991 static BitArrayRange R_rs1_0(19, 15);
992 rs1 += R_rs1_0.read(ba) << 0;
993 etiss_uint8 rs2 = 0;
994 static BitArrayRange R_rs2_0(24, 20);
995 rs2 += R_rs2_0.read(ba) << 0;
996 
997 // -----------------------------------------------------------------------------
998 
999  {
1000  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1001 
1002  cp.code() = std::string("//FSGNJ_D\n");
1003 
1004 // -----------------------------------------------------------------------------
1005 { // block
1006 cp.code() += "{ // block\n";
1007 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1008 cp.code() += "} // block\n";
1009 } // block
1010 { // block
1011 cp.code() += "{ // block\n";
1012 cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1ULL)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";
1013 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1014 cp.code() += "} // block\n";
1015 } // block
1016 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1017 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1018 // -----------------------------------------------------------------------------
1019  cp.getAffectedRegisters().add("instructionPointer", 32);
1020  }
1021 
1022  return true;
1023  },
1024  0,
1025  [] (BitArray & ba, Instruction & instr)
1026  {
1027 // -----------------------------------------------------------------------------
1028 etiss_uint8 rd = 0;
1029 static BitArrayRange R_rd_0(11, 7);
1030 rd += R_rd_0.read(ba) << 0;
1031 etiss_uint8 rs1 = 0;
1032 static BitArrayRange R_rs1_0(19, 15);
1033 rs1 += R_rs1_0.read(ba) << 0;
1034 etiss_uint8 rs2 = 0;
1035 static BitArrayRange R_rs2_0(24, 20);
1036 rs2 += R_rs2_0.read(ba) << 0;
1037 
1038 // -----------------------------------------------------------------------------
1039 
1040  std::stringstream ss;
1041 // -----------------------------------------------------------------------------
1042 ss << "fsgnj_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1043 // -----------------------------------------------------------------------------
1044  return ss.str();
1045  }
1046 );
1047 
1048 // FSGNJN_D --------------------------------------------------------------------
1049 static InstructionDefinition fsgnjn_d_rd_rs1_rs2 (
1050  ISA32_RV64IMACFD,
1051  "fsgnjn_d",
1052  (uint32_t) 0x22001053,
1053  (uint32_t) 0xfe00707f,
1054  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1055  {
1056 
1057 // -----------------------------------------------------------------------------
1058 
1059 // -----------------------------------------------------------------------------
1060 
1061 // -----------------------------------------------------------------------------
1062 etiss_uint8 rd = 0;
1063 static BitArrayRange R_rd_0(11, 7);
1064 rd += R_rd_0.read(ba) << 0;
1065 etiss_uint8 rs1 = 0;
1066 static BitArrayRange R_rs1_0(19, 15);
1067 rs1 += R_rs1_0.read(ba) << 0;
1068 etiss_uint8 rs2 = 0;
1069 static BitArrayRange R_rs2_0(24, 20);
1070 rs2 += R_rs2_0.read(ba) << 0;
1071 
1072 // -----------------------------------------------------------------------------
1073 
1074  {
1075  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1076 
1077  cp.code() = std::string("//FSGNJN_D\n");
1078 
1079 // -----------------------------------------------------------------------------
1080 { // block
1081 cp.code() += "{ // block\n";
1082 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1083 cp.code() += "} // block\n";
1084 } // block
1085 { // block
1086 cp.code() += "{ // block\n";
1087 cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1ULL))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";
1088 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1089 cp.code() += "} // block\n";
1090 } // block
1091 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1092 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1093 // -----------------------------------------------------------------------------
1094  cp.getAffectedRegisters().add("instructionPointer", 32);
1095  }
1096 
1097  return true;
1098  },
1099  0,
1100  [] (BitArray & ba, Instruction & instr)
1101  {
1102 // -----------------------------------------------------------------------------
1103 etiss_uint8 rd = 0;
1104 static BitArrayRange R_rd_0(11, 7);
1105 rd += R_rd_0.read(ba) << 0;
1106 etiss_uint8 rs1 = 0;
1107 static BitArrayRange R_rs1_0(19, 15);
1108 rs1 += R_rs1_0.read(ba) << 0;
1109 etiss_uint8 rs2 = 0;
1110 static BitArrayRange R_rs2_0(24, 20);
1111 rs2 += R_rs2_0.read(ba) << 0;
1112 
1113 // -----------------------------------------------------------------------------
1114 
1115  std::stringstream ss;
1116 // -----------------------------------------------------------------------------
1117 ss << "fsgnjn_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1118 // -----------------------------------------------------------------------------
1119  return ss.str();
1120  }
1121 );
1122 
1123 // FSGNJX_D --------------------------------------------------------------------
1124 static InstructionDefinition fsgnjx_d_rd_rs1_rs2 (
1125  ISA32_RV64IMACFD,
1126  "fsgnjx_d",
1127  (uint32_t) 0x22002053,
1128  (uint32_t) 0xfe00707f,
1129  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1130  {
1131 
1132 // -----------------------------------------------------------------------------
1133 
1134 // -----------------------------------------------------------------------------
1135 
1136 // -----------------------------------------------------------------------------
1137 etiss_uint8 rd = 0;
1138 static BitArrayRange R_rd_0(11, 7);
1139 rd += R_rd_0.read(ba) << 0;
1140 etiss_uint8 rs1 = 0;
1141 static BitArrayRange R_rs1_0(19, 15);
1142 rs1 += R_rs1_0.read(ba) << 0;
1143 etiss_uint8 rs2 = 0;
1144 static BitArrayRange R_rs2_0(24, 20);
1145 rs2 += R_rs2_0.read(ba) << 0;
1146 
1147 // -----------------------------------------------------------------------------
1148 
1149  {
1150  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1151 
1152  cp.code() = std::string("//FSGNJX_D\n");
1153 
1154 // -----------------------------------------------------------------------------
1155 { // block
1156 cp.code() += "{ // block\n";
1157 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1158 cp.code() += "} // block\n";
1159 } // block
1160 { // block
1161 cp.code() += "{ // block\n";
1162 cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
1163 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1164 cp.code() += "} // block\n";
1165 } // block
1166 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1167 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1168 // -----------------------------------------------------------------------------
1169  cp.getAffectedRegisters().add("instructionPointer", 32);
1170  }
1171 
1172  return true;
1173  },
1174  0,
1175  [] (BitArray & ba, Instruction & instr)
1176  {
1177 // -----------------------------------------------------------------------------
1178 etiss_uint8 rd = 0;
1179 static BitArrayRange R_rd_0(11, 7);
1180 rd += R_rd_0.read(ba) << 0;
1181 etiss_uint8 rs1 = 0;
1182 static BitArrayRange R_rs1_0(19, 15);
1183 rs1 += R_rs1_0.read(ba) << 0;
1184 etiss_uint8 rs2 = 0;
1185 static BitArrayRange R_rs2_0(24, 20);
1186 rs2 += R_rs2_0.read(ba) << 0;
1187 
1188 // -----------------------------------------------------------------------------
1189 
1190  std::stringstream ss;
1191 // -----------------------------------------------------------------------------
1192 ss << "fsgnjx_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1193 // -----------------------------------------------------------------------------
1194  return ss.str();
1195  }
1196 );
1197 
1198 // FMIN_D ----------------------------------------------------------------------
1199 static InstructionDefinition fmin_d_rd_rs1_rs2 (
1200  ISA32_RV64IMACFD,
1201  "fmin_d",
1202  (uint32_t) 0x2a000053,
1203  (uint32_t) 0xfe00707f,
1204  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1205  {
1206 
1207 // -----------------------------------------------------------------------------
1208 
1209 // -----------------------------------------------------------------------------
1210 
1211 // -----------------------------------------------------------------------------
1212 etiss_uint8 rd = 0;
1213 static BitArrayRange R_rd_0(11, 7);
1214 rd += R_rd_0.read(ba) << 0;
1215 etiss_uint8 rs1 = 0;
1216 static BitArrayRange R_rs1_0(19, 15);
1217 rs1 += R_rs1_0.read(ba) << 0;
1218 etiss_uint8 rs2 = 0;
1219 static BitArrayRange R_rs2_0(24, 20);
1220 rs2 += R_rs2_0.read(ba) << 0;
1221 
1222 // -----------------------------------------------------------------------------
1223 
1224  {
1225  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1226 
1227  cp.code() = std::string("//FMIN_D\n");
1228 
1229 // -----------------------------------------------------------------------------
1230 { // block
1231 cp.code() += "{ // block\n";
1232 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1233 cp.code() += "} // block\n";
1234 } // block
1235 { // block
1236 cp.code() += "{ // block\n";
1237 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0LL);\n";
1238 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1239 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1240 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1241 cp.code() += "} // block\n";
1242 } // block
1243 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1244 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1245 // -----------------------------------------------------------------------------
1246  cp.getAffectedRegisters().add("instructionPointer", 32);
1247  }
1248 
1249  return true;
1250  },
1251  0,
1252  [] (BitArray & ba, Instruction & instr)
1253  {
1254 // -----------------------------------------------------------------------------
1255 etiss_uint8 rd = 0;
1256 static BitArrayRange R_rd_0(11, 7);
1257 rd += R_rd_0.read(ba) << 0;
1258 etiss_uint8 rs1 = 0;
1259 static BitArrayRange R_rs1_0(19, 15);
1260 rs1 += R_rs1_0.read(ba) << 0;
1261 etiss_uint8 rs2 = 0;
1262 static BitArrayRange R_rs2_0(24, 20);
1263 rs2 += R_rs2_0.read(ba) << 0;
1264 
1265 // -----------------------------------------------------------------------------
1266 
1267  std::stringstream ss;
1268 // -----------------------------------------------------------------------------
1269 ss << "fmin_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1270 // -----------------------------------------------------------------------------
1271  return ss.str();
1272  }
1273 );
1274 
1275 // FMAX_D ----------------------------------------------------------------------
1276 static InstructionDefinition fmax_d_rd_rs1_rs2 (
1277  ISA32_RV64IMACFD,
1278  "fmax_d",
1279  (uint32_t) 0x2a001053,
1280  (uint32_t) 0xfe00707f,
1281  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1282  {
1283 
1284 // -----------------------------------------------------------------------------
1285 
1286 // -----------------------------------------------------------------------------
1287 
1288 // -----------------------------------------------------------------------------
1289 etiss_uint8 rd = 0;
1290 static BitArrayRange R_rd_0(11, 7);
1291 rd += R_rd_0.read(ba) << 0;
1292 etiss_uint8 rs1 = 0;
1293 static BitArrayRange R_rs1_0(19, 15);
1294 rs1 += R_rs1_0.read(ba) << 0;
1295 etiss_uint8 rs2 = 0;
1296 static BitArrayRange R_rs2_0(24, 20);
1297 rs2 += R_rs2_0.read(ba) << 0;
1298 
1299 // -----------------------------------------------------------------------------
1300 
1301  {
1302  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1303 
1304  cp.code() = std::string("//FMAX_D\n");
1305 
1306 // -----------------------------------------------------------------------------
1307 { // block
1308 cp.code() += "{ // block\n";
1309 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1310 cp.code() += "} // block\n";
1311 } // block
1312 { // block
1313 cp.code() += "{ // block\n";
1314 cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
1315 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1316 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1317 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1318 cp.code() += "} // block\n";
1319 } // block
1320 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1321 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1322 // -----------------------------------------------------------------------------
1323  cp.getAffectedRegisters().add("instructionPointer", 32);
1324  }
1325 
1326  return true;
1327  },
1328  0,
1329  [] (BitArray & ba, Instruction & instr)
1330  {
1331 // -----------------------------------------------------------------------------
1332 etiss_uint8 rd = 0;
1333 static BitArrayRange R_rd_0(11, 7);
1334 rd += R_rd_0.read(ba) << 0;
1335 etiss_uint8 rs1 = 0;
1336 static BitArrayRange R_rs1_0(19, 15);
1337 rs1 += R_rs1_0.read(ba) << 0;
1338 etiss_uint8 rs2 = 0;
1339 static BitArrayRange R_rs2_0(24, 20);
1340 rs2 += R_rs2_0.read(ba) << 0;
1341 
1342 // -----------------------------------------------------------------------------
1343 
1344  std::stringstream ss;
1345 // -----------------------------------------------------------------------------
1346 ss << "fmax_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1347 // -----------------------------------------------------------------------------
1348  return ss.str();
1349  }
1350 );
1351 
1352 // FCVT_S_D --------------------------------------------------------------------
1353 static InstructionDefinition fcvt_s_d_rd_rm_rs1 (
1354  ISA32_RV64IMACFD,
1355  "fcvt_s_d",
1356  (uint32_t) 0x40100053,
1357  (uint32_t) 0xfff0007f,
1358  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1359  {
1360 
1361 // -----------------------------------------------------------------------------
1362 
1363 // -----------------------------------------------------------------------------
1364 
1365 // -----------------------------------------------------------------------------
1366 etiss_uint8 rd = 0;
1367 static BitArrayRange R_rd_0(11, 7);
1368 rd += R_rd_0.read(ba) << 0;
1369 etiss_uint8 rm = 0;
1370 static BitArrayRange R_rm_0(14, 12);
1371 rm += R_rm_0.read(ba) << 0;
1372 etiss_uint8 rs1 = 0;
1373 static BitArrayRange R_rs1_0(19, 15);
1374 rs1 += R_rs1_0.read(ba) << 0;
1375 
1376 // -----------------------------------------------------------------------------
1377 
1378  {
1379  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1380 
1381  cp.code() = std::string("//FCVT_S_D\n");
1382 
1383 // -----------------------------------------------------------------------------
1384 { // block
1385 cp.code() += "{ // block\n";
1386 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1387 cp.code() += "} // block\n";
1388 } // block
1389 { // block
1390 cp.code() += "{ // block\n";
1391 cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
1392 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n";
1393 cp.code() += "} // block\n";
1394 } // block
1395 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1396 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1397 // -----------------------------------------------------------------------------
1398  cp.getAffectedRegisters().add("instructionPointer", 32);
1399  }
1400 
1401  return true;
1402  },
1403  0,
1404  [] (BitArray & ba, Instruction & instr)
1405  {
1406 // -----------------------------------------------------------------------------
1407 etiss_uint8 rd = 0;
1408 static BitArrayRange R_rd_0(11, 7);
1409 rd += R_rd_0.read(ba) << 0;
1410 etiss_uint8 rm = 0;
1411 static BitArrayRange R_rm_0(14, 12);
1412 rm += R_rm_0.read(ba) << 0;
1413 etiss_uint8 rs1 = 0;
1414 static BitArrayRange R_rs1_0(19, 15);
1415 rs1 += R_rs1_0.read(ba) << 0;
1416 
1417 // -----------------------------------------------------------------------------
1418 
1419  std::stringstream ss;
1420 // -----------------------------------------------------------------------------
1421 ss << "fcvt_s_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1422 // -----------------------------------------------------------------------------
1423  return ss.str();
1424  }
1425 );
1426 
1427 // FCVT_D_S --------------------------------------------------------------------
1428 static InstructionDefinition fcvt_d_s_rd_rm_rs1 (
1429  ISA32_RV64IMACFD,
1430  "fcvt_d_s",
1431  (uint32_t) 0x42000053,
1432  (uint32_t) 0xfff0007f,
1433  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1434  {
1435 
1436 // -----------------------------------------------------------------------------
1437 
1438 // -----------------------------------------------------------------------------
1439 
1440 // -----------------------------------------------------------------------------
1441 etiss_uint8 rd = 0;
1442 static BitArrayRange R_rd_0(11, 7);
1443 rd += R_rd_0.read(ba) << 0;
1444 etiss_uint8 rm = 0;
1445 static BitArrayRange R_rm_0(14, 12);
1446 rm += R_rm_0.read(ba) << 0;
1447 etiss_uint8 rs1 = 0;
1448 static BitArrayRange R_rs1_0(19, 15);
1449 rs1 += R_rs1_0.read(ba) << 0;
1450 
1451 // -----------------------------------------------------------------------------
1452 
1453  {
1454  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1455 
1456  cp.code() = std::string("//FCVT_D_S\n");
1457 
1458 // -----------------------------------------------------------------------------
1459 { // block
1460 cp.code() += "{ // block\n";
1461 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1462 cp.code() += "} // block\n";
1463 } // block
1464 { // block
1465 cp.code() += "{ // block\n";
1466 cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
1467 { // block
1468 cp.code() += "{ // block\n";
1469 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1470 cp.code() += "} // block\n";
1471 } // block
1472 cp.code() += "} // block\n";
1473 } // block
1474 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1475 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1476 // -----------------------------------------------------------------------------
1477  cp.getAffectedRegisters().add("instructionPointer", 32);
1478  }
1479 
1480  return true;
1481  },
1482  0,
1483  [] (BitArray & ba, Instruction & instr)
1484  {
1485 // -----------------------------------------------------------------------------
1486 etiss_uint8 rd = 0;
1487 static BitArrayRange R_rd_0(11, 7);
1488 rd += R_rd_0.read(ba) << 0;
1489 etiss_uint8 rm = 0;
1490 static BitArrayRange R_rm_0(14, 12);
1491 rm += R_rm_0.read(ba) << 0;
1492 etiss_uint8 rs1 = 0;
1493 static BitArrayRange R_rs1_0(19, 15);
1494 rs1 += R_rs1_0.read(ba) << 0;
1495 
1496 // -----------------------------------------------------------------------------
1497 
1498  std::stringstream ss;
1499 // -----------------------------------------------------------------------------
1500 ss << "fcvt_d_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1501 // -----------------------------------------------------------------------------
1502  return ss.str();
1503  }
1504 );
1505 
1506 // FEQ_D -----------------------------------------------------------------------
1507 static InstructionDefinition feq_d_rd_rs1_rs2 (
1508  ISA32_RV64IMACFD,
1509  "feq_d",
1510  (uint32_t) 0xa2002053,
1511  (uint32_t) 0xfe00707f,
1512  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1513  {
1514 
1515 // -----------------------------------------------------------------------------
1516 
1517 // -----------------------------------------------------------------------------
1518 
1519 // -----------------------------------------------------------------------------
1520 etiss_uint8 rd = 0;
1521 static BitArrayRange R_rd_0(11, 7);
1522 rd += R_rd_0.read(ba) << 0;
1523 etiss_uint8 rs1 = 0;
1524 static BitArrayRange R_rs1_0(19, 15);
1525 rs1 += R_rs1_0.read(ba) << 0;
1526 etiss_uint8 rs2 = 0;
1527 static BitArrayRange R_rs2_0(24, 20);
1528 rs2 += R_rs2_0.read(ba) << 0;
1529 
1530 // -----------------------------------------------------------------------------
1531 
1532  {
1533  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1534 
1535  cp.code() = std::string("//FEQ_D\n");
1536 
1537 // -----------------------------------------------------------------------------
1538 { // block
1539 cp.code() += "{ // block\n";
1540 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1541 cp.code() += "} // block\n";
1542 } // block
1543 { // block
1544 cp.code() += "{ // block\n";
1545 cp.code() += "etiss_uint64 res = 0LL;\n";
1546 cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0LL);\n";
1547 if ((rd % 32ULL) != 0LL) { // conditional
1548 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1549 } // conditional
1550 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1551 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1552 cp.code() += "} // block\n";
1553 } // block
1554 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1555 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1556 // -----------------------------------------------------------------------------
1557  cp.getAffectedRegisters().add("instructionPointer", 32);
1558  }
1559 
1560  return true;
1561  },
1562  0,
1563  [] (BitArray & ba, Instruction & instr)
1564  {
1565 // -----------------------------------------------------------------------------
1566 etiss_uint8 rd = 0;
1567 static BitArrayRange R_rd_0(11, 7);
1568 rd += R_rd_0.read(ba) << 0;
1569 etiss_uint8 rs1 = 0;
1570 static BitArrayRange R_rs1_0(19, 15);
1571 rs1 += R_rs1_0.read(ba) << 0;
1572 etiss_uint8 rs2 = 0;
1573 static BitArrayRange R_rs2_0(24, 20);
1574 rs2 += R_rs2_0.read(ba) << 0;
1575 
1576 // -----------------------------------------------------------------------------
1577 
1578  std::stringstream ss;
1579 // -----------------------------------------------------------------------------
1580 ss << "feq_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1581 // -----------------------------------------------------------------------------
1582  return ss.str();
1583  }
1584 );
1585 
1586 // FLT_D -----------------------------------------------------------------------
1587 static InstructionDefinition flt_d_rd_rs1_rs2 (
1588  ISA32_RV64IMACFD,
1589  "flt_d",
1590  (uint32_t) 0xa2001053,
1591  (uint32_t) 0xfe00707f,
1592  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1593  {
1594 
1595 // -----------------------------------------------------------------------------
1596 
1597 // -----------------------------------------------------------------------------
1598 
1599 // -----------------------------------------------------------------------------
1600 etiss_uint8 rd = 0;
1601 static BitArrayRange R_rd_0(11, 7);
1602 rd += R_rd_0.read(ba) << 0;
1603 etiss_uint8 rs1 = 0;
1604 static BitArrayRange R_rs1_0(19, 15);
1605 rs1 += R_rs1_0.read(ba) << 0;
1606 etiss_uint8 rs2 = 0;
1607 static BitArrayRange R_rs2_0(24, 20);
1608 rs2 += R_rs2_0.read(ba) << 0;
1609 
1610 // -----------------------------------------------------------------------------
1611 
1612  {
1613  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1614 
1615  cp.code() = std::string("//FLT_D\n");
1616 
1617 // -----------------------------------------------------------------------------
1618 { // block
1619 cp.code() += "{ // block\n";
1620 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1621 cp.code() += "} // block\n";
1622 } // block
1623 { // block
1624 cp.code() += "{ // block\n";
1625 cp.code() += "etiss_uint64 res = 0LL;\n";
1626 cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n";
1627 if ((rd % 32ULL) != 0LL) { // conditional
1628 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1629 } // conditional
1630 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1631 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1632 cp.code() += "} // block\n";
1633 } // block
1634 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1635 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1636 // -----------------------------------------------------------------------------
1637  cp.getAffectedRegisters().add("instructionPointer", 32);
1638  }
1639 
1640  return true;
1641  },
1642  0,
1643  [] (BitArray & ba, Instruction & instr)
1644  {
1645 // -----------------------------------------------------------------------------
1646 etiss_uint8 rd = 0;
1647 static BitArrayRange R_rd_0(11, 7);
1648 rd += R_rd_0.read(ba) << 0;
1649 etiss_uint8 rs1 = 0;
1650 static BitArrayRange R_rs1_0(19, 15);
1651 rs1 += R_rs1_0.read(ba) << 0;
1652 etiss_uint8 rs2 = 0;
1653 static BitArrayRange R_rs2_0(24, 20);
1654 rs2 += R_rs2_0.read(ba) << 0;
1655 
1656 // -----------------------------------------------------------------------------
1657 
1658  std::stringstream ss;
1659 // -----------------------------------------------------------------------------
1660 ss << "flt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1661 // -----------------------------------------------------------------------------
1662  return ss.str();
1663  }
1664 );
1665 
1666 // FLE_D -----------------------------------------------------------------------
1667 static InstructionDefinition fle_d_rd_rs1_rs2 (
1668  ISA32_RV64IMACFD,
1669  "fle_d",
1670  (uint32_t) 0xa2000053,
1671  (uint32_t) 0xfe00707f,
1672  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1673  {
1674 
1675 // -----------------------------------------------------------------------------
1676 
1677 // -----------------------------------------------------------------------------
1678 
1679 // -----------------------------------------------------------------------------
1680 etiss_uint8 rd = 0;
1681 static BitArrayRange R_rd_0(11, 7);
1682 rd += R_rd_0.read(ba) << 0;
1683 etiss_uint8 rs1 = 0;
1684 static BitArrayRange R_rs1_0(19, 15);
1685 rs1 += R_rs1_0.read(ba) << 0;
1686 etiss_uint8 rs2 = 0;
1687 static BitArrayRange R_rs2_0(24, 20);
1688 rs2 += R_rs2_0.read(ba) << 0;
1689 
1690 // -----------------------------------------------------------------------------
1691 
1692  {
1693  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1694 
1695  cp.code() = std::string("//FLE_D\n");
1696 
1697 // -----------------------------------------------------------------------------
1698 { // block
1699 cp.code() += "{ // block\n";
1700 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1701 cp.code() += "} // block\n";
1702 } // block
1703 { // block
1704 cp.code() += "{ // block\n";
1705 cp.code() += "etiss_uint64 res = 0LL;\n";
1706 cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n";
1707 if ((rd % 32ULL) != 0LL) { // conditional
1708 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1709 } // conditional
1710 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1711 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1712 cp.code() += "} // block\n";
1713 } // block
1714 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1715 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1716 // -----------------------------------------------------------------------------
1717  cp.getAffectedRegisters().add("instructionPointer", 32);
1718  }
1719 
1720  return true;
1721  },
1722  0,
1723  [] (BitArray & ba, Instruction & instr)
1724  {
1725 // -----------------------------------------------------------------------------
1726 etiss_uint8 rd = 0;
1727 static BitArrayRange R_rd_0(11, 7);
1728 rd += R_rd_0.read(ba) << 0;
1729 etiss_uint8 rs1 = 0;
1730 static BitArrayRange R_rs1_0(19, 15);
1731 rs1 += R_rs1_0.read(ba) << 0;
1732 etiss_uint8 rs2 = 0;
1733 static BitArrayRange R_rs2_0(24, 20);
1734 rs2 += R_rs2_0.read(ba) << 0;
1735 
1736 // -----------------------------------------------------------------------------
1737 
1738  std::stringstream ss;
1739 // -----------------------------------------------------------------------------
1740 ss << "fle_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1741 // -----------------------------------------------------------------------------
1742  return ss.str();
1743  }
1744 );
1745 
1746 // FCLASS_D --------------------------------------------------------------------
1747 static InstructionDefinition fclass_d_rd_rs1 (
1748  ISA32_RV64IMACFD,
1749  "fclass_d",
1750  (uint32_t) 0xe2001053,
1751  (uint32_t) 0xfff0707f,
1752  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1753  {
1754 
1755 // -----------------------------------------------------------------------------
1756 
1757 // -----------------------------------------------------------------------------
1758 
1759 // -----------------------------------------------------------------------------
1760 etiss_uint8 rd = 0;
1761 static BitArrayRange R_rd_0(11, 7);
1762 rd += R_rd_0.read(ba) << 0;
1763 etiss_uint8 rs1 = 0;
1764 static BitArrayRange R_rs1_0(19, 15);
1765 rs1 += R_rs1_0.read(ba) << 0;
1766 
1767 // -----------------------------------------------------------------------------
1768 
1769  {
1770  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1771 
1772  cp.code() = std::string("//FCLASS_D\n");
1773 
1774 // -----------------------------------------------------------------------------
1775 { // block
1776 cp.code() += "{ // block\n";
1777 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1778 cp.code() += "} // block\n";
1779 } // block
1780 { // block
1781 cp.code() += "{ // block\n";
1782 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
1783 cp.code() += "} // block\n";
1784 } // block
1785 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1786 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1787 // -----------------------------------------------------------------------------
1788  cp.getAffectedRegisters().add("instructionPointer", 32);
1789  }
1790 
1791  return true;
1792  },
1793  0,
1794  [] (BitArray & ba, Instruction & instr)
1795  {
1796 // -----------------------------------------------------------------------------
1797 etiss_uint8 rd = 0;
1798 static BitArrayRange R_rd_0(11, 7);
1799 rd += R_rd_0.read(ba) << 0;
1800 etiss_uint8 rs1 = 0;
1801 static BitArrayRange R_rs1_0(19, 15);
1802 rs1 += R_rs1_0.read(ba) << 0;
1803 
1804 // -----------------------------------------------------------------------------
1805 
1806  std::stringstream ss;
1807 // -----------------------------------------------------------------------------
1808 ss << "fclass_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
1809 // -----------------------------------------------------------------------------
1810  return ss.str();
1811  }
1812 );
1813 
1814 // FCVT_W_D --------------------------------------------------------------------
1815 static InstructionDefinition fcvt_w_d_rd_rm_rs1 (
1816  ISA32_RV64IMACFD,
1817  "fcvt_w_d",
1818  (uint32_t) 0xc2000053,
1819  (uint32_t) 0xfff0007f,
1820  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1821  {
1822 
1823 // -----------------------------------------------------------------------------
1824 
1825 // -----------------------------------------------------------------------------
1826 
1827 // -----------------------------------------------------------------------------
1828 etiss_uint8 rd = 0;
1829 static BitArrayRange R_rd_0(11, 7);
1830 rd += R_rd_0.read(ba) << 0;
1831 etiss_uint8 rm = 0;
1832 static BitArrayRange R_rm_0(14, 12);
1833 rm += R_rm_0.read(ba) << 0;
1834 etiss_uint8 rs1 = 0;
1835 static BitArrayRange R_rs1_0(19, 15);
1836 rs1 += R_rs1_0.read(ba) << 0;
1837 
1838 // -----------------------------------------------------------------------------
1839 
1840  {
1841  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1842 
1843  cp.code() = std::string("//FCVT_W_D\n");
1844 
1845 // -----------------------------------------------------------------------------
1846 { // block
1847 cp.code() += "{ // block\n";
1848 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1849 cp.code() += "} // block\n";
1850 } // block
1851 { // block
1852 cp.code() += "{ // block\n";
1853 cp.code() += "etiss_int32 res = 0LL;\n";
1854 cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0LL, " + std::to_string(rm) + "ULL);\n";
1855 if ((rd % 32ULL) != 0LL) { // conditional
1856 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1857 } // conditional
1858 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1859 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1860 cp.code() += "} // block\n";
1861 } // block
1862 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1863 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1864 // -----------------------------------------------------------------------------
1865  cp.getAffectedRegisters().add("instructionPointer", 32);
1866  }
1867 
1868  return true;
1869  },
1870  0,
1871  [] (BitArray & ba, Instruction & instr)
1872  {
1873 // -----------------------------------------------------------------------------
1874 etiss_uint8 rd = 0;
1875 static BitArrayRange R_rd_0(11, 7);
1876 rd += R_rd_0.read(ba) << 0;
1877 etiss_uint8 rm = 0;
1878 static BitArrayRange R_rm_0(14, 12);
1879 rm += R_rm_0.read(ba) << 0;
1880 etiss_uint8 rs1 = 0;
1881 static BitArrayRange R_rs1_0(19, 15);
1882 rs1 += R_rs1_0.read(ba) << 0;
1883 
1884 // -----------------------------------------------------------------------------
1885 
1886  std::stringstream ss;
1887 // -----------------------------------------------------------------------------
1888 ss << "fcvt_w_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1889 // -----------------------------------------------------------------------------
1890  return ss.str();
1891  }
1892 );
1893 
1894 // FCVT_WU_D -------------------------------------------------------------------
1895 static InstructionDefinition fcvt_wu_d_rd_rm_rs1 (
1896  ISA32_RV64IMACFD,
1897  "fcvt_wu_d",
1898  (uint32_t) 0xc2100053,
1899  (uint32_t) 0xfff0007f,
1900  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1901  {
1902 
1903 // -----------------------------------------------------------------------------
1904 
1905 // -----------------------------------------------------------------------------
1906 
1907 // -----------------------------------------------------------------------------
1908 etiss_uint8 rd = 0;
1909 static BitArrayRange R_rd_0(11, 7);
1910 rd += R_rd_0.read(ba) << 0;
1911 etiss_uint8 rm = 0;
1912 static BitArrayRange R_rm_0(14, 12);
1913 rm += R_rm_0.read(ba) << 0;
1914 etiss_uint8 rs1 = 0;
1915 static BitArrayRange R_rs1_0(19, 15);
1916 rs1 += R_rs1_0.read(ba) << 0;
1917 
1918 // -----------------------------------------------------------------------------
1919 
1920  {
1921  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1922 
1923  cp.code() = std::string("//FCVT_WU_D\n");
1924 
1925 // -----------------------------------------------------------------------------
1926 { // block
1927 cp.code() += "{ // block\n";
1928 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1929 cp.code() += "} // block\n";
1930 } // block
1931 { // block
1932 cp.code() += "{ // block\n";
1933 cp.code() += "etiss_uint32 res = 0LL;\n";
1934 cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n";
1935 if ((rd % 32ULL) != 0LL) { // conditional
1936 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
1937 } // conditional
1938 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1939 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1940 cp.code() += "} // block\n";
1941 } // block
1942 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1943 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1944 // -----------------------------------------------------------------------------
1945  cp.getAffectedRegisters().add("instructionPointer", 32);
1946  }
1947 
1948  return true;
1949  },
1950  0,
1951  [] (BitArray & ba, Instruction & instr)
1952  {
1953 // -----------------------------------------------------------------------------
1954 etiss_uint8 rd = 0;
1955 static BitArrayRange R_rd_0(11, 7);
1956 rd += R_rd_0.read(ba) << 0;
1957 etiss_uint8 rm = 0;
1958 static BitArrayRange R_rm_0(14, 12);
1959 rm += R_rm_0.read(ba) << 0;
1960 etiss_uint8 rs1 = 0;
1961 static BitArrayRange R_rs1_0(19, 15);
1962 rs1 += R_rs1_0.read(ba) << 0;
1963 
1964 // -----------------------------------------------------------------------------
1965 
1966  std::stringstream ss;
1967 // -----------------------------------------------------------------------------
1968 ss << "fcvt_wu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1969 // -----------------------------------------------------------------------------
1970  return ss.str();
1971  }
1972 );
1973 
1974 // FCVT_D_W --------------------------------------------------------------------
1975 static InstructionDefinition fcvt_d_w_rd_rm_rs1 (
1976  ISA32_RV64IMACFD,
1977  "fcvt_d_w",
1978  (uint32_t) 0xd2000053,
1979  (uint32_t) 0xfff0007f,
1980  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1981  {
1982 
1983 // -----------------------------------------------------------------------------
1984 
1985 // -----------------------------------------------------------------------------
1986 
1987 // -----------------------------------------------------------------------------
1988 etiss_uint8 rd = 0;
1989 static BitArrayRange R_rd_0(11, 7);
1990 rd += R_rd_0.read(ba) << 0;
1991 etiss_uint8 rm = 0;
1992 static BitArrayRange R_rm_0(14, 12);
1993 rm += R_rm_0.read(ba) << 0;
1994 etiss_uint8 rs1 = 0;
1995 static BitArrayRange R_rs1_0(19, 15);
1996 rs1 += R_rs1_0.read(ba) << 0;
1997 
1998 // -----------------------------------------------------------------------------
1999 
2000  {
2001  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2002 
2003  cp.code() = std::string("//FCVT_D_W\n");
2004 
2005 // -----------------------------------------------------------------------------
2006 { // block
2007 cp.code() += "{ // block\n";
2008 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2009 cp.code() += "} // block\n";
2010 } // block
2011 { // block
2012 cp.code() += "{ // block\n";
2013 cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
2014 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2015 cp.code() += "} // block\n";
2016 } // block
2017 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2018 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2019 // -----------------------------------------------------------------------------
2020  cp.getAffectedRegisters().add("instructionPointer", 32);
2021  }
2022 
2023  return true;
2024  },
2025  0,
2026  [] (BitArray & ba, Instruction & instr)
2027  {
2028 // -----------------------------------------------------------------------------
2029 etiss_uint8 rd = 0;
2030 static BitArrayRange R_rd_0(11, 7);
2031 rd += R_rd_0.read(ba) << 0;
2032 etiss_uint8 rm = 0;
2033 static BitArrayRange R_rm_0(14, 12);
2034 rm += R_rm_0.read(ba) << 0;
2035 etiss_uint8 rs1 = 0;
2036 static BitArrayRange R_rs1_0(19, 15);
2037 rs1 += R_rs1_0.read(ba) << 0;
2038 
2039 // -----------------------------------------------------------------------------
2040 
2041  std::stringstream ss;
2042 // -----------------------------------------------------------------------------
2043 ss << "fcvt_d_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2044 // -----------------------------------------------------------------------------
2045  return ss.str();
2046  }
2047 );
2048 
2049 // FCVT_D_WU -------------------------------------------------------------------
2050 static InstructionDefinition fcvt_d_wu_rd_rm_rs1 (
2051  ISA32_RV64IMACFD,
2052  "fcvt_d_wu",
2053  (uint32_t) 0xd2100053,
2054  (uint32_t) 0xfff0007f,
2055  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2056  {
2057 
2058 // -----------------------------------------------------------------------------
2059 
2060 // -----------------------------------------------------------------------------
2061 
2062 // -----------------------------------------------------------------------------
2063 etiss_uint8 rd = 0;
2064 static BitArrayRange R_rd_0(11, 7);
2065 rd += R_rd_0.read(ba) << 0;
2066 etiss_uint8 rm = 0;
2067 static BitArrayRange R_rm_0(14, 12);
2068 rm += R_rm_0.read(ba) << 0;
2069 etiss_uint8 rs1 = 0;
2070 static BitArrayRange R_rs1_0(19, 15);
2071 rs1 += R_rs1_0.read(ba) << 0;
2072 
2073 // -----------------------------------------------------------------------------
2074 
2075  {
2076  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2077 
2078  cp.code() = std::string("//FCVT_D_WU\n");
2079 
2080 // -----------------------------------------------------------------------------
2081 { // block
2082 cp.code() += "{ // block\n";
2083 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2084 cp.code() += "} // block\n";
2085 } // block
2086 { // block
2087 cp.code() += "{ // block\n";
2088 cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2089 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2090 cp.code() += "} // block\n";
2091 } // block
2092 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2093 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2094 // -----------------------------------------------------------------------------
2095  cp.getAffectedRegisters().add("instructionPointer", 32);
2096  }
2097 
2098  return true;
2099  },
2100  0,
2101  [] (BitArray & ba, Instruction & instr)
2102  {
2103 // -----------------------------------------------------------------------------
2104 etiss_uint8 rd = 0;
2105 static BitArrayRange R_rd_0(11, 7);
2106 rd += R_rd_0.read(ba) << 0;
2107 etiss_uint8 rm = 0;
2108 static BitArrayRange R_rm_0(14, 12);
2109 rm += R_rm_0.read(ba) << 0;
2110 etiss_uint8 rs1 = 0;
2111 static BitArrayRange R_rs1_0(19, 15);
2112 rs1 += R_rs1_0.read(ba) << 0;
2113 
2114 // -----------------------------------------------------------------------------
2115 
2116  std::stringstream ss;
2117 // -----------------------------------------------------------------------------
2118 ss << "fcvt_d_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2119 // -----------------------------------------------------------------------------
2120  return ss.str();
2121  }
2122 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fadd_d_rd_rm_rs1_rs2
static InstructionDefinition fadd_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fadd_d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
flt_d_rd_rs1_rs2
static InstructionDefinition flt_d_rd_rs1_rs2(ISA32_RV64IMACFD, "flt_d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 2ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fdiv_d_rd_rm_rs1_rs2
static InstructionDefinition fdiv_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fdiv_d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fle_d_rd_rs1_rs2
static InstructionDefinition fle_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fle_d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 1ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fnmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fnmadd_d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fcvt_d_w_rd_rm_rs1
static InstructionDefinition fcvt_d_w_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_W\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_w_d_rd_rm_rs1
static InstructionDefinition fcvt_w_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_w_d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 0LL, "+std::to_string(rm)+"ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_s_rd_rm_rs1
static InstructionDefinition fcvt_d_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), "+std::to_string(rm)+"ULL);\n";{ cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnjx_d_rd_rs1_rs2
static InstructionDefinition fsgnjx_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnjx_d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) & 9223372036854775808ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsub_d_rd_rm_rs1_rs2
static InstructionDefinition fsub_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fsub_d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_wu_d_rd_rm_rs1
static InstructionDefinition fcvt_wu_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_wu_d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="res = fcvt_64_32(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 1ULL, "+std::to_string(rm)+"ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmul_d_rd_rm_rs1_rs2
static InstructionDefinition fmul_d_rd_rm_rs1_rs2(ISA32_RV64IMACFD, "fmul_d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fmadd_d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fsqrt_d_rd_rm_rs1
static InstructionDefinition fsqrt_d_rd_rm_rs1(ISA32_RV64IMACFD, "fsqrt_d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fnmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fnmsub_d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmin_d_rd_rs1_rs2
static InstructionDefinition fmin_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fmin_d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 0LL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_d_wu_rd_rm_rs1
static InstructionDefinition fcvt_d_wu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_WU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_d_rd_rm_rs1
static InstructionDefinition fcvt_s_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL + res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnj_d_rd_rs1_rs2
static InstructionDefinition fsgnj_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnj_d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL)) << 63) | ((((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsd_imm_rs1_rs2
static InstructionDefinition fsd_imm_rs1_rs2(ISA32_RV64IMACFD, "fsd",(uint32_t) 0x003027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fld_rd_rs1_imm
static InstructionDefinition fld_rd_rs1_imm(ISA32_RV64IMACFD, "fld",(uint32_t) 0x003007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fsgnjn_d_rd_rs1_rs2
static InstructionDefinition fsgnjn_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fsgnjn_d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL))) << 63) | ((((((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmax_d_rd_rs1_rs2
static InstructionDefinition fmax_d_rd_rs1_rs2(ISA32_RV64IMACFD, "fmax_d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 1ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
feq_d_rd_rs1_rs2
static InstructionDefinition feq_d_rd_rs1_rs2(ISA32_RV64IMACFD, "feq_d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="res = fcmp_d(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 0LL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fclass_d_rd_rs1
static InstructionDefinition fclass_d_rd_rs1(ISA32_RV64IMACFD, "fclass_d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV64IMACFD, "fmsub_d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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