ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
MemoryDevice.cpp
Go to the documentation of this file.
1 /*
2 
3  @copyright
4 
5  <pre>
6 
7  Copyright 2018 Infineon Technologies AG
8 
9  This file is part of ETISS tool, see <https://github.com/tum-ei-eda/etiss>.
10 
11  The initial version of this software has been created with the funding support by the German Federal
12  Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.
13 
14  Redistribution and use in source and binary forms, with or without modification, are permitted
15  provided that the following conditions are met:
16 
17  1. Redistributions of source code must retain the above copyright notice, this list of conditions and
18  the following disclaimer.
19 
20  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
21  and the following disclaimer in the documentation and/or other materials provided with the distribution.
22 
23  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
24  or promote products derived from this software without specific prior written permission.
25 
26  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
27  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
28  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
29  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
32  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  POSSIBILITY OF SUCH DAMAGE.
34 
35  </pre>
36 
37  @author Chair of Electronic Design Automation, TUM
38 
39  @version 0.1
40 
41 */
42 
44 
45 namespace etiss
46 {
47 namespace plugin
48 {
49 
50 namespace
51 {
52 
54 {
55 
56  struct ETISS_System sys;
57 
59 
61 
62  bool (*fastrule)(uint64_t addr, unsigned len);
63 };
64 
65 bool empty_fastrule(uint64_t, unsigned)
66 {
67  return false; // pass through directly
68 }
69 
71 {
72  MapperSystem *lsys = ((MapperSystem *)handle);
73  if (lsys->fastrule(addr, length))
74  {
75  return lsys->this_->iread(lsys->orig, cpu, addr, length);
76  }
77  ETISS_System *sys = lsys->orig;
78  return sys->iread(sys->handle, cpu, addr, length);
79 }
81 {
82  MapperSystem *lsys = ((MapperSystem *)handle);
83  if (lsys->fastrule(addr, length))
84  {
85  return lsys->this_->iwrite(lsys->orig, cpu, addr, buffer, length);
86  }
87  ETISS_System *sys = lsys->orig;
88  return sys->iwrite(sys->handle, cpu, addr, buffer, length);
89 }
90 
92 {
93  MapperSystem *lsys = ((MapperSystem *)handle);
94  if (lsys->fastrule(addr, length))
95  {
96  return lsys->this_->dread(lsys->orig, cpu, addr, buffer, length);
97  }
98  ETISS_System *sys = lsys->orig;
99  return sys->dread(sys->handle, cpu, addr, buffer, length);
100 }
102 {
103  MapperSystem *lsys = ((MapperSystem *)handle);
104  if (lsys->fastrule(addr, length))
105  {
106  return lsys->this_->dwrite(lsys->orig, cpu, addr, buffer, length);
107  }
108  ETISS_System *sys = lsys->orig;
109  return sys->dwrite(sys->handle, cpu, addr, buffer, length);
110 }
111 
113 {
114  MapperSystem *lsys = ((MapperSystem *)handle);
115  if (lsys->fastrule(addr, length))
116  {
117  return lsys->this_->dbg_read(lsys->orig, addr, buffer, length);
118  }
119  ETISS_System *sys = lsys->orig;
120  return sys->dbg_read(sys->handle, addr, buffer, length);
121 }
122 
124 {
125  MapperSystem *lsys = ((MapperSystem *)handle);
126  if (lsys->fastrule(addr, length))
127  {
128  return lsys->this_->dbg_write(lsys->orig, addr, buffer, length);
129  }
130  ETISS_System *sys = lsys->orig;
131  return sys->dbg_write(sys->handle, addr, buffer, length);
132 }
133 
134 void syncTime_(void *handle, ETISS_CPU *cpu)
135 {
136  MapperSystem *lsys = ((MapperSystem *)handle);
137  ETISS_System *sys = lsys->orig;
138  sys->syncTime(sys->handle, cpu);
139 }
140 
141 } // namespace
142 
143 MemoryDeviceMapper::MemoryDeviceMapper(std::string name) : name_(name) {}
144 
146 
148 {
149  MapperSystem *ret = new MapperSystem();
150 
151  ret->sys.iread = &iread_;
152  ret->sys.iwrite = &iwrite_;
153  ret->sys.dread = &dread_;
154  ret->sys.dwrite = &dwrite_;
155  ret->sys.dbg_read = &dbg_read_;
156  ret->sys.dbg_write = &dbg_write_;
157  ret->sys.syncTime = &syncTime_;
158 
159  ret->sys.handle = (void *)ret;
160 
161  ret->this_ = this;
162 
163  ret->orig = system;
164 
165  ret->fastrule = &empty_fastrule;
166 
167  return (ETISS_System *)ret;
168 }
170 {
171  ETISS_System *ret = ((MapperSystem *)system)->orig;
172 
173  delete system;
174 
175  return ret;
176 }
177 
179 {
180  while (true)
181  {
182  unsigned nlen = len;
183  int index = map(true, true, false, addr, 0, len, nlen);
184  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
185  {
186  int32_t err = sys->iread(sys->handle, cpu, addr, len);
187  if (err)
188  return err;
189  }
190  else
191  {
192  int32_t err = devices_[index]->iread(cpu, addr, nlen);
193  if (err)
194  return err;
195  }
196  len = len - nlen;
197  if (len == 0)
198  return 0;
199  addr += nlen;
200  }
201 }
203  etiss::uint32 len)
204 {
205  while (true)
206  {
207  unsigned nlen = len;
208  int index = map(true, false, false, addr, buf, len, nlen);
209  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
210  {
211  int32_t err = sys->iwrite(sys->handle, cpu, addr, buf, len);
212  if (err)
213  return err;
214  }
215  else
216  {
217  int32_t err = devices_[index]->iwrite(cpu, addr, buf, nlen);
218  if (err)
219  return err;
220  }
221  len = len - nlen;
222  if (len == 0)
223  return 0;
224  buf += nlen;
225  addr += nlen;
226  }
227 }
229  etiss::uint32 len)
230 {
231  while (true)
232  {
233  unsigned nlen = len;
234  int index = map(false, true, false, addr, buf, len, nlen);
235  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
236  {
237  int32_t err = sys->dread(sys->handle, cpu, addr, buf, len);
238  if (err)
239  return err;
240  }
241  else
242  {
243  int32_t err = devices_[index]->dread(cpu, addr, buf, nlen);
244  if (err)
245  return err;
246  }
247  len = len - nlen;
248  if (len == 0)
249  return 0;
250  buf += nlen;
251  addr += nlen;
252  }
253 }
255  etiss::uint32 len)
256 {
257  while (true)
258  {
259  unsigned nlen = len;
260  int index = map(false, false, false, addr, buf, len, nlen);
261  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
262  {
263  int32_t err = sys->dwrite(sys->handle, cpu, addr, buf, len);
264  if (err)
265  return err;
266  }
267  else
268  {
269  int32_t err = devices_[index]->dwrite(cpu, addr, buf, nlen);
270  if (err)
271  return err;
272  }
273  len = len - nlen;
274  if (len == 0)
275  return 0;
276  buf += nlen;
277  addr += nlen;
278  }
279 }
281 {
282  while (true)
283  {
284  unsigned nlen = len;
285  int index = map(false, true, true, addr, buf, len, nlen);
286  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
287  {
288  int32_t err = sys->dbg_read(sys->handle, addr, buf, len);
289  if (err)
290  return err;
291  }
292  else
293  {
294  int32_t err = devices_[index]->dbg_read(addr, buf, nlen);
295  if (err)
296  return err;
297  }
298  len = len - nlen;
299  if (len == 0)
300  return 0;
301  buf += nlen;
302  addr += nlen;
303  }
304 }
306 {
307  while (true)
308  {
309  unsigned nlen = len;
310  int index = map(false, true, true, addr, buf, len, nlen);
311  if ((index < 0) || (index > (int)devices_.size()) || (devices_[index] == 0))
312  {
313  int32_t err = sys->dbg_write(sys->handle, addr, buf, len);
314  if (err)
315  return err;
316  }
317  else
318  {
319  int32_t err = devices_[index]->dbg_write(addr, buf, nlen);
320  if (err)
321  return err;
322  }
323  len = len - nlen;
324  if (len == 0)
325  return 0;
326  buf += nlen;
327  addr += nlen;
328  }
329 }
330 
331 int MemoryDeviceMapper::map(bool ibus, bool read, bool dbg, uint64_t addr, uint8_t *buf, unsigned len, unsigned &newlen)
332 {
333  for (unsigned i = 0; i < mountPoints_.size(); i++)
334  {
335  std::pair<uint64_t, uint64_t> &mp = mountPoints_[i];
336  if ((addr & mp.first) == mp.second)
337  return (int)i;
338  }
339  return -1;
340 }
341 
343 {
344  if (sys == 0)
345  return false;
346 
347  devices_.push_back(sys);
348  mountPoints_.push_back(std::make_pair(mask, addr));
349 
350  return true;
351 }
352 
353 } // namespace plugin
354 } // namespace etiss
etiss_uint8 uint8
Definition: 386-GCC.h:76
etiss_int32 int32
Definition: 386-GCC.h:81
etiss_uint32 uint32
Definition: 386-GCC.h:80
etiss_uint64 uint64
Definition: 386-GCC.h:82
static __inline__ uint64_t
Definition: arm_cde.h:31
static __inline__ int32_t
Definition: arm_mve.h:51
static __inline__ uint8_t
Definition: arm_mve.h:323
uint64_t etiss_uint64
Definition: types.h:96
uint32_t etiss_uint32
Definition: types.h:93
uint8_t etiss_uint8
Definition: types.h:87
int32_t etiss_int32
Definition: types.h:92
System Interface for the basic system IO operations and time synchronization.
Definition: System.h:77
std::vector< etiss::System * > devices_
Definition: MemoryDevice.h:78
etiss::int32 dread(ETISS_System *sys, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
etiss::int32 dbg_read(ETISS_System *sys, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
virtual int map(bool ibus, bool read, bool dbg, uint64_t addr, uint8_t *buf, unsigned len, unsigned &newlen)
virtual bool mount(etiss::System *sys, uint64_t mask, uint64_t addr)
virtual ETISS_System * unwrap(ETISS_CPU *cpu, ETISS_System *system)
undo wrap function call this function will be called AFTER etiss::Plugin::cleanup
etiss::int32 dbg_write(ETISS_System *sys, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
std::vector< std::pair< uint64_t, uint64_t > > mountPoints_
Definition: MemoryDevice.h:79
etiss::int32 iwrite(ETISS_System *sys, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
etiss::int32 iread(ETISS_System *sys, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint32 len)
etiss::int32 dwrite(ETISS_System *sys, ETISS_CPU *cpu, etiss::uint64 addr, etiss::uint8 *buf, etiss::uint32 len)
virtual ETISS_System * wrap(ETISS_CPU *cpu, ETISS_System *system)
change/wrap the passed system structure.
etiss_int32 dread_(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
etiss_int32 dbg_write_(void *handle, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
etiss_int32 iwrite_(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
etiss_int32 dbg_read_(void *handle, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
etiss_int32 iread_(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint32 length)
etiss_int32 dwrite_(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
void syncTime_(void *handle, ETISS_CPU *cpu)
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
float __ovld __cnfn length(float p)
Return the length of vector p, i.e., sqrt(p.x2 + p.y 2 + ...)
#define bool
Definition: stdbool.h:15
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:89
memory access and time synchronization functions.
Definition: System.h:78
etiss_int32(* dwrite)(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
write data
Definition: System.h:97
etiss_int32(* iread)(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint32 length)
used to simulate an instruction fetch.
Definition: System.h:84
void * handle
custom handle that will be passed to the functions of this structure
Definition: System.h:116
etiss_int32(* dbg_write)(void *handle, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
direct debug write
Definition: System.h:108
etiss_int32(* dbg_read)(void *handle, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
direct debug read
Definition: System.h:104
etiss_int32(* dread)(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
read data
Definition: System.h:93
void(* syncTime)(void *handle, ETISS_CPU *cpu)
called after a block to synchronize the time
Definition: System.h:114
etiss_int32(* iwrite)(void *handle, ETISS_CPU *cpu, etiss_uint64 addr, etiss_uint8 *buffer, etiss_uint32 length)
write instruction data over instruction bus
Definition: System.h:88