ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
Loading...
Searching...
No Matches
RV64IMACFD.h
Go to the documentation of this file.
1
7#ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
8#define ETISS_RV64IMACFDArch_RV64IMACFD_H_
9#include <stdio.h>
10#include "etiss/jit/CPU.h"
11
12#ifdef __cplusplus
13extern "C"
14{
15#endif
16#pragma pack(push, 1)
17 struct RV64IMACFD
18 {
19 ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure.
20 // This allows to cast X * to ETISS_CPU * and vice versa
53 etiss_uint64 *X[32];
88 etiss_uint64 *CSR[4096];
122 etiss_uint64 *F[32];
125 };
126
127#pragma pack(pop) // undo changes
128 // convenient use of X instead of struct X in generated C code
129 typedef struct RV64IMACFD RV64IMACFD;
130#ifdef __cplusplus
131} // extern "C"
132#endif
133#endif
uint64_t etiss_uint64
Definition types.h:58
uint8_t etiss_uint8
Definition types.h:49
basic cpu state structure needed for execution of any cpu architecture.
Definition CPU.h:51
Generated on Fri, 19 Jun 2026 08:11:16 +0000.
Definition RV64IMACFD.h:18
etiss_uint64 CYCLE
Definition RV64IMACFD.h:65
etiss_uint64 FRM
Definition RV64IMACFD.h:61
etiss_uint64 S8
Definition RV64IMACFD.h:45
etiss_uint64 FA6
Definition RV64IMACFD.h:106
etiss_uint64 A6
Definition RV64IMACFD.h:37
ETISS_CPU cpu
Definition RV64IMACFD.h:19
etiss_uint64 A1
Definition RV64IMACFD.h:32
etiss_uint64 FS3
Definition RV64IMACFD.h:109
etiss_uint64 MINSTRET
Definition RV64IMACFD.h:73
etiss_uint64 T1
Definition RV64IMACFD.h:27
etiss_uint64 FT3
Definition RV64IMACFD.h:93
etiss_uint64 INSTRET
Definition RV64IMACFD.h:71
etiss_uint64 INSTRETH
Definition RV64IMACFD.h:72
etiss_uint64 FS5
Definition RV64IMACFD.h:111
etiss_uint64 S2
Definition RV64IMACFD.h:39
etiss_uint64 MCAUSE
Definition RV64IMACFD.h:86
etiss_uint64 * F[32]
Definition RV64IMACFD.h:122
etiss_uint64 FENCE[8]
Definition RV64IMACFD.h:55
etiss_uint64 MINSTRETH
Definition RV64IMACFD.h:74
etiss_uint64 RES_ADDR
Definition RV64IMACFD.h:124
etiss_uint64 MTVEC
Definition RV64IMACFD.h:82
etiss_uint64 A5
Definition RV64IMACFD.h:36
etiss_uint64 MIP
Definition RV64IMACFD.h:64
etiss_uint64 ins_X[32]
Definition RV64IMACFD.h:54
etiss_uint8 PRIV
Definition RV64IMACFD.h:57
etiss_uint64 S1
Definition RV64IMACFD.h:30
etiss_uint64 MIE
Definition RV64IMACFD.h:63
etiss_uint64 FT0
Definition RV64IMACFD.h:90
etiss_uint64 MEPC
Definition RV64IMACFD.h:85
etiss_uint64 MEDELEG
Definition RV64IMACFD.h:80
etiss_uint64 ins_CSR[4096]
Definition RV64IMACFD.h:89
etiss_uint64 T2
Definition RV64IMACFD.h:28
etiss_uint64 S10
Definition RV64IMACFD.h:47
etiss_uint64 MARCHID
Definition RV64IMACFD.h:76
etiss_uint64 FS1
Definition RV64IMACFD.h:99
etiss_uint64 * CSR[4096]
Definition RV64IMACFD.h:88
etiss_uint64 RA
Definition RV64IMACFD.h:22
etiss_uint64 FS8
Definition RV64IMACFD.h:114
etiss_uint64 S6
Definition RV64IMACFD.h:43
etiss_uint64 MVENDORID
Definition RV64IMACFD.h:75
etiss_uint64 FA4
Definition RV64IMACFD.h:104
etiss_uint64 S0
Definition RV64IMACFD.h:29
etiss_uint64 S4
Definition RV64IMACFD.h:41
etiss_uint64 FS0
Definition RV64IMACFD.h:98
etiss_uint64 FS7
Definition RV64IMACFD.h:113
etiss_uint64 ins_F[32]
Definition RV64IMACFD.h:123
etiss_uint64 MTVAL
Definition RV64IMACFD.h:87
etiss_uint64 FFLAGS
Definition RV64IMACFD.h:60
etiss_uint64 FA7
Definition RV64IMACFD.h:107
etiss_uint64 TIME
Definition RV64IMACFD.h:69
etiss_uint64 T3
Definition RV64IMACFD.h:49
etiss_uint64 FT1
Definition RV64IMACFD.h:91
etiss_uint64 FS9
Definition RV64IMACFD.h:115
etiss_uint64 FT7
Definition RV64IMACFD.h:97
etiss_uint64 FS4
Definition RV64IMACFD.h:110
etiss_uint64 MIDELEG
Definition RV64IMACFD.h:81
etiss_uint64 MCYCLE
Definition RV64IMACFD.h:67
etiss_uint64 FCSR
Definition RV64IMACFD.h:59
etiss_uint64 FS10
Definition RV64IMACFD.h:116
etiss_uint64 S7
Definition RV64IMACFD.h:44
etiss_uint64 SP
Definition RV64IMACFD.h:23
etiss_uint64 A7
Definition RV64IMACFD.h:38
etiss_uint64 MCOUNTEREN
Definition RV64IMACFD.h:83
etiss_uint64 * X[32]
Definition RV64IMACFD.h:53
etiss_uint64 S3
Definition RV64IMACFD.h:40
etiss_uint64 FT4
Definition RV64IMACFD.h:94
etiss_uint64 FS11
Definition RV64IMACFD.h:117
etiss_uint64 TIMEH
Definition RV64IMACFD.h:70
etiss_uint64 A0
Definition RV64IMACFD.h:31
etiss_uint64 FA3
Definition RV64IMACFD.h:103
etiss_uint64 T6
Definition RV64IMACFD.h:52
etiss_uint64 MCYCLEH
Definition RV64IMACFD.h:68
etiss_uint64 ZERO
Definition RV64IMACFD.h:21
etiss_uint64 CYCLEH
Definition RV64IMACFD.h:66
etiss_uint8 RES[8]
Definition RV64IMACFD.h:56
etiss_uint64 TP
Definition RV64IMACFD.h:25
etiss_uint64 T0
Definition RV64IMACFD.h:26
etiss_uint64 MSCRATCH
Definition RV64IMACFD.h:84
etiss_uint64 FS2
Definition RV64IMACFD.h:108
etiss_uint64 A3
Definition RV64IMACFD.h:34
etiss_uint64 FA5
Definition RV64IMACFD.h:105
etiss_uint64 S5
Definition RV64IMACFD.h:42
etiss_uint64 FT10
Definition RV64IMACFD.h:120
etiss_uint64 MISA
Definition RV64IMACFD.h:79
etiss_uint64 FT8
Definition RV64IMACFD.h:118
etiss_uint64 A2
Definition RV64IMACFD.h:33
etiss_uint64 T5
Definition RV64IMACFD.h:51
etiss_uint64 FA1
Definition RV64IMACFD.h:101
etiss_uint64 GP
Definition RV64IMACFD.h:24
etiss_uint64 MSTATUS
Definition RV64IMACFD.h:62
etiss_uint64 FA0
Definition RV64IMACFD.h:100
etiss_uint64 MHARTID
Definition RV64IMACFD.h:78
etiss_uint64 A4
Definition RV64IMACFD.h:35
etiss_uint64 FT5
Definition RV64IMACFD.h:95
etiss_uint64 S9
Definition RV64IMACFD.h:46
etiss_uint64 MIMPID
Definition RV64IMACFD.h:77
etiss_uint64 FT2
Definition RV64IMACFD.h:92
etiss_uint64 S11
Definition RV64IMACFD.h:48
etiss_uint64 FT6
Definition RV64IMACFD.h:96
etiss_uint64 FA2
Definition RV64IMACFD.h:102
etiss_uint64 FT11
Definition RV64IMACFD.h:121
etiss_uint64 T4
Definition RV64IMACFD.h:50
etiss_uint64 FT9
Definition RV64IMACFD.h:119
etiss_uint64 FS6
Definition RV64IMACFD.h:112
etiss_uint64 DPC
Definition RV64IMACFD.h:58