connects a wishbone bus interface implemented with the variables of WishboneSignalMap to a ETISS_System structure. More...

#include <Wishbone.h>

Inheritance diagram for etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >:

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Collaboration diagram for etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >:

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Public Member Functions
	WishboneBus (WishboneSignalMap< BOOLSIG, VECTORSIG > &sigs, ETISS_System &system, ETISS_CPU &cpu, etiss::CPUCore &core)
	Constructor. More...

void	init ()
	Initiate all bus output signals and set pending status to "nothing pending". More...

etiss_int32	update (uint64_t time, bool premain, bool reset, bool posSimTime=true)
	Update signals to CPU or read/write from/to bus. More...

Public Member Functions inherited from etiss::interfaces::Delegate
	Delegate (ETISS_System &system, ETISS_CPU &cpu)

void	syncTime (uint64_t time_ps)

etiss::int32	read (bool ibus, uint64_t &time_ps, uint64_t addr, uint8_t *buf, unsigned len)
	handles read operations. More...

etiss::int32	write (bool ibus, uint64_t &time_ps, uint64_t addr, uint8_t *buf, unsigned len)
	handles write operations. More...

Public Attributes
WishboneSignalMap< BOOLSIG, VECTORSIG > &	sigs
	Signals between bus and CPU. More...

Public Attributes inherited from etiss::interfaces::Delegate
std::function< etiss::int32(bool, uint64_t &, uint64_t, uint8_t *, unsigned, bool &, bool &)>	injectedRead
	if valid then this function will be called by read() instead of performing any action itself More...

std::function< etiss::int32(bool, uint64_t &, uint64_t, uint8_t *, unsigned, bool &, bool &)>	redirectedWrite

std::function< void(bool injected, const uint64_t &time_ps, uint64_t addr, const uint8_t *buf, unsigned len)>	snoopRead

Private Member Functions
void	flipEndianness (uint8_t *buf)
	Flips endianess of a VECTORSIG. More...

bool	sel2Length (uint32_t sel, unsigned &length, unsigned &addressOffset)
	Calculates length and offset out of signal sel. More...

Private Attributes
etiss::CPUCore &	core_

uint64_t	lastutime
	time of last signal evaluation phase More...

uint64_t	etime

bool	lastclock
	used for determining clock edge More...

bool	useposclkedge
	use positive or negative clock edge More...

VECTORSIGSTORAGETYPE	dat_o
	buffer for data out to CPU More...

bool	po_err
	bus error arised More...

unsigned	pending
	0: nothing pending; 1: Read pending; 2: Write pending More...

Detailed Description

template<typename BOOLSIG, typename VECTORSIG, bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>
class etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >

connects a wishbone bus interface implemented with the variables of WishboneSignalMap to a ETISS_System structure.

the template parameter instrBus defined is the iread/iwrite or dread/dwrite functions are used (-> instruction bus or data bus)

Definition at line 178 of file Wishbone.h.

Constructor & Destructor Documentation

◆ WishboneBus()

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::WishboneBus	(	WishboneSignalMap< BOOLSIG, VECTORSIG > &	sigs,
		ETISS_System &	system,
		ETISS_CPU &	cpu,
		etiss::CPUCore &	core
	)

inline

Constructor.

Parameters

sigs	Signals between bus and CPU
system	Underlying ETISS system for accessing external bus
cpu	ETISS CPU state

Definition at line 189 of file Wishbone.h.

Member Function Documentation

◆ flipEndianness()

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

void etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::flipEndianness ( uint8_t * buf )

inlineprivate

Flips endianess of a VECTORSIG.

Definition at line 370 of file Wishbone.h.

References swap().

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◆ init()

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

void etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::init ( )

inline

Initiate all bus output signals and set pending status to "nothing pending".

Definition at line 204 of file Wishbone.h.

◆ sel2Length()

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

bool etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::sel2Length	(	uint32_t	sel,
		unsigned &	length,
		unsigned &	addressOffset
	)

inlineprivate

Calculates length and offset out of signal sel.

Parameters

[in]	sel	Select signal
[out]	length	Number of Bytes to read/write
[in]	addressOffset	Offset on the aligned address (is proved in this function)

Returns: Select signal was valid

Definition at line 388 of file Wishbone.h.

References length(), etiss::log(), and etiss::WARNING.

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◆ update()

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

etiss_int32 etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::update	(	uint64_t	time,
		bool	premain,
		bool	reset,
		bool	posSimTime = `true`
	)

inline

Update signals to CPU or read/write from/to bus.

Has to different tasks depending on parameter premain: In the premain phase all signals are updated on the CPU side. Otherwise the signals are evaluated for bus access and a read or write access can be fulfilled.

Parameters

time	Actual simulation time
premain	Determines premain phase
reset	Determines if CPU sends reset signal
posSimTime	If true, time is checked if it has elapsed

Definition at line 223 of file Wishbone.h.

References bool, etiss::ERROR, etiss_log, etiss::FATALERROR, etiss::interfaces::getAddr(), etiss::interfaces::getBool(), etiss::interfaces::getSel(), etiss::py::init(), etiss::log(), etiss::mm::NOERROR, etiss::interfaces::setBool(), uint64_t, and uint8_t.

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Member Data Documentation

◆ core_

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

etiss::CPUCore& etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::core_

private

Definition at line 440 of file Wishbone.h.

◆ dat_o

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

VECTORSIGSTORAGETYPE etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::dat_o

private

buffer for data out to CPU

Definition at line 445 of file Wishbone.h.

◆ etime

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

uint64_t etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::etime

private

Definition at line 442 of file Wishbone.h.

◆ lastclock

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

bool etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::lastclock

private

used for determining clock edge

Definition at line 443 of file Wishbone.h.

◆ lastutime

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

uint64_t etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::lastutime

private

time of last signal evaluation phase

Definition at line 441 of file Wishbone.h.

◆ pending

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

unsigned etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::pending

private

0: nothing pending; 1: Read pending; 2: Write pending

Definition at line 447 of file Wishbone.h.

◆ po_err

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

bool etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::po_err

private

bus error arised

Definition at line 446 of file Wishbone.h.

◆ sigs

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

WishboneSignalMap<BOOLSIG, VECTORSIG>& etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::sigs

Signals between bus and CPU.

Definition at line 437 of file Wishbone.h.

◆ useposclkedge

template<typename BOOLSIG , typename VECTORSIG , bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>

bool etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >::useposclkedge

private

use positive or negative clock edge

Definition at line 444 of file Wishbone.h.

The documentation for this class was generated from the following file:

/home/runner/work/etiss/etiss/include/etiss/interfaces/Wishbone.h

Public Member Functions

Public Attributes

Private Member Functions

Private Attributes

Detailed Description

template<typename BOOLSIG, typename VECTORSIG, bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG> class etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >

Constructor & Destructor Documentation

◆ WishboneBus()

Member Function Documentation

◆ flipEndianness()

◆ init()

◆ sel2Length()

◆ update()

Member Data Documentation

◆ core_

◆ dat_o

◆ etime

◆ lastclock

◆ lastutime

◆ pending

◆ po_err

◆ sigs

◆ useposclkedge

template<typename BOOLSIG, typename VECTORSIG, bool instrBus, bool flipEndianess, unsigned bytewidth = sizeof(VECTORSIG), typename VECTORSIGSTORAGETYPE = VECTORSIG>
class etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE >