| core_ | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| cpu | etiss::interfaces::Delegate | private |
| dat_o | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| Delegate(ETISS_System &system, ETISS_CPU &cpu) | etiss::interfaces::Delegate | |
| etime | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| flipEndianness(uint8_t *buf) | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | inlineprivate |
| init() | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | inline |
| injectedRead | etiss::interfaces::Delegate | |
| lastclock | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| lastutime | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| pending | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| po_err | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| read(bool ibus, uint64_t &time_ps, uint64_t addr, uint8_t *buf, unsigned len) | etiss::interfaces::Delegate | |
| redirectedWrite | etiss::interfaces::Delegate | |
| sel2Length(uint32_t sel, unsigned &length, unsigned &addressOffset) | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | inlineprivate |
| sigs | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | |
| snoopRead | etiss::interfaces::Delegate | |
| syncTime(uint64_t time_ps) | etiss::interfaces::Delegate | |
| system | etiss::interfaces::Delegate | private |
| update(uint64_t time, bool premain, bool reset, bool posSimTime=true) | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | inline |
| useposclkedge | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | private |
| WishboneBus(WishboneSignalMap< BOOLSIG, VECTORSIG > &sigs, ETISS_System &system, ETISS_CPU &cpu, etiss::CPUCore &core) | etiss::interfaces::WishboneBus< BOOLSIG, VECTORSIG, instrBus, flipEndianess, bytewidth, VECTORSIGSTORAGETYPE > | inline |
| write(bool ibus, uint64_t &time_ps, uint64_t addr, uint8_t *buf, unsigned len) | etiss::interfaces::Delegate | |
