32imm += R_imm_0.
read(ba) << 0;
35rs1 += R_rs1_0.
read(ba) << 0;
37imm += R_imm_5.
read(ba) << 5;
45 cp.
code() = std::string(
"//CADDIW\n");
48cp.
code() +=
"etiss_coverage_count(1, 206);\n";
50cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
51cp.
code() +=
"{ // block\n";
53cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
54cp.
code() +=
"} // block\n";
56cp.
code() +=
"etiss_coverage_count(1, 8096);\n";
57if ((rs1 % 32ULL) != 0LL) {
58cp.
code() +=
"etiss_coverage_count(5, 8102, 8099, 8097, 8100, 8101);\n";
59cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL]) + " + std::to_string(((
etiss_int8)(((
etiss_int8)imm) << (2)) >> (2))) +
"LL;\n";
60cp.
code() +=
"etiss_coverage_count(11, 8119, 8107, 8106, 8104, 8118, 8114, 8112, 8111, 8109, 8117, 8115);\n";
63cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
76imm += R_imm_0.read(ba) << 0;
79rs1 += R_rs1_0.read(ba) << 0;
81imm += R_imm_5.read(ba) << 5;
87ss <<
"caddiw" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rs1=" + std::to_string(rs1) +
"]");
110nzuimm += R_nzuimm_0.
read(ba) << 0;
113rs1 += R_rs1_0.
read(ba) << 0;
115nzuimm += R_nzuimm_5.
read(ba) << 5;
123 cp.
code() = std::string(
"//CSRLI\n");
126cp.
code() +=
"etiss_coverage_count(1, 199);\n";
128cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
129cp.
code() +=
"{ // block\n";
131cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
132cp.
code() +=
"} // block\n";
135cp.
code() +=
"etiss_coverage_count(1, 7957);\n";
136cp.
code() +=
"{ // block\n";
137cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] >> " + std::to_string(nzuimm) +
"ULL;\n";
138cp.
code() +=
"etiss_coverage_count(11, 7956, 7948, 7947, 7945, 7946, 7955, 7953, 7952, 7950, 7951, 7954);\n";
139cp.
code() +=
"} // block\n";
142cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
155nzuimm += R_nzuimm_0.read(ba) << 0;
158rs1 += R_rs1_0.read(ba) << 0;
160nzuimm += R_nzuimm_5.read(ba) << 5;
164 std::stringstream ss;
166ss <<
"csrli" <<
" # " << ba << (
" [nzuimm=" + std::to_string(nzuimm) +
" | rs1=" + std::to_string(rs1) +
"]");
189shamt += R_shamt_0.
read(ba) << 0;
192rs1 += R_rs1_0.
read(ba) << 0;
194shamt += R_shamt_5.
read(ba) << 5;
202 cp.
code() = std::string(
"//CSRAI\n");
205cp.
code() +=
"etiss_coverage_count(1, 200);\n";
207cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
208cp.
code() +=
"{ // block\n";
210cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
211cp.
code() +=
"} // block\n";
214cp.
code() +=
"etiss_coverage_count(1, 7974);\n";
215cp.
code() +=
"{ // block\n";
216cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL])) >> " + std::to_string(shamt) +
"ULL;\n";
217cp.
code() +=
"etiss_coverage_count(13, 7973, 7962, 7961, 7959, 7960, 7972, 7969, 7967, 7966, 7964, 7965, 7970, 7971);\n";
218cp.
code() +=
"} // block\n";
221cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
234shamt += R_shamt_0.read(ba) << 0;
237rs1 += R_rs1_0.read(ba) << 0;
239shamt += R_shamt_5.read(ba) << 5;
243 std::stringstream ss;
245ss <<
"csrai" <<
" # " << ba << (
" [shamt=" + std::to_string(shamt) +
" | rs1=" + std::to_string(rs1) +
"]");
268shamt += R_shamt_0.
read(ba) << 0;
271rs1 += R_rs1_0.
read(ba) << 0;
273shamt += R_shamt_5.
read(ba) << 5;
281 cp.
code() = std::string(
"//CSLLI\n");
284cp.
code() +=
"etiss_coverage_count(1, 201);\n";
286cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
287cp.
code() +=
"{ // block\n";
289cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
290cp.
code() +=
"} // block\n";
293cp.
code() +=
"etiss_coverage_count(1, 7991);\n";
294cp.
code() +=
"{ // block\n";
295cp.
code() +=
"etiss_coverage_count(1, 7975);\n";
297cp.
code() +=
"etiss_coverage_count(3, 7978, 7976, 7977);\n";
299cp.
code() +=
"{ // procedure\n";
300cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
301cp.
code() +=
"etiss_coverage_count(2, 7981, 7979);\n";
303cp.
code() +=
"} // procedure\n";
306cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) +
"ULL] << " + std::to_string(shamt) +
"ULL;\n";
307cp.
code() +=
"etiss_coverage_count(7, 7990, 7984, 7983, 7989, 7987, 7986, 7988);\n";
308cp.
code() +=
"} // block\n";
311cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
318 cp.
code() = std::string(
"//CSLLI\n");
321cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
333shamt += R_shamt_0.read(ba) << 0;
336rs1 += R_rs1_0.read(ba) << 0;
338shamt += R_shamt_5.read(ba) << 5;
342 std::stringstream ss;
344ss <<
"cslli" <<
" # " << ba << (
" [shamt=" + std::to_string(shamt) +
" | rs1=" + std::to_string(rs1) +
"]");
367rd += R_rd_0.
read(ba) << 0;
370uimm += R_uimm_6.
read(ba) << 6;
373rs1 += R_rs1_0.
read(ba) << 0;
375uimm += R_uimm_3.
read(ba) << 3;
383 cp.
code() = std::string(
"//CLD\n");
386cp.
code() +=
"etiss_coverage_count(1, 202);\n";
388cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
389cp.
code() +=
"{ // block\n";
391cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
392cp.
code() +=
"} // block\n";
395cp.
code() +=
"etiss_coverage_count(1, 8015);\n";
396cp.
code() +=
"{ // block\n";
397cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
398cp.
code() +=
"etiss_coverage_count(7, 8000, 7999, 7997, 7996, 7994, 7995, 7998);\n";
399cp.
code() +=
"etiss_uint64 mem_val_0;\n";
400cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
401cp.
code() +=
"if (cpu->exception) { // conditional\n";
403cp.
code() +=
"{ // procedure\n";
404cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
406cp.
code() +=
"} // procedure\n";
408cp.
code() +=
"} // conditional\n";
409cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = (etiss_int64)(mem_val_0);\n";
410cp.
code() +=
"etiss_coverage_count(10, 8014, 8005, 8004, 8002, 8003, 8013, 8011, 8009, 8007, 8008);\n";
411cp.
code() +=
"} // block\n";
414cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
421 cp.
code() = std::string(
"//CLD\n");
424cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
436rd += R_rd_0.read(ba) << 0;
439uimm += R_uimm_6.read(ba) << 6;
442rs1 += R_rs1_0.read(ba) << 0;
444uimm += R_uimm_3.read(ba) << 3;
448 std::stringstream ss;
450ss <<
"cld" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
473rs2 += R_rs2_0.
read(ba) << 0;
476uimm += R_uimm_6.
read(ba) << 6;
479rs1 += R_rs1_0.
read(ba) << 0;
481uimm += R_uimm_3.
read(ba) << 3;
489 cp.
code() = std::string(
"//CSD\n");
492cp.
code() +=
"etiss_coverage_count(1, 203);\n";
494cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
495cp.
code() +=
"{ // block\n";
497cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
498cp.
code() +=
"} // block\n";
501cp.
code() +=
"etiss_coverage_count(1, 8039);\n";
502cp.
code() +=
"{ // block\n";
503cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
504cp.
code() +=
"etiss_coverage_count(7, 8024, 8023, 8021, 8020, 8018, 8019, 8022);\n";
505cp.
code() +=
"etiss_uint64 mem_val_0;\n";
506cp.
code() +=
"mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL]);\n";
507cp.
code() +=
"etiss_coverage_count(10, 8038, 8030, 8028, 8026, 8027, 8037, 8035, 8034, 8032, 8033);\n";
508cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
509cp.
code() +=
"if (cpu->exception) { // conditional\n";
511cp.
code() +=
"{ // procedure\n";
512cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
514cp.
code() +=
"} // procedure\n";
516cp.
code() +=
"} // conditional\n";
517cp.
code() +=
"} // block\n";
520cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
527 cp.
code() = std::string(
"//CSD\n");
530cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
542rs2 += R_rs2_0.read(ba) << 0;
545uimm += R_uimm_6.read(ba) << 6;
548rs1 += R_rs1_0.read(ba) << 0;
550uimm += R_uimm_3.read(ba) << 3;
554 std::stringstream ss;
556ss <<
"csd" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
579rs2 += R_rs2_0.
read(ba) << 0;
582rd += R_rd_0.
read(ba) << 0;
590 cp.
code() = std::string(
"//CSUBW\n");
593cp.
code() +=
"etiss_coverage_count(1, 204);\n";
595cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
596cp.
code() +=
"{ // block\n";
598cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
599cp.
code() +=
"} // block\n";
602cp.
code() +=
"etiss_coverage_count(1, 8067);\n";
603cp.
code() +=
"{ // block\n";
604cp.
code() +=
"etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL]);\n";
605cp.
code() +=
"etiss_coverage_count(12, 8056, 8055, 8047, 8045, 8044, 8042, 8043, 8054, 8052, 8051, 8049, 8050);\n";
606cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = (etiss_uint64)((etiss_int32)(res));\n";
607cp.
code() +=
"etiss_coverage_count(8, 8066, 8061, 8060, 8058, 8059, 8065, 8063, 8062);\n";
608cp.
code() +=
"} // block\n";
611cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
624rs2 += R_rs2_0.read(ba) << 0;
627rd += R_rd_0.read(ba) << 0;
631 std::stringstream ss;
633ss <<
"csubw" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
656rs2 += R_rs2_0.
read(ba) << 0;
659rd += R_rd_0.
read(ba) << 0;
667 cp.
code() = std::string(
"//CADDW\n");
670cp.
code() +=
"etiss_coverage_count(1, 205);\n";
672cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
673cp.
code() +=
"{ // block\n";
675cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
676cp.
code() +=
"} // block\n";
679cp.
code() +=
"etiss_coverage_count(1, 8095);\n";
680cp.
code() +=
"{ // block\n";
681cp.
code() +=
"etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL]);\n";
682cp.
code() +=
"etiss_coverage_count(12, 8084, 8083, 8075, 8073, 8072, 8070, 8071, 8082, 8080, 8079, 8077, 8078);\n";
683cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = (etiss_uint64)((etiss_int32)(res));\n";
684cp.
code() +=
"etiss_coverage_count(8, 8094, 8089, 8088, 8086, 8087, 8093, 8091, 8090);\n";
685cp.
code() +=
"} // block\n";
688cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
701rs2 += R_rs2_0.read(ba) << 0;
704rd += R_rd_0.read(ba) << 0;
708 std::stringstream ss;
710ss <<
"caddw" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
733uimm += R_uimm_6.
read(ba) << 6;
735uimm += R_uimm_3.
read(ba) << 3;
738rd += R_rd_0.
read(ba) << 0;
740uimm += R_uimm_5.
read(ba) << 5;
748 cp.
code() = std::string(
"//CLDSP\n");
751cp.
code() +=
"etiss_coverage_count(1, 207);\n";
753cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
754cp.
code() +=
"{ // block\n";
756cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
757cp.
code() +=
"} // block\n";
760cp.
code() +=
"etiss_coverage_count(1, 8149);\n";
761cp.
code() +=
"{ // block\n";
762cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL;\n";
763cp.
code() +=
"etiss_coverage_count(5, 8126, 8125, 8123, 8122, 8124);\n";
764cp.
code() +=
"etiss_uint64 mem_val_0;\n";
765cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
766cp.
code() +=
"if (cpu->exception) { // conditional\n";
768cp.
code() +=
"{ // procedure\n";
769cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
771cp.
code() +=
"} // procedure\n";
773cp.
code() +=
"} // conditional\n";
774cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
775cp.
code() +=
"etiss_coverage_count(5, 8134, 8133, 8131, 8129, 8130);\n";
776cp.
code() +=
"etiss_coverage_count(1, 8135);\n";
778cp.
code() +=
"etiss_coverage_count(2, 8138, 8136);\n";
779cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
780cp.
code() +=
"etiss_coverage_count(5, 8145, 8143, 8142, 8140, 8144);\n";
784cp.
code() +=
"{ // procedure\n";
785cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
786cp.
code() +=
"etiss_coverage_count(3, 8148, 8146, 8147);\n";
788cp.
code() +=
"} // procedure\n";
791cp.
code() +=
"} // block\n";
794cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
801 cp.
code() = std::string(
"//CLDSP\n");
804cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
816uimm += R_uimm_6.read(ba) << 6;
818uimm += R_uimm_3.read(ba) << 3;
821rd += R_rd_0.read(ba) << 0;
823uimm += R_uimm_5.read(ba) << 5;
827 std::stringstream ss;
829ss <<
"cldsp" <<
" # " << ba << (
" [uimm=" + std::to_string(uimm) +
" | rd=" + std::to_string(rd) +
"]");
852rs2 += R_rs2_0.
read(ba) << 0;
855uimm += R_uimm_6.
read(ba) << 6;
857uimm += R_uimm_3.
read(ba) << 3;
865 cp.
code() = std::string(
"//CSDSP\n");
868cp.
code() +=
"etiss_coverage_count(1, 208);\n";
870cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
871cp.
code() +=
"{ // block\n";
873cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
874cp.
code() +=
"} // block\n";
877cp.
code() +=
"etiss_coverage_count(1, 8171);\n";
878cp.
code() +=
"{ // block\n";
879cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL;\n";
880cp.
code() +=
"etiss_coverage_count(5, 8156, 8155, 8153, 8152, 8154);\n";
881cp.
code() +=
"etiss_uint64 mem_val_0;\n";
882cp.
code() +=
"mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
883cp.
code() +=
"etiss_coverage_count(9, 8170, 8162, 8160, 8158, 8159, 8169, 8167, 8166, 8164);\n";
884cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
885cp.
code() +=
"if (cpu->exception) { // conditional\n";
887cp.
code() +=
"{ // procedure\n";
888cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
890cp.
code() +=
"} // procedure\n";
892cp.
code() +=
"} // conditional\n";
893cp.
code() +=
"} // block\n";
896cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
903 cp.
code() = std::string(
"//CSDSP\n");
906cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
918rs2 += R_rs2_0.read(ba) << 0;
921uimm += R_uimm_6.read(ba) << 6;
923uimm += R_uimm_3.read(ba) << 3;
927 std::stringstream ss;
929ss <<
"csdsp" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
"]");
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
static InstructionDefinition csdsp_rs2_uimm(ISA16_RV64IMACFD, "csdsp",(uint64_t) 0xe002,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSDSP\n");cp.code()+="etiss_coverage_count(1, 208);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8171);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 8156, 8155, 8153, 8152, 8154);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(9, 8170, 8162, 8160, 8158, 8159, 8169, 8167, 8166, 8164);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
static InstructionDefinition csd_rs2_uimm_rs1(ISA16_RV64IMACFD, "csd",(uint64_t) 0xe000,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSD\n");cp.code()+="etiss_coverage_count(1, 203);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8039);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 8024, 8023, 8021, 8020, 8018, 8019, 8022);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 8038, 8030, 8028, 8026, 8027, 8037, 8035, 8034, 8032, 8033);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition csubw_rs2_rd(ISA16_RV64IMACFD, "csubw",(uint64_t) 0x9c01,(uint64_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUBW\n");cp.code()+="etiss_coverage_count(1, 204);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8067);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 8056, 8055, 8047, 8045, 8044, 8042, 8043, 8054, 8052, 8051, 8049, 8050);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(8, 8066, 8061, 8060, 8058, 8059, 8065, 8063, 8062);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csubw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition caddw_rs2_rd(ISA16_RV64IMACFD, "caddw",(uint64_t) 0x9c21,(uint64_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDW\n");cp.code()+="etiss_coverage_count(1, 205);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8095);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 8084, 8083, 8075, 8073, 8072, 8070, 8071, 8082, 8080, 8079, 8077, 8078);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(8, 8094, 8089, 8088, 8086, 8087, 8093, 8091, 8090);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "caddw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition cldsp_uimm_rd(ISA16_RV64IMACFD, "cldsp",(uint64_t) 0x6002,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLDSP\n");cp.code()+="etiss_coverage_count(1, 207);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8149);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 8126, 8125, 8123, 8122, 8124);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 8134, 8133, 8131, 8129, 8130);\n";cp.code()+="etiss_coverage_count(1, 8135);\n";if(rd % 32ULL) { cp.code()+="etiss_coverage_count(2, 8138, 8136);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8145, 8143, 8142, 8140, 8144);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 8148, 8146, 8147);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition csrai_shamt_rs1(ISA16_RV64IMACFD, "csrai",(uint64_t) 0x8401,(uint64_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");cp.code()+="etiss_coverage_count(1, 200);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7974);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(13, 7973, 7962, 7961, 7959, 7960, 7972, 7969, 7967, 7966, 7964, 7965, 7970, 7971);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition csrli_nzuimm_rs1(ISA16_RV64IMACFD, "csrli",(uint64_t) 0x8001,(uint64_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");cp.code()+="etiss_coverage_count(1, 199);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7957);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(nzuimm)+"ULL;\n";cp.code()+="etiss_coverage_count(11, 7956, 7948, 7947, 7945, 7946, 7955, 7953, 7952, 7950, 7951, 7954);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition caddiw_imm_rs1(ISA16_RV64IMACFD, "caddiw",(uint64_t) 0x2001,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDIW\n");cp.code()+="etiss_coverage_count(1, 206);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 8096);\n";if((rs1 % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8102, 8099, 8097, 8100, 8101);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(11, 8119, 8107, 8106, 8104, 8118, 8114, 8112, 8111, 8109, 8117, 8115);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddiw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cslli_shamt_rs1(ISA16_RV64IMACFD, "cslli",(uint64_t) 0x02,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="etiss_coverage_count(1, 201);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7991);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7975);\n";if(rs1==0LL) { cp.code()+="etiss_coverage_count(3, 7978, 7976, 7977);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 7981, 7979);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 7990, 7984, 7983, 7989, 7987, 7986, 7988);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cld_rd_uimm_rs1(ISA16_RV64IMACFD, "cld",(uint64_t) 0x6000,(uint64_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLD\n");cp.code()+="etiss_coverage_count(1, 202);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+2)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8015);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 8000, 7999, 7997, 7996, 7994, 7995, 7998);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(10, 8014, 8005, 8004, 8002, 8003, 8013, 8011, 8009, 8007, 8008);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.