ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64ICInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CADDIW ----------------------------------------------------------------------
16 static InstructionDefinition caddiw_imm_rs1 (
17  ISA16_RV64IMACFD,
18  "caddiw",
19  (uint16_t) 0x2001,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 imm = 0;
30 static BitArrayRange R_imm_0(6, 2);
31 imm += R_imm_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(11, 7);
34 rs1 += R_rs1_0.read(ba) << 0;
35 static BitArrayRange R_imm_5(12, 12);
36 imm += R_imm_5.read(ba) << 5;
37 
38 // -----------------------------------------------------------------------------
39 
40  {
41  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
42 
43  cp.code() = std::string("//CADDIW\n");
44 
45 // -----------------------------------------------------------------------------
46 cp.code() += "etiss_coverage_count(1, 206);\n";
47 { // block
48 cp.code() += "etiss_coverage_count(1, 1169);\n";
49 cp.code() += "{ // block\n";
50 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
51 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
52 cp.code() += "} // block\n";
53 } // block
54 cp.code() += "etiss_coverage_count(1, 7407);\n";
55 if ((rs1 % 32ULL) != 0LL) { // conditional
56 cp.code() += "etiss_coverage_count(5, 7413, 7410, 7408, 7411, 7412);\n";
57 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
58 cp.code() += "etiss_coverage_count(11, 7430, 7418, 7417, 7415, 7429, 7425, 7423, 7422, 7420, 7428, 7426);\n";
59 } // conditional
60 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
61 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
62 // -----------------------------------------------------------------------------
63  cp.getAffectedRegisters().add("instructionPointer", 32);
64  }
65 
66  return true;
67  },
68  0,
69  [] (BitArray & ba, Instruction & instr)
70  {
71 // -----------------------------------------------------------------------------
72 etiss_uint8 imm = 0;
73 static BitArrayRange R_imm_0(6, 2);
74 imm += R_imm_0.read(ba) << 0;
75 etiss_uint8 rs1 = 0;
76 static BitArrayRange R_rs1_0(11, 7);
77 rs1 += R_rs1_0.read(ba) << 0;
78 static BitArrayRange R_imm_5(12, 12);
79 imm += R_imm_5.read(ba) << 5;
80 
81 // -----------------------------------------------------------------------------
82 
83  std::stringstream ss;
84 // -----------------------------------------------------------------------------
85 ss << "caddiw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
86 // -----------------------------------------------------------------------------
87  return ss.str();
88  }
89 );
90 
91 // CSRLI -----------------------------------------------------------------------
92 static InstructionDefinition csrli_nzuimm_rs1 (
93  ISA16_RV64IMACFD,
94  "csrli",
95  (uint16_t) 0x8001,
96  (uint16_t) 0xec03,
97  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
98  {
99 
100 // -----------------------------------------------------------------------------
101 
102 // -----------------------------------------------------------------------------
103 
104 // -----------------------------------------------------------------------------
105 etiss_uint8 nzuimm = 0;
106 static BitArrayRange R_nzuimm_0(6, 2);
107 nzuimm += R_nzuimm_0.read(ba) << 0;
108 etiss_uint8 rs1 = 0;
109 static BitArrayRange R_rs1_0(9, 7);
110 rs1 += R_rs1_0.read(ba) << 0;
111 static BitArrayRange R_nzuimm_5(12, 12);
112 nzuimm += R_nzuimm_5.read(ba) << 5;
113 
114 // -----------------------------------------------------------------------------
115 
116  {
117  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
118 
119  cp.code() = std::string("//CSRLI\n");
120 
121 // -----------------------------------------------------------------------------
122 cp.code() += "etiss_coverage_count(1, 199);\n";
123 { // block
124 cp.code() += "etiss_coverage_count(1, 1169);\n";
125 cp.code() += "{ // block\n";
126 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
127 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
128 cp.code() += "} // block\n";
129 } // block
130 { // block
131 cp.code() += "etiss_coverage_count(1, 7444);\n";
132 cp.code() += "{ // block\n";
133 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(nzuimm) + "ULL;\n";
134 cp.code() += "etiss_coverage_count(11, 7443, 7435, 7434, 7432, 7433, 7442, 7440, 7439, 7437, 7438, 7441);\n";
135 cp.code() += "} // block\n";
136 } // block
137 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
138 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
139 // -----------------------------------------------------------------------------
140  cp.getAffectedRegisters().add("instructionPointer", 32);
141  }
142 
143  return true;
144  },
145  0,
146  [] (BitArray & ba, Instruction & instr)
147  {
148 // -----------------------------------------------------------------------------
149 etiss_uint8 nzuimm = 0;
150 static BitArrayRange R_nzuimm_0(6, 2);
151 nzuimm += R_nzuimm_0.read(ba) << 0;
152 etiss_uint8 rs1 = 0;
153 static BitArrayRange R_rs1_0(9, 7);
154 rs1 += R_rs1_0.read(ba) << 0;
155 static BitArrayRange R_nzuimm_5(12, 12);
156 nzuimm += R_nzuimm_5.read(ba) << 5;
157 
158 // -----------------------------------------------------------------------------
159 
160  std::stringstream ss;
161 // -----------------------------------------------------------------------------
162 ss << "csrli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
163 // -----------------------------------------------------------------------------
164  return ss.str();
165  }
166 );
167 
168 // CSRAI -----------------------------------------------------------------------
169 static InstructionDefinition csrai_shamt_rs1 (
170  ISA16_RV64IMACFD,
171  "csrai",
172  (uint16_t) 0x8401,
173  (uint16_t) 0xec03,
174  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
175  {
176 
177 // -----------------------------------------------------------------------------
178 
179 // -----------------------------------------------------------------------------
180 
181 // -----------------------------------------------------------------------------
182 etiss_uint8 shamt = 0;
183 static BitArrayRange R_shamt_0(6, 2);
184 shamt += R_shamt_0.read(ba) << 0;
185 etiss_uint8 rs1 = 0;
186 static BitArrayRange R_rs1_0(9, 7);
187 rs1 += R_rs1_0.read(ba) << 0;
188 static BitArrayRange R_shamt_5(12, 12);
189 shamt += R_shamt_5.read(ba) << 5;
190 
191 // -----------------------------------------------------------------------------
192 
193  {
194  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
195 
196  cp.code() = std::string("//CSRAI\n");
197 
198 // -----------------------------------------------------------------------------
199 cp.code() += "etiss_coverage_count(1, 200);\n";
200 { // block
201 cp.code() += "etiss_coverage_count(1, 1169);\n";
202 cp.code() += "{ // block\n";
203 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
204 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
205 cp.code() += "} // block\n";
206 } // block
207 { // block
208 cp.code() += "etiss_coverage_count(1, 7461);\n";
209 cp.code() += "{ // block\n";
210 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
211 cp.code() += "etiss_coverage_count(13, 7460, 7449, 7448, 7446, 7447, 7459, 7456, 7454, 7453, 7451, 7452, 7457, 7458);\n";
212 cp.code() += "} // block\n";
213 } // block
214 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
215 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
216 // -----------------------------------------------------------------------------
217  cp.getAffectedRegisters().add("instructionPointer", 32);
218  }
219 
220  return true;
221  },
222  0,
223  [] (BitArray & ba, Instruction & instr)
224  {
225 // -----------------------------------------------------------------------------
226 etiss_uint8 shamt = 0;
227 static BitArrayRange R_shamt_0(6, 2);
228 shamt += R_shamt_0.read(ba) << 0;
229 etiss_uint8 rs1 = 0;
230 static BitArrayRange R_rs1_0(9, 7);
231 rs1 += R_rs1_0.read(ba) << 0;
232 static BitArrayRange R_shamt_5(12, 12);
233 shamt += R_shamt_5.read(ba) << 5;
234 
235 // -----------------------------------------------------------------------------
236 
237  std::stringstream ss;
238 // -----------------------------------------------------------------------------
239 ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
240 // -----------------------------------------------------------------------------
241  return ss.str();
242  }
243 );
244 
245 // CSLLI -----------------------------------------------------------------------
246 static InstructionDefinition cslli_shamt_rs1 (
247  ISA16_RV64IMACFD,
248  "cslli",
249  (uint16_t) 0x02,
250  (uint16_t) 0xe003,
251  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
252  {
253 
254 // -----------------------------------------------------------------------------
255 
256 // -----------------------------------------------------------------------------
257 
258 // -----------------------------------------------------------------------------
259 etiss_uint8 shamt = 0;
260 static BitArrayRange R_shamt_0(6, 2);
261 shamt += R_shamt_0.read(ba) << 0;
262 etiss_uint8 rs1 = 0;
263 static BitArrayRange R_rs1_0(11, 7);
264 rs1 += R_rs1_0.read(ba) << 0;
265 static BitArrayRange R_shamt_5(12, 12);
266 shamt += R_shamt_5.read(ba) << 5;
267 
268 // -----------------------------------------------------------------------------
269 
270  {
271  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
272 
273  cp.code() = std::string("//CSLLI\n");
274 
275 // -----------------------------------------------------------------------------
276 cp.code() += "etiss_coverage_count(1, 201);\n";
277 { // block
278 cp.code() += "etiss_coverage_count(1, 1169);\n";
279 cp.code() += "{ // block\n";
280 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
281 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
282 cp.code() += "} // block\n";
283 } // block
284 { // block
285 cp.code() += "etiss_coverage_count(1, 7478);\n";
286 cp.code() += "{ // block\n";
287 cp.code() += "etiss_coverage_count(1, 7462);\n";
288 if (rs1 == 0LL) { // conditional
289 cp.code() += "etiss_coverage_count(3, 7465, 7463, 7464);\n";
290 { // procedure
291 cp.code() += "{ // procedure\n";
292 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
293 cp.code() += "etiss_coverage_count(2, 7468, 7466);\n";
294 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
295 cp.code() += "} // procedure\n";
296 } // procedure
297 } // conditional
298 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
299 cp.code() += "etiss_coverage_count(7, 7477, 7471, 7470, 7476, 7474, 7473, 7475);\n";
300 cp.code() += "} // block\n";
301 } // block
302 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
303 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
304 // -----------------------------------------------------------------------------
305  cp.getAffectedRegisters().add("instructionPointer", 32);
306  }
307  {
308  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
309 
310  cp.code() = std::string("//CSLLI\n");
311 
312 // -----------------------------------------------------------------------------
313 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
314 // -----------------------------------------------------------------------------
315  }
316 
317  return true;
318  },
319  0,
320  [] (BitArray & ba, Instruction & instr)
321  {
322 // -----------------------------------------------------------------------------
323 etiss_uint8 shamt = 0;
324 static BitArrayRange R_shamt_0(6, 2);
325 shamt += R_shamt_0.read(ba) << 0;
326 etiss_uint8 rs1 = 0;
327 static BitArrayRange R_rs1_0(11, 7);
328 rs1 += R_rs1_0.read(ba) << 0;
329 static BitArrayRange R_shamt_5(12, 12);
330 shamt += R_shamt_5.read(ba) << 5;
331 
332 // -----------------------------------------------------------------------------
333 
334  std::stringstream ss;
335 // -----------------------------------------------------------------------------
336 ss << "cslli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
337 // -----------------------------------------------------------------------------
338  return ss.str();
339  }
340 );
341 
342 // CLD -------------------------------------------------------------------------
343 static InstructionDefinition cld_rd_uimm_rs1 (
344  ISA16_RV64IMACFD,
345  "cld",
346  (uint16_t) 0x6000,
347  (uint16_t) 0xe003,
348  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
349  {
350 
351 // -----------------------------------------------------------------------------
352 
353 // -----------------------------------------------------------------------------
354 
355 // -----------------------------------------------------------------------------
356 etiss_uint8 rd = 0;
357 static BitArrayRange R_rd_0(4, 2);
358 rd += R_rd_0.read(ba) << 0;
359 etiss_uint8 uimm = 0;
360 static BitArrayRange R_uimm_6(6, 5);
361 uimm += R_uimm_6.read(ba) << 6;
362 etiss_uint8 rs1 = 0;
363 static BitArrayRange R_rs1_0(9, 7);
364 rs1 += R_rs1_0.read(ba) << 0;
365 static BitArrayRange R_uimm_3(12, 10);
366 uimm += R_uimm_3.read(ba) << 3;
367 
368 // -----------------------------------------------------------------------------
369 
370  {
371  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
372 
373  cp.code() = std::string("//CLD\n");
374 
375 // -----------------------------------------------------------------------------
376 cp.code() += "etiss_coverage_count(1, 202);\n";
377 { // block
378 cp.code() += "etiss_coverage_count(1, 1169);\n";
379 cp.code() += "{ // block\n";
380 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
381 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
382 cp.code() += "} // block\n";
383 } // block
384 { // block
385 cp.code() += "etiss_coverage_count(1, 7499);\n";
386 cp.code() += "{ // block\n";
387 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
388 cp.code() += "etiss_coverage_count(7, 7487, 7486, 7484, 7483, 7481, 7482, 7485);\n";
389 cp.code() += "etiss_uint64 mem_val_0;\n";
390 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
391 cp.code() += "if (cpu->exception) { // conditional\n";
392 { // procedure
393 cp.code() += "{ // procedure\n";
394 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
395 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
396 cp.code() += "} // procedure\n";
397 } // procedure
398 cp.code() += "} // conditional\n";
399 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int64)(mem_val_0);\n";
400 cp.code() += "etiss_coverage_count(8, 7498, 7492, 7491, 7489, 7490, 7497, 7495, 7494);\n";
401 cp.code() += "} // block\n";
402 } // block
403 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
404 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
405 // -----------------------------------------------------------------------------
406  cp.getAffectedRegisters().add("instructionPointer", 32);
407  }
408  {
409  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
410 
411  cp.code() = std::string("//CLD\n");
412 
413 // -----------------------------------------------------------------------------
414 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
415 // -----------------------------------------------------------------------------
416  }
417 
418  return true;
419  },
420  0,
421  [] (BitArray & ba, Instruction & instr)
422  {
423 // -----------------------------------------------------------------------------
424 etiss_uint8 rd = 0;
425 static BitArrayRange R_rd_0(4, 2);
426 rd += R_rd_0.read(ba) << 0;
427 etiss_uint8 uimm = 0;
428 static BitArrayRange R_uimm_6(6, 5);
429 uimm += R_uimm_6.read(ba) << 6;
430 etiss_uint8 rs1 = 0;
431 static BitArrayRange R_rs1_0(9, 7);
432 rs1 += R_rs1_0.read(ba) << 0;
433 static BitArrayRange R_uimm_3(12, 10);
434 uimm += R_uimm_3.read(ba) << 3;
435 
436 // -----------------------------------------------------------------------------
437 
438  std::stringstream ss;
439 // -----------------------------------------------------------------------------
440 ss << "cld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
441 // -----------------------------------------------------------------------------
442  return ss.str();
443  }
444 );
445 
446 // CSD -------------------------------------------------------------------------
447 static InstructionDefinition csd_rs2_uimm_rs1 (
448  ISA16_RV64IMACFD,
449  "csd",
450  (uint16_t) 0xe000,
451  (uint16_t) 0xe003,
452  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
453  {
454 
455 // -----------------------------------------------------------------------------
456 
457 // -----------------------------------------------------------------------------
458 
459 // -----------------------------------------------------------------------------
460 etiss_uint8 rs2 = 0;
461 static BitArrayRange R_rs2_0(4, 2);
462 rs2 += R_rs2_0.read(ba) << 0;
463 etiss_uint8 uimm = 0;
464 static BitArrayRange R_uimm_6(6, 5);
465 uimm += R_uimm_6.read(ba) << 6;
466 etiss_uint8 rs1 = 0;
467 static BitArrayRange R_rs1_0(9, 7);
468 rs1 += R_rs1_0.read(ba) << 0;
469 static BitArrayRange R_uimm_3(12, 10);
470 uimm += R_uimm_3.read(ba) << 3;
471 
472 // -----------------------------------------------------------------------------
473 
474  {
475  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
476 
477  cp.code() = std::string("//CSD\n");
478 
479 // -----------------------------------------------------------------------------
480 cp.code() += "etiss_coverage_count(1, 203);\n";
481 { // block
482 cp.code() += "etiss_coverage_count(1, 1169);\n";
483 cp.code() += "{ // block\n";
484 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
485 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
486 cp.code() += "} // block\n";
487 } // block
488 { // block
489 cp.code() += "etiss_coverage_count(1, 7520);\n";
490 cp.code() += "{ // block\n";
491 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
492 cp.code() += "etiss_coverage_count(7, 7508, 7507, 7505, 7504, 7502, 7503, 7506);\n";
493 cp.code() += "etiss_uint64 mem_val_0;\n";
494 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
495 cp.code() += "etiss_coverage_count(8, 7519, 7511, 7510, 7518, 7516, 7515, 7513, 7514);\n";
496 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
497 cp.code() += "if (cpu->exception) { // conditional\n";
498 { // procedure
499 cp.code() += "{ // procedure\n";
500 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
501 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
502 cp.code() += "} // procedure\n";
503 } // procedure
504 cp.code() += "} // conditional\n";
505 cp.code() += "} // block\n";
506 } // block
507 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
508 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
509 // -----------------------------------------------------------------------------
510  cp.getAffectedRegisters().add("instructionPointer", 32);
511  }
512  {
513  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
514 
515  cp.code() = std::string("//CSD\n");
516 
517 // -----------------------------------------------------------------------------
518 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
519 // -----------------------------------------------------------------------------
520  }
521 
522  return true;
523  },
524  0,
525  [] (BitArray & ba, Instruction & instr)
526  {
527 // -----------------------------------------------------------------------------
528 etiss_uint8 rs2 = 0;
529 static BitArrayRange R_rs2_0(4, 2);
530 rs2 += R_rs2_0.read(ba) << 0;
531 etiss_uint8 uimm = 0;
532 static BitArrayRange R_uimm_6(6, 5);
533 uimm += R_uimm_6.read(ba) << 6;
534 etiss_uint8 rs1 = 0;
535 static BitArrayRange R_rs1_0(9, 7);
536 rs1 += R_rs1_0.read(ba) << 0;
537 static BitArrayRange R_uimm_3(12, 10);
538 uimm += R_uimm_3.read(ba) << 3;
539 
540 // -----------------------------------------------------------------------------
541 
542  std::stringstream ss;
543 // -----------------------------------------------------------------------------
544 ss << "csd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
545 // -----------------------------------------------------------------------------
546  return ss.str();
547  }
548 );
549 
550 // CSUBW -----------------------------------------------------------------------
551 static InstructionDefinition csubw_rs2_rd (
552  ISA16_RV64IMACFD,
553  "csubw",
554  (uint16_t) 0x9c01,
555  (uint16_t) 0xfc63,
556  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
557  {
558 
559 // -----------------------------------------------------------------------------
560 
561 // -----------------------------------------------------------------------------
562 
563 // -----------------------------------------------------------------------------
564 etiss_uint8 rs2 = 0;
565 static BitArrayRange R_rs2_0(4, 2);
566 rs2 += R_rs2_0.read(ba) << 0;
567 etiss_uint8 rd = 0;
568 static BitArrayRange R_rd_0(9, 7);
569 rd += R_rd_0.read(ba) << 0;
570 
571 // -----------------------------------------------------------------------------
572 
573  {
574  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
575 
576  cp.code() = std::string("//CSUBW\n");
577 
578 // -----------------------------------------------------------------------------
579 cp.code() += "etiss_coverage_count(1, 204);\n";
580 { // block
581 cp.code() += "etiss_coverage_count(1, 1169);\n";
582 cp.code() += "{ // block\n";
583 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
584 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
585 cp.code() += "} // block\n";
586 } // block
587 { // block
588 cp.code() += "etiss_coverage_count(1, 7548);\n";
589 cp.code() += "{ // block\n";
590 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
591 cp.code() += "etiss_coverage_count(12, 7537, 7536, 7528, 7526, 7525, 7523, 7524, 7535, 7533, 7532, 7530, 7531);\n";
592 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
593 cp.code() += "etiss_coverage_count(8, 7547, 7542, 7541, 7539, 7540, 7546, 7544, 7543);\n";
594 cp.code() += "} // block\n";
595 } // block
596 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
597 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
598 // -----------------------------------------------------------------------------
599  cp.getAffectedRegisters().add("instructionPointer", 32);
600  }
601 
602  return true;
603  },
604  0,
605  [] (BitArray & ba, Instruction & instr)
606  {
607 // -----------------------------------------------------------------------------
608 etiss_uint8 rs2 = 0;
609 static BitArrayRange R_rs2_0(4, 2);
610 rs2 += R_rs2_0.read(ba) << 0;
611 etiss_uint8 rd = 0;
612 static BitArrayRange R_rd_0(9, 7);
613 rd += R_rd_0.read(ba) << 0;
614 
615 // -----------------------------------------------------------------------------
616 
617  std::stringstream ss;
618 // -----------------------------------------------------------------------------
619 ss << "csubw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
620 // -----------------------------------------------------------------------------
621  return ss.str();
622  }
623 );
624 
625 // CADDW -----------------------------------------------------------------------
626 static InstructionDefinition caddw_rs2_rd (
627  ISA16_RV64IMACFD,
628  "caddw",
629  (uint16_t) 0x9c21,
630  (uint16_t) 0xfc63,
631  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
632  {
633 
634 // -----------------------------------------------------------------------------
635 
636 // -----------------------------------------------------------------------------
637 
638 // -----------------------------------------------------------------------------
639 etiss_uint8 rs2 = 0;
640 static BitArrayRange R_rs2_0(4, 2);
641 rs2 += R_rs2_0.read(ba) << 0;
642 etiss_uint8 rd = 0;
643 static BitArrayRange R_rd_0(9, 7);
644 rd += R_rd_0.read(ba) << 0;
645 
646 // -----------------------------------------------------------------------------
647 
648  {
649  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
650 
651  cp.code() = std::string("//CADDW\n");
652 
653 // -----------------------------------------------------------------------------
654 cp.code() += "etiss_coverage_count(1, 205);\n";
655 { // block
656 cp.code() += "etiss_coverage_count(1, 1169);\n";
657 cp.code() += "{ // block\n";
658 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
659 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
660 cp.code() += "} // block\n";
661 } // block
662 { // block
663 cp.code() += "etiss_coverage_count(1, 7576);\n";
664 cp.code() += "{ // block\n";
665 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
666 cp.code() += "etiss_coverage_count(12, 7565, 7564, 7556, 7554, 7553, 7551, 7552, 7563, 7561, 7560, 7558, 7559);\n";
667 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
668 cp.code() += "etiss_coverage_count(8, 7575, 7570, 7569, 7567, 7568, 7574, 7572, 7571);\n";
669 cp.code() += "} // block\n";
670 } // block
671 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
672 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
673 // -----------------------------------------------------------------------------
674  cp.getAffectedRegisters().add("instructionPointer", 32);
675  }
676 
677  return true;
678  },
679  0,
680  [] (BitArray & ba, Instruction & instr)
681  {
682 // -----------------------------------------------------------------------------
683 etiss_uint8 rs2 = 0;
684 static BitArrayRange R_rs2_0(4, 2);
685 rs2 += R_rs2_0.read(ba) << 0;
686 etiss_uint8 rd = 0;
687 static BitArrayRange R_rd_0(9, 7);
688 rd += R_rd_0.read(ba) << 0;
689 
690 // -----------------------------------------------------------------------------
691 
692  std::stringstream ss;
693 // -----------------------------------------------------------------------------
694 ss << "caddw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
695 // -----------------------------------------------------------------------------
696  return ss.str();
697  }
698 );
699 
700 // CLDSP -----------------------------------------------------------------------
701 static InstructionDefinition cldsp_uimm_rd (
702  ISA16_RV64IMACFD,
703  "cldsp",
704  (uint16_t) 0x6002,
705  (uint16_t) 0xe003,
706  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
707  {
708 
709 // -----------------------------------------------------------------------------
710 
711 // -----------------------------------------------------------------------------
712 
713 // -----------------------------------------------------------------------------
714 etiss_uint16 uimm = 0;
715 static BitArrayRange R_uimm_6(4, 2);
716 uimm += R_uimm_6.read(ba) << 6;
717 static BitArrayRange R_uimm_3(6, 5);
718 uimm += R_uimm_3.read(ba) << 3;
719 etiss_uint8 rd = 0;
720 static BitArrayRange R_rd_0(11, 7);
721 rd += R_rd_0.read(ba) << 0;
722 static BitArrayRange R_uimm_5(12, 12);
723 uimm += R_uimm_5.read(ba) << 5;
724 
725 // -----------------------------------------------------------------------------
726 
727  {
728  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
729 
730  cp.code() = std::string("//CLDSP\n");
731 
732 // -----------------------------------------------------------------------------
733 cp.code() += "etiss_coverage_count(1, 207);\n";
734 { // block
735 cp.code() += "etiss_coverage_count(1, 1169);\n";
736 cp.code() += "{ // block\n";
737 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
738 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
739 cp.code() += "} // block\n";
740 } // block
741 { // block
742 cp.code() += "etiss_coverage_count(1, 7603);\n";
743 cp.code() += "{ // block\n";
744 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
745 cp.code() += "etiss_coverage_count(5, 7583, 7582, 7580, 7579, 7581);\n";
746 cp.code() += "etiss_uint64 mem_val_0;\n";
747 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
748 cp.code() += "if (cpu->exception) { // conditional\n";
749 { // procedure
750 cp.code() += "{ // procedure\n";
751 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
752 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
753 cp.code() += "} // procedure\n";
754 } // procedure
755 cp.code() += "} // conditional\n";
756 cp.code() += "etiss_int64 res = mem_val_0;\n";
757 cp.code() += "etiss_coverage_count(3, 7588, 7587, 7586);\n";
758 cp.code() += "etiss_coverage_count(1, 7589);\n";
759 if (rd % 32ULL) { // conditional
760 cp.code() += "etiss_coverage_count(2, 7592, 7590);\n";
761 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
762 cp.code() += "etiss_coverage_count(5, 7599, 7597, 7596, 7594, 7598);\n";
763 } // conditional
764 else { // conditional
765 { // procedure
766 cp.code() += "{ // procedure\n";
767 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
768 cp.code() += "etiss_coverage_count(3, 7602, 7600, 7601);\n";
769 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
770 cp.code() += "} // procedure\n";
771 } // procedure
772 } // conditional
773 cp.code() += "} // block\n";
774 } // block
775 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
776 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
777 // -----------------------------------------------------------------------------
778  cp.getAffectedRegisters().add("instructionPointer", 32);
779  }
780  {
781  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
782 
783  cp.code() = std::string("//CLDSP\n");
784 
785 // -----------------------------------------------------------------------------
786 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
787 // -----------------------------------------------------------------------------
788  }
789 
790  return true;
791  },
792  0,
793  [] (BitArray & ba, Instruction & instr)
794  {
795 // -----------------------------------------------------------------------------
796 etiss_uint16 uimm = 0;
797 static BitArrayRange R_uimm_6(4, 2);
798 uimm += R_uimm_6.read(ba) << 6;
799 static BitArrayRange R_uimm_3(6, 5);
800 uimm += R_uimm_3.read(ba) << 3;
801 etiss_uint8 rd = 0;
802 static BitArrayRange R_rd_0(11, 7);
803 rd += R_rd_0.read(ba) << 0;
804 static BitArrayRange R_uimm_5(12, 12);
805 uimm += R_uimm_5.read(ba) << 5;
806 
807 // -----------------------------------------------------------------------------
808 
809  std::stringstream ss;
810 // -----------------------------------------------------------------------------
811 ss << "cldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
812 // -----------------------------------------------------------------------------
813  return ss.str();
814  }
815 );
816 
817 // CSDSP -----------------------------------------------------------------------
818 static InstructionDefinition csdsp_rs2_uimm (
819  ISA16_RV64IMACFD,
820  "csdsp",
821  (uint16_t) 0xe002,
822  (uint16_t) 0xe003,
823  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
824  {
825 
826 // -----------------------------------------------------------------------------
827 
828 // -----------------------------------------------------------------------------
829 
830 // -----------------------------------------------------------------------------
831 etiss_uint8 rs2 = 0;
832 static BitArrayRange R_rs2_0(6, 2);
833 rs2 += R_rs2_0.read(ba) << 0;
834 etiss_uint16 uimm = 0;
835 static BitArrayRange R_uimm_6(9, 7);
836 uimm += R_uimm_6.read(ba) << 6;
837 static BitArrayRange R_uimm_3(12, 10);
838 uimm += R_uimm_3.read(ba) << 3;
839 
840 // -----------------------------------------------------------------------------
841 
842  {
843  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
844 
845  cp.code() = std::string("//CSDSP\n");
846 
847 // -----------------------------------------------------------------------------
848 cp.code() += "etiss_coverage_count(1, 208);\n";
849 { // block
850 cp.code() += "etiss_coverage_count(1, 1169);\n";
851 cp.code() += "{ // block\n";
852 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
853 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
854 cp.code() += "} // block\n";
855 } // block
856 { // block
857 cp.code() += "etiss_coverage_count(1, 7622);\n";
858 cp.code() += "{ // block\n";
859 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
860 cp.code() += "etiss_coverage_count(5, 7610, 7609, 7607, 7606, 7608);\n";
861 cp.code() += "etiss_uint64 mem_val_0;\n";
862 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
863 cp.code() += "etiss_coverage_count(7, 7621, 7613, 7612, 7620, 7618, 7617, 7615);\n";
864 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
865 cp.code() += "if (cpu->exception) { // conditional\n";
866 { // procedure
867 cp.code() += "{ // procedure\n";
868 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
869 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
870 cp.code() += "} // procedure\n";
871 } // procedure
872 cp.code() += "} // conditional\n";
873 cp.code() += "} // block\n";
874 } // block
875 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
876 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
877 // -----------------------------------------------------------------------------
878  cp.getAffectedRegisters().add("instructionPointer", 32);
879  }
880  {
881  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
882 
883  cp.code() = std::string("//CSDSP\n");
884 
885 // -----------------------------------------------------------------------------
886 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
887 // -----------------------------------------------------------------------------
888  }
889 
890  return true;
891  },
892  0,
893  [] (BitArray & ba, Instruction & instr)
894  {
895 // -----------------------------------------------------------------------------
896 etiss_uint8 rs2 = 0;
897 static BitArrayRange R_rs2_0(6, 2);
898 rs2 += R_rs2_0.read(ba) << 0;
899 etiss_uint16 uimm = 0;
900 static BitArrayRange R_uimm_6(9, 7);
901 uimm += R_uimm_6.read(ba) << 6;
902 static BitArrayRange R_uimm_3(12, 10);
903 uimm += R_uimm_3.read(ba) << 3;
904 
905 // -----------------------------------------------------------------------------
906 
907  std::stringstream ss;
908 // -----------------------------------------------------------------------------
909 ss << "csdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
910 // -----------------------------------------------------------------------------
911  return ss.str();
912  }
913 );
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
csrai_shamt_rs1
static InstructionDefinition csrai_shamt_rs1(ISA16_RV64IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");cp.code()+="etiss_coverage_count(1, 200);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7461);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(13, 7460, 7449, 7448, 7446, 7447, 7459, 7456, 7454, 7453, 7451, 7452, 7457, 7458);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csubw_rs2_rd
static InstructionDefinition csubw_rs2_rd(ISA16_RV64IMACFD, "csubw",(uint16_t) 0x9c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUBW\n");cp.code()+="etiss_coverage_count(1, 204);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7548);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 7537, 7536, 7528, 7526, 7525, 7523, 7524, 7535, 7533, 7532, 7530, 7531);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(8, 7547, 7542, 7541, 7539, 7540, 7546, 7544, 7543);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csubw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csdsp_rs2_uimm
static InstructionDefinition csdsp_rs2_uimm(ISA16_RV64IMACFD, "csdsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSDSP\n");cp.code()+="etiss_coverage_count(1, 208);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7622);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 7610, 7609, 7607, 7606, 7608);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 7621, 7613, 7612, 7620, 7618, 7617, 7615);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
caddw_rs2_rd
static InstructionDefinition caddw_rs2_rd(ISA16_RV64IMACFD, "caddw",(uint16_t) 0x9c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDW\n");cp.code()+="etiss_coverage_count(1, 205);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7576);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 7565, 7564, 7556, 7554, 7553, 7551, 7552, 7563, 7561, 7560, 7558, 7559);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(8, 7575, 7570, 7569, 7567, 7568, 7574, 7572, 7571);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "caddw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cldsp_uimm_rd
static InstructionDefinition cldsp_uimm_rd(ISA16_RV64IMACFD, "cldsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLDSP\n");cp.code()+="etiss_coverage_count(1, 207);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7603);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 7583, 7582, 7580, 7579, 7581);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 7588, 7587, 7586);\n";cp.code()+="etiss_coverage_count(1, 7589);\n";if(rd % 32ULL) { cp.code()+="etiss_coverage_count(2, 7592, 7590);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 7599, 7597, 7596, 7594, 7598);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 7602, 7600, 7601);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csrli_nzuimm_rs1
static InstructionDefinition csrli_nzuimm_rs1(ISA16_RV64IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");cp.code()+="etiss_coverage_count(1, 199);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7444);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(nzuimm)+"ULL;\n";cp.code()+="etiss_coverage_count(11, 7443, 7435, 7434, 7432, 7433, 7442, 7440, 7439, 7437, 7438, 7441);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
caddiw_imm_rs1
static InstructionDefinition caddiw_imm_rs1(ISA16_RV64IMACFD, "caddiw",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDIW\n");cp.code()+="etiss_coverage_count(1, 206);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 7407);\n";if((rs1 % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7413, 7410, 7408, 7411, 7412);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";cp.code()+="etiss_coverage_count(11, 7430, 7418, 7417, 7415, 7429, 7425, 7423, 7422, 7420, 7428, 7426);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddiw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cslli_shamt_rs1
static InstructionDefinition cslli_shamt_rs1(ISA16_RV64IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="etiss_coverage_count(1, 201);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7478);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7462);\n";if(rs1==0LL) { cp.code()+="etiss_coverage_count(3, 7465, 7463, 7464);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 7468, 7466);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 7477, 7471, 7470, 7476, 7474, 7473, 7475);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csd_rs2_uimm_rs1
static InstructionDefinition csd_rs2_uimm_rs1(ISA16_RV64IMACFD, "csd",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSD\n");cp.code()+="etiss_coverage_count(1, 203);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7520);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 7508, 7507, 7505, 7504, 7502, 7503, 7506);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 7519, 7511, 7510, 7518, 7516, 7515, 7513, 7514);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cld_rd_uimm_rs1
static InstructionDefinition cld_rd_uimm_rs1(ISA16_RV64IMACFD, "cld",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLD\n");cp.code()+="etiss_coverage_count(1, 202);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7499);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 7487, 7486, 7484, 7483, 7481, 7482, 7485);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(8, 7498, 7492, 7491, 7489, 7490, 7497, 7495, 7494);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_int8
int8_t etiss_int8
Definition: types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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