ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64ICInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CADDIW ----------------------------------------------------------------------
16 static InstructionDefinition caddiw_imm_rs1 (
17  ISA16_RV64IMACFD,
18  "caddiw",
19  (uint16_t) 0x2001,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 imm = 0;
30 static BitArrayRange R_imm_0(6, 2);
31 imm += R_imm_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(11, 7);
34 rs1 += R_rs1_0.read(ba) << 0;
35 static BitArrayRange R_imm_5(12, 12);
36 imm += R_imm_5.read(ba) << 5;
37 
38 // -----------------------------------------------------------------------------
39 
40  {
41  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
42 
43  cp.code() = std::string("//CADDIW\n");
44 
45 // -----------------------------------------------------------------------------
46 { // block
47 cp.code() += "{ // block\n";
48 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
49 cp.code() += "} // block\n";
50 } // block
51 if ((rs1 % 32ULL) != 0LL) { // conditional
52 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
53 } // conditional
54 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
55 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
56 // -----------------------------------------------------------------------------
57  cp.getAffectedRegisters().add("instructionPointer", 32);
58  }
59 
60  return true;
61  },
62  0,
63  [] (BitArray & ba, Instruction & instr)
64  {
65 // -----------------------------------------------------------------------------
66 etiss_uint8 imm = 0;
67 static BitArrayRange R_imm_0(6, 2);
68 imm += R_imm_0.read(ba) << 0;
69 etiss_uint8 rs1 = 0;
70 static BitArrayRange R_rs1_0(11, 7);
71 rs1 += R_rs1_0.read(ba) << 0;
72 static BitArrayRange R_imm_5(12, 12);
73 imm += R_imm_5.read(ba) << 5;
74 
75 // -----------------------------------------------------------------------------
76 
77  std::stringstream ss;
78 // -----------------------------------------------------------------------------
79 ss << "caddiw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
80 // -----------------------------------------------------------------------------
81  return ss.str();
82  }
83 );
84 
85 // CSRLI -----------------------------------------------------------------------
86 static InstructionDefinition csrli_nzuimm_rs1 (
87  ISA16_RV64IMACFD,
88  "csrli",
89  (uint16_t) 0x8001,
90  (uint16_t) 0xec03,
91  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
92  {
93 
94 // -----------------------------------------------------------------------------
95 
96 // -----------------------------------------------------------------------------
97 
98 // -----------------------------------------------------------------------------
99 etiss_uint8 nzuimm = 0;
100 static BitArrayRange R_nzuimm_0(6, 2);
101 nzuimm += R_nzuimm_0.read(ba) << 0;
102 etiss_uint8 rs1 = 0;
103 static BitArrayRange R_rs1_0(9, 7);
104 rs1 += R_rs1_0.read(ba) << 0;
105 static BitArrayRange R_nzuimm_5(12, 12);
106 nzuimm += R_nzuimm_5.read(ba) << 5;
107 
108 // -----------------------------------------------------------------------------
109 
110  {
111  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
112 
113  cp.code() = std::string("//CSRLI\n");
114 
115 // -----------------------------------------------------------------------------
116 { // block
117 cp.code() += "{ // block\n";
118 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
119 cp.code() += "} // block\n";
120 } // block
121 { // block
122 cp.code() += "{ // block\n";
123 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(nzuimm) + "ULL;\n";
124 cp.code() += "} // block\n";
125 } // block
126 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
127 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
128 // -----------------------------------------------------------------------------
129  cp.getAffectedRegisters().add("instructionPointer", 32);
130  }
131 
132  return true;
133  },
134  0,
135  [] (BitArray & ba, Instruction & instr)
136  {
137 // -----------------------------------------------------------------------------
138 etiss_uint8 nzuimm = 0;
139 static BitArrayRange R_nzuimm_0(6, 2);
140 nzuimm += R_nzuimm_0.read(ba) << 0;
141 etiss_uint8 rs1 = 0;
142 static BitArrayRange R_rs1_0(9, 7);
143 rs1 += R_rs1_0.read(ba) << 0;
144 static BitArrayRange R_nzuimm_5(12, 12);
145 nzuimm += R_nzuimm_5.read(ba) << 5;
146 
147 // -----------------------------------------------------------------------------
148 
149  std::stringstream ss;
150 // -----------------------------------------------------------------------------
151 ss << "csrli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
152 // -----------------------------------------------------------------------------
153  return ss.str();
154  }
155 );
156 
157 // CSRAI -----------------------------------------------------------------------
158 static InstructionDefinition csrai_shamt_rs1 (
159  ISA16_RV64IMACFD,
160  "csrai",
161  (uint16_t) 0x8401,
162  (uint16_t) 0xec03,
163  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
164  {
165 
166 // -----------------------------------------------------------------------------
167 
168 // -----------------------------------------------------------------------------
169 
170 // -----------------------------------------------------------------------------
171 etiss_uint8 shamt = 0;
172 static BitArrayRange R_shamt_0(6, 2);
173 shamt += R_shamt_0.read(ba) << 0;
174 etiss_uint8 rs1 = 0;
175 static BitArrayRange R_rs1_0(9, 7);
176 rs1 += R_rs1_0.read(ba) << 0;
177 static BitArrayRange R_shamt_5(12, 12);
178 shamt += R_shamt_5.read(ba) << 5;
179 
180 // -----------------------------------------------------------------------------
181 
182  {
183  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
184 
185  cp.code() = std::string("//CSRAI\n");
186 
187 // -----------------------------------------------------------------------------
188 { // block
189 cp.code() += "{ // block\n";
190 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
191 cp.code() += "} // block\n";
192 } // block
193 { // block
194 cp.code() += "{ // block\n";
195 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
196 cp.code() += "} // block\n";
197 } // block
198 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
199 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
200 // -----------------------------------------------------------------------------
201  cp.getAffectedRegisters().add("instructionPointer", 32);
202  }
203 
204  return true;
205  },
206  0,
207  [] (BitArray & ba, Instruction & instr)
208  {
209 // -----------------------------------------------------------------------------
210 etiss_uint8 shamt = 0;
211 static BitArrayRange R_shamt_0(6, 2);
212 shamt += R_shamt_0.read(ba) << 0;
213 etiss_uint8 rs1 = 0;
214 static BitArrayRange R_rs1_0(9, 7);
215 rs1 += R_rs1_0.read(ba) << 0;
216 static BitArrayRange R_shamt_5(12, 12);
217 shamt += R_shamt_5.read(ba) << 5;
218 
219 // -----------------------------------------------------------------------------
220 
221  std::stringstream ss;
222 // -----------------------------------------------------------------------------
223 ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
224 // -----------------------------------------------------------------------------
225  return ss.str();
226  }
227 );
228 
229 // CSLLI -----------------------------------------------------------------------
230 static InstructionDefinition cslli_shamt_rs1 (
231  ISA16_RV64IMACFD,
232  "cslli",
233  (uint16_t) 0x02,
234  (uint16_t) 0xe003,
235  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
236  {
237 
238 // -----------------------------------------------------------------------------
239 
240 // -----------------------------------------------------------------------------
241 
242 // -----------------------------------------------------------------------------
243 etiss_uint8 shamt = 0;
244 static BitArrayRange R_shamt_0(6, 2);
245 shamt += R_shamt_0.read(ba) << 0;
246 etiss_uint8 rs1 = 0;
247 static BitArrayRange R_rs1_0(11, 7);
248 rs1 += R_rs1_0.read(ba) << 0;
249 static BitArrayRange R_shamt_5(12, 12);
250 shamt += R_shamt_5.read(ba) << 5;
251 
252 // -----------------------------------------------------------------------------
253 
254  {
255  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
256 
257  cp.code() = std::string("//CSLLI\n");
258 
259 // -----------------------------------------------------------------------------
260 { // block
261 cp.code() += "{ // block\n";
262 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
263 cp.code() += "} // block\n";
264 } // block
265 { // block
266 cp.code() += "{ // block\n";
267 if (rs1 == 0LL) { // conditional
268 { // procedure
269 cp.code() += "{ // procedure\n";
270 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
271 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
272 cp.code() += "} // procedure\n";
273 } // procedure
274 } // conditional
275 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
276 cp.code() += "} // block\n";
277 } // block
278 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
279 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
280 // -----------------------------------------------------------------------------
281  cp.getAffectedRegisters().add("instructionPointer", 32);
282  }
283  {
284  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
285 
286  cp.code() = std::string("//CSLLI\n");
287 
288 // -----------------------------------------------------------------------------
289 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
290 // -----------------------------------------------------------------------------
291  }
292 
293  return true;
294  },
295  0,
296  [] (BitArray & ba, Instruction & instr)
297  {
298 // -----------------------------------------------------------------------------
299 etiss_uint8 shamt = 0;
300 static BitArrayRange R_shamt_0(6, 2);
301 shamt += R_shamt_0.read(ba) << 0;
302 etiss_uint8 rs1 = 0;
303 static BitArrayRange R_rs1_0(11, 7);
304 rs1 += R_rs1_0.read(ba) << 0;
305 static BitArrayRange R_shamt_5(12, 12);
306 shamt += R_shamt_5.read(ba) << 5;
307 
308 // -----------------------------------------------------------------------------
309 
310  std::stringstream ss;
311 // -----------------------------------------------------------------------------
312 ss << "cslli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
313 // -----------------------------------------------------------------------------
314  return ss.str();
315  }
316 );
317 
318 // CLD -------------------------------------------------------------------------
319 static InstructionDefinition cld_rd_uimm_rs1 (
320  ISA16_RV64IMACFD,
321  "cld",
322  (uint16_t) 0x6000,
323  (uint16_t) 0xe003,
324  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
325  {
326 
327 // -----------------------------------------------------------------------------
328 
329 // -----------------------------------------------------------------------------
330 
331 // -----------------------------------------------------------------------------
332 etiss_uint8 rd = 0;
333 static BitArrayRange R_rd_0(4, 2);
334 rd += R_rd_0.read(ba) << 0;
335 etiss_uint8 uimm = 0;
336 static BitArrayRange R_uimm_6(6, 5);
337 uimm += R_uimm_6.read(ba) << 6;
338 etiss_uint8 rs1 = 0;
339 static BitArrayRange R_rs1_0(9, 7);
340 rs1 += R_rs1_0.read(ba) << 0;
341 static BitArrayRange R_uimm_3(12, 10);
342 uimm += R_uimm_3.read(ba) << 3;
343 
344 // -----------------------------------------------------------------------------
345 
346  {
347  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
348 
349  cp.code() = std::string("//CLD\n");
350 
351 // -----------------------------------------------------------------------------
352 { // block
353 cp.code() += "{ // block\n";
354 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
355 cp.code() += "} // block\n";
356 } // block
357 { // block
358 cp.code() += "{ // block\n";
359 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
360 cp.code() += "etiss_uint64 mem_val_0;\n";
361 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
362 cp.code() += "if (cpu->exception) { // conditional\n";
363 { // procedure
364 cp.code() += "{ // procedure\n";
365 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
366 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
367 cp.code() += "} // procedure\n";
368 } // procedure
369 cp.code() += "} // conditional\n";
370 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int64)(mem_val_0);\n";
371 cp.code() += "} // block\n";
372 } // block
373 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
374 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
375 // -----------------------------------------------------------------------------
376  cp.getAffectedRegisters().add("instructionPointer", 32);
377  }
378  {
379  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
380 
381  cp.code() = std::string("//CLD\n");
382 
383 // -----------------------------------------------------------------------------
384 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
385 // -----------------------------------------------------------------------------
386  }
387 
388  return true;
389  },
390  0,
391  [] (BitArray & ba, Instruction & instr)
392  {
393 // -----------------------------------------------------------------------------
394 etiss_uint8 rd = 0;
395 static BitArrayRange R_rd_0(4, 2);
396 rd += R_rd_0.read(ba) << 0;
397 etiss_uint8 uimm = 0;
398 static BitArrayRange R_uimm_6(6, 5);
399 uimm += R_uimm_6.read(ba) << 6;
400 etiss_uint8 rs1 = 0;
401 static BitArrayRange R_rs1_0(9, 7);
402 rs1 += R_rs1_0.read(ba) << 0;
403 static BitArrayRange R_uimm_3(12, 10);
404 uimm += R_uimm_3.read(ba) << 3;
405 
406 // -----------------------------------------------------------------------------
407 
408  std::stringstream ss;
409 // -----------------------------------------------------------------------------
410 ss << "cld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
411 // -----------------------------------------------------------------------------
412  return ss.str();
413  }
414 );
415 
416 // CSD -------------------------------------------------------------------------
417 static InstructionDefinition csd_rs2_uimm_rs1 (
418  ISA16_RV64IMACFD,
419  "csd",
420  (uint16_t) 0xe000,
421  (uint16_t) 0xe003,
422  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
423  {
424 
425 // -----------------------------------------------------------------------------
426 
427 // -----------------------------------------------------------------------------
428 
429 // -----------------------------------------------------------------------------
430 etiss_uint8 rs2 = 0;
431 static BitArrayRange R_rs2_0(4, 2);
432 rs2 += R_rs2_0.read(ba) << 0;
433 etiss_uint8 uimm = 0;
434 static BitArrayRange R_uimm_6(6, 5);
435 uimm += R_uimm_6.read(ba) << 6;
436 etiss_uint8 rs1 = 0;
437 static BitArrayRange R_rs1_0(9, 7);
438 rs1 += R_rs1_0.read(ba) << 0;
439 static BitArrayRange R_uimm_3(12, 10);
440 uimm += R_uimm_3.read(ba) << 3;
441 
442 // -----------------------------------------------------------------------------
443 
444  {
445  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
446 
447  cp.code() = std::string("//CSD\n");
448 
449 // -----------------------------------------------------------------------------
450 { // block
451 cp.code() += "{ // block\n";
452 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
453 cp.code() += "} // block\n";
454 } // block
455 { // block
456 cp.code() += "{ // block\n";
457 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
458 cp.code() += "etiss_uint64 mem_val_0;\n";
459 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
460 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
461 cp.code() += "if (cpu->exception) { // conditional\n";
462 { // procedure
463 cp.code() += "{ // procedure\n";
464 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
465 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
466 cp.code() += "} // procedure\n";
467 } // procedure
468 cp.code() += "} // conditional\n";
469 cp.code() += "} // block\n";
470 } // block
471 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
472 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
473 // -----------------------------------------------------------------------------
474  cp.getAffectedRegisters().add("instructionPointer", 32);
475  }
476  {
477  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
478 
479  cp.code() = std::string("//CSD\n");
480 
481 // -----------------------------------------------------------------------------
482 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
483 // -----------------------------------------------------------------------------
484  }
485 
486  return true;
487  },
488  0,
489  [] (BitArray & ba, Instruction & instr)
490  {
491 // -----------------------------------------------------------------------------
492 etiss_uint8 rs2 = 0;
493 static BitArrayRange R_rs2_0(4, 2);
494 rs2 += R_rs2_0.read(ba) << 0;
495 etiss_uint8 uimm = 0;
496 static BitArrayRange R_uimm_6(6, 5);
497 uimm += R_uimm_6.read(ba) << 6;
498 etiss_uint8 rs1 = 0;
499 static BitArrayRange R_rs1_0(9, 7);
500 rs1 += R_rs1_0.read(ba) << 0;
501 static BitArrayRange R_uimm_3(12, 10);
502 uimm += R_uimm_3.read(ba) << 3;
503 
504 // -----------------------------------------------------------------------------
505 
506  std::stringstream ss;
507 // -----------------------------------------------------------------------------
508 ss << "csd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
509 // -----------------------------------------------------------------------------
510  return ss.str();
511  }
512 );
513 
514 // CSUBW -----------------------------------------------------------------------
515 static InstructionDefinition csubw_rs2_rd (
516  ISA16_RV64IMACFD,
517  "csubw",
518  (uint16_t) 0x9c01,
519  (uint16_t) 0xfc63,
520  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
521  {
522 
523 // -----------------------------------------------------------------------------
524 
525 // -----------------------------------------------------------------------------
526 
527 // -----------------------------------------------------------------------------
528 etiss_uint8 rs2 = 0;
529 static BitArrayRange R_rs2_0(4, 2);
530 rs2 += R_rs2_0.read(ba) << 0;
531 etiss_uint8 rd = 0;
532 static BitArrayRange R_rd_0(9, 7);
533 rd += R_rd_0.read(ba) << 0;
534 
535 // -----------------------------------------------------------------------------
536 
537  {
538  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
539 
540  cp.code() = std::string("//CSUBW\n");
541 
542 // -----------------------------------------------------------------------------
543 { // block
544 cp.code() += "{ // block\n";
545 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
546 cp.code() += "} // block\n";
547 } // block
548 { // block
549 cp.code() += "{ // block\n";
550 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
551 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
552 cp.code() += "} // block\n";
553 } // block
554 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
555 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
556 // -----------------------------------------------------------------------------
557  cp.getAffectedRegisters().add("instructionPointer", 32);
558  }
559 
560  return true;
561  },
562  0,
563  [] (BitArray & ba, Instruction & instr)
564  {
565 // -----------------------------------------------------------------------------
566 etiss_uint8 rs2 = 0;
567 static BitArrayRange R_rs2_0(4, 2);
568 rs2 += R_rs2_0.read(ba) << 0;
569 etiss_uint8 rd = 0;
570 static BitArrayRange R_rd_0(9, 7);
571 rd += R_rd_0.read(ba) << 0;
572 
573 // -----------------------------------------------------------------------------
574 
575  std::stringstream ss;
576 // -----------------------------------------------------------------------------
577 ss << "csubw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
578 // -----------------------------------------------------------------------------
579  return ss.str();
580  }
581 );
582 
583 // CADDW -----------------------------------------------------------------------
584 static InstructionDefinition caddw_rs2_rd (
585  ISA16_RV64IMACFD,
586  "caddw",
587  (uint16_t) 0x9c21,
588  (uint16_t) 0xfc63,
589  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
590  {
591 
592 // -----------------------------------------------------------------------------
593 
594 // -----------------------------------------------------------------------------
595 
596 // -----------------------------------------------------------------------------
597 etiss_uint8 rs2 = 0;
598 static BitArrayRange R_rs2_0(4, 2);
599 rs2 += R_rs2_0.read(ba) << 0;
600 etiss_uint8 rd = 0;
601 static BitArrayRange R_rd_0(9, 7);
602 rd += R_rd_0.read(ba) << 0;
603 
604 // -----------------------------------------------------------------------------
605 
606  {
607  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
608 
609  cp.code() = std::string("//CADDW\n");
610 
611 // -----------------------------------------------------------------------------
612 { // block
613 cp.code() += "{ // block\n";
614 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
615 cp.code() += "} // block\n";
616 } // block
617 { // block
618 cp.code() += "{ // block\n";
619 cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
620 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
621 cp.code() += "} // block\n";
622 } // block
623 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
624 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
625 // -----------------------------------------------------------------------------
626  cp.getAffectedRegisters().add("instructionPointer", 32);
627  }
628 
629  return true;
630  },
631  0,
632  [] (BitArray & ba, Instruction & instr)
633  {
634 // -----------------------------------------------------------------------------
635 etiss_uint8 rs2 = 0;
636 static BitArrayRange R_rs2_0(4, 2);
637 rs2 += R_rs2_0.read(ba) << 0;
638 etiss_uint8 rd = 0;
639 static BitArrayRange R_rd_0(9, 7);
640 rd += R_rd_0.read(ba) << 0;
641 
642 // -----------------------------------------------------------------------------
643 
644  std::stringstream ss;
645 // -----------------------------------------------------------------------------
646 ss << "caddw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
647 // -----------------------------------------------------------------------------
648  return ss.str();
649  }
650 );
651 
652 // CLDSP -----------------------------------------------------------------------
653 static InstructionDefinition cldsp_uimm_rd (
654  ISA16_RV64IMACFD,
655  "cldsp",
656  (uint16_t) 0x6002,
657  (uint16_t) 0xe003,
658  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
659  {
660 
661 // -----------------------------------------------------------------------------
662 
663 // -----------------------------------------------------------------------------
664 
665 // -----------------------------------------------------------------------------
666 etiss_uint16 uimm = 0;
667 static BitArrayRange R_uimm_6(4, 2);
668 uimm += R_uimm_6.read(ba) << 6;
669 static BitArrayRange R_uimm_3(6, 5);
670 uimm += R_uimm_3.read(ba) << 3;
671 etiss_uint8 rd = 0;
672 static BitArrayRange R_rd_0(11, 7);
673 rd += R_rd_0.read(ba) << 0;
674 static BitArrayRange R_uimm_5(12, 12);
675 uimm += R_uimm_5.read(ba) << 5;
676 
677 // -----------------------------------------------------------------------------
678 
679  {
680  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
681 
682  cp.code() = std::string("//CLDSP\n");
683 
684 // -----------------------------------------------------------------------------
685 { // block
686 cp.code() += "{ // block\n";
687 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
688 cp.code() += "} // block\n";
689 } // block
690 { // block
691 cp.code() += "{ // block\n";
692 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
693 cp.code() += "etiss_uint64 mem_val_0;\n";
694 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
695 cp.code() += "if (cpu->exception) { // conditional\n";
696 { // procedure
697 cp.code() += "{ // procedure\n";
698 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
699 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
700 cp.code() += "} // procedure\n";
701 } // procedure
702 cp.code() += "} // conditional\n";
703 cp.code() += "etiss_int64 res = mem_val_0;\n";
704 if (rd % 32ULL) { // conditional
705 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
706 } // conditional
707 else { // conditional
708 { // procedure
709 cp.code() += "{ // procedure\n";
710 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
711 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
712 cp.code() += "} // procedure\n";
713 } // procedure
714 } // conditional
715 cp.code() += "} // block\n";
716 } // block
717 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
718 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
719 // -----------------------------------------------------------------------------
720  cp.getAffectedRegisters().add("instructionPointer", 32);
721  }
722  {
723  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
724 
725  cp.code() = std::string("//CLDSP\n");
726 
727 // -----------------------------------------------------------------------------
728 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
729 // -----------------------------------------------------------------------------
730  }
731 
732  return true;
733  },
734  0,
735  [] (BitArray & ba, Instruction & instr)
736  {
737 // -----------------------------------------------------------------------------
738 etiss_uint16 uimm = 0;
739 static BitArrayRange R_uimm_6(4, 2);
740 uimm += R_uimm_6.read(ba) << 6;
741 static BitArrayRange R_uimm_3(6, 5);
742 uimm += R_uimm_3.read(ba) << 3;
743 etiss_uint8 rd = 0;
744 static BitArrayRange R_rd_0(11, 7);
745 rd += R_rd_0.read(ba) << 0;
746 static BitArrayRange R_uimm_5(12, 12);
747 uimm += R_uimm_5.read(ba) << 5;
748 
749 // -----------------------------------------------------------------------------
750 
751  std::stringstream ss;
752 // -----------------------------------------------------------------------------
753 ss << "cldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
754 // -----------------------------------------------------------------------------
755  return ss.str();
756  }
757 );
758 
759 // CSDSP -----------------------------------------------------------------------
760 static InstructionDefinition csdsp_rs2_uimm (
761  ISA16_RV64IMACFD,
762  "csdsp",
763  (uint16_t) 0xe002,
764  (uint16_t) 0xe003,
765  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
766  {
767 
768 // -----------------------------------------------------------------------------
769 
770 // -----------------------------------------------------------------------------
771 
772 // -----------------------------------------------------------------------------
773 etiss_uint8 rs2 = 0;
774 static BitArrayRange R_rs2_0(6, 2);
775 rs2 += R_rs2_0.read(ba) << 0;
776 etiss_uint16 uimm = 0;
777 static BitArrayRange R_uimm_6(9, 7);
778 uimm += R_uimm_6.read(ba) << 6;
779 static BitArrayRange R_uimm_3(12, 10);
780 uimm += R_uimm_3.read(ba) << 3;
781 
782 // -----------------------------------------------------------------------------
783 
784  {
785  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
786 
787  cp.code() = std::string("//CSDSP\n");
788 
789 // -----------------------------------------------------------------------------
790 { // block
791 cp.code() += "{ // block\n";
792 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
793 cp.code() += "} // block\n";
794 } // block
795 { // block
796 cp.code() += "{ // block\n";
797 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
798 cp.code() += "etiss_uint64 mem_val_0;\n";
799 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
800 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
801 cp.code() += "if (cpu->exception) { // conditional\n";
802 { // procedure
803 cp.code() += "{ // procedure\n";
804 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
805 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
806 cp.code() += "} // procedure\n";
807 } // procedure
808 cp.code() += "} // conditional\n";
809 cp.code() += "} // block\n";
810 } // block
811 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
812 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
813 // -----------------------------------------------------------------------------
814  cp.getAffectedRegisters().add("instructionPointer", 32);
815  }
816  {
817  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
818 
819  cp.code() = std::string("//CSDSP\n");
820 
821 // -----------------------------------------------------------------------------
822 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
823 // -----------------------------------------------------------------------------
824  }
825 
826  return true;
827  },
828  0,
829  [] (BitArray & ba, Instruction & instr)
830  {
831 // -----------------------------------------------------------------------------
832 etiss_uint8 rs2 = 0;
833 static BitArrayRange R_rs2_0(6, 2);
834 rs2 += R_rs2_0.read(ba) << 0;
835 etiss_uint16 uimm = 0;
836 static BitArrayRange R_uimm_6(9, 7);
837 uimm += R_uimm_6.read(ba) << 6;
838 static BitArrayRange R_uimm_3(12, 10);
839 uimm += R_uimm_3.read(ba) << 3;
840 
841 // -----------------------------------------------------------------------------
842 
843  std::stringstream ss;
844 // -----------------------------------------------------------------------------
845 ss << "csdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
846 // -----------------------------------------------------------------------------
847  return ss.str();
848  }
849 );
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
caddw_rs2_rd
static InstructionDefinition caddw_rs2_rd(ISA16_RV64IMACFD, "caddw",(uint16_t) 0x9c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "caddw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csrai_shamt_rs1
static InstructionDefinition csrai_shamt_rs1(ISA16_RV64IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csubw_rs2_rd
static InstructionDefinition csubw_rs2_rd(ISA16_RV64IMACFD, "csubw",(uint16_t) 0x9c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUBW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csubw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csrli_nzuimm_rs1
static InstructionDefinition csrli_nzuimm_rs1(ISA16_RV64IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(nzuimm)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_nzuimm_5(12, 12);nzuimm+=R_nzuimm_5.read(ba)<< 5;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cld_rd_uimm_rs1
static InstructionDefinition cld_rd_uimm_rs1(ISA16_RV64IMACFD, "cld",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int64)(mem_val_0);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cslli_shamt_rs1
static InstructionDefinition cslli_shamt_rs1(ISA16_RV64IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(rs1==0LL) { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_shamt_5(12, 12);shamt+=R_shamt_5.read(ba)<< 5;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csdsp_rs2_uimm
static InstructionDefinition csdsp_rs2_uimm(ISA16_RV64IMACFD, "csdsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSDSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
caddiw_imm_rs1
static InstructionDefinition caddiw_imm_rs1(ISA16_RV64IMACFD, "caddiw",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDIW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rs1 % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddiw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csd_rs2_uimm_rs1
static InstructionDefinition csd_rs2_uimm_rs1(ISA16_RV64IMACFD, "csd",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cldsp_uimm_rd
static InstructionDefinition cldsp_uimm_rd(ISA16_RV64IMACFD, "cldsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLDSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if(rd % 32ULL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_int8
int8_t etiss_int8
Definition: types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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