ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64FInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FCVT_L_S --------------------------------------------------------------------
16 static InstructionDefinition fcvt_l_s_rd_rm_rs1 (
17  ISA32_RV64IMACFD,
18  "fcvt_l_s",
19  (uint32_t) 0xc0200053,
20  (uint32_t) 0xfff0007f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rm = 0;
33 static BitArrayRange R_rm_0(14, 12);
34 rm += R_rm_0.read(ba) << 0;
35 etiss_uint8 rs1 = 0;
36 static BitArrayRange R_rs1_0(19, 15);
37 rs1 += R_rs1_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FCVT_L_S\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
55 if ((rd % 32ULL) != 0LL) { // conditional
56 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
57 } // conditional
58 cp.code() += "etiss_uint32 flags = fget_flags();\n";
59 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
60 cp.code() += "} // block\n";
61 } // block
62 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
63 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
64 // -----------------------------------------------------------------------------
65  cp.getAffectedRegisters().add("instructionPointer", 32);
66  }
67 
68  return true;
69  },
70  0,
71  [] (BitArray & ba, Instruction & instr)
72  {
73 // -----------------------------------------------------------------------------
74 etiss_uint8 rd = 0;
75 static BitArrayRange R_rd_0(11, 7);
76 rd += R_rd_0.read(ba) << 0;
77 etiss_uint8 rm = 0;
78 static BitArrayRange R_rm_0(14, 12);
79 rm += R_rm_0.read(ba) << 0;
80 etiss_uint8 rs1 = 0;
81 static BitArrayRange R_rs1_0(19, 15);
82 rs1 += R_rs1_0.read(ba) << 0;
83 
84 // -----------------------------------------------------------------------------
85 
86  std::stringstream ss;
87 // -----------------------------------------------------------------------------
88 ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
89 // -----------------------------------------------------------------------------
90  return ss.str();
91  }
92 );
93 
94 // FCVT_LU_S -------------------------------------------------------------------
95 static InstructionDefinition fcvt_lu_s_rd_rm_rs1 (
96  ISA32_RV64IMACFD,
97  "fcvt_lu_s",
98  (uint32_t) 0xc0300053,
99  (uint32_t) 0xfff0007f,
100  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
101  {
102 
103 // -----------------------------------------------------------------------------
104 
105 // -----------------------------------------------------------------------------
106 
107 // -----------------------------------------------------------------------------
108 etiss_uint8 rd = 0;
109 static BitArrayRange R_rd_0(11, 7);
110 rd += R_rd_0.read(ba) << 0;
111 etiss_uint8 rm = 0;
112 static BitArrayRange R_rm_0(14, 12);
113 rm += R_rm_0.read(ba) << 0;
114 etiss_uint8 rs1 = 0;
115 static BitArrayRange R_rs1_0(19, 15);
116 rs1 += R_rs1_0.read(ba) << 0;
117 
118 // -----------------------------------------------------------------------------
119 
120  {
121  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
122 
123  cp.code() = std::string("//FCVT_LU_S\n");
124 
125 // -----------------------------------------------------------------------------
126 { // block
127 cp.code() += "{ // block\n";
128 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
129 cp.code() += "} // block\n";
130 } // block
131 { // block
132 cp.code() += "{ // block\n";
133 cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
134 if ((rd % 32ULL) != 0LL) { // conditional
135 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
136 } // conditional
137 cp.code() += "etiss_uint32 flags = fget_flags();\n";
138 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
139 cp.code() += "} // block\n";
140 } // block
141 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
142 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
143 // -----------------------------------------------------------------------------
144  cp.getAffectedRegisters().add("instructionPointer", 32);
145  }
146 
147  return true;
148  },
149  0,
150  [] (BitArray & ba, Instruction & instr)
151  {
152 // -----------------------------------------------------------------------------
153 etiss_uint8 rd = 0;
154 static BitArrayRange R_rd_0(11, 7);
155 rd += R_rd_0.read(ba) << 0;
156 etiss_uint8 rm = 0;
157 static BitArrayRange R_rm_0(14, 12);
158 rm += R_rm_0.read(ba) << 0;
159 etiss_uint8 rs1 = 0;
160 static BitArrayRange R_rs1_0(19, 15);
161 rs1 += R_rs1_0.read(ba) << 0;
162 
163 // -----------------------------------------------------------------------------
164 
165  std::stringstream ss;
166 // -----------------------------------------------------------------------------
167 ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
168 // -----------------------------------------------------------------------------
169  return ss.str();
170  }
171 );
172 
173 // FCVT_S_L --------------------------------------------------------------------
174 static InstructionDefinition fcvt_s_l_rd_rm_rs1 (
175  ISA32_RV64IMACFD,
176  "fcvt_s_l",
177  (uint32_t) 0xd0200053,
178  (uint32_t) 0xfff0007f,
179  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
180  {
181 
182 // -----------------------------------------------------------------------------
183 
184 // -----------------------------------------------------------------------------
185 
186 // -----------------------------------------------------------------------------
187 etiss_uint8 rd = 0;
188 static BitArrayRange R_rd_0(11, 7);
189 rd += R_rd_0.read(ba) << 0;
190 etiss_uint8 rm = 0;
191 static BitArrayRange R_rm_0(14, 12);
192 rm += R_rm_0.read(ba) << 0;
193 etiss_uint8 rs1 = 0;
194 static BitArrayRange R_rs1_0(19, 15);
195 rs1 += R_rs1_0.read(ba) << 0;
196 
197 // -----------------------------------------------------------------------------
198 
199  {
200  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
201 
202  cp.code() = std::string("//FCVT_S_L\n");
203 
204 // -----------------------------------------------------------------------------
205 { // block
206 cp.code() += "{ // block\n";
207 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
208 cp.code() += "} // block\n";
209 } // block
210 { // block
211 cp.code() += "{ // block\n";
212 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
213 { // block
214 cp.code() += "{ // block\n";
215 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
216 cp.code() += "} // block\n";
217 } // block
218 cp.code() += "} // block\n";
219 } // block
220 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
221 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
222 // -----------------------------------------------------------------------------
223  cp.getAffectedRegisters().add("instructionPointer", 32);
224  }
225 
226  return true;
227  },
228  0,
229  [] (BitArray & ba, Instruction & instr)
230  {
231 // -----------------------------------------------------------------------------
232 etiss_uint8 rd = 0;
233 static BitArrayRange R_rd_0(11, 7);
234 rd += R_rd_0.read(ba) << 0;
235 etiss_uint8 rm = 0;
236 static BitArrayRange R_rm_0(14, 12);
237 rm += R_rm_0.read(ba) << 0;
238 etiss_uint8 rs1 = 0;
239 static BitArrayRange R_rs1_0(19, 15);
240 rs1 += R_rs1_0.read(ba) << 0;
241 
242 // -----------------------------------------------------------------------------
243 
244  std::stringstream ss;
245 // -----------------------------------------------------------------------------
246 ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
247 // -----------------------------------------------------------------------------
248  return ss.str();
249  }
250 );
251 
252 // FCVT_S_LU -------------------------------------------------------------------
253 static InstructionDefinition fcvt_s_lu_rd_rm_rs1 (
254  ISA32_RV64IMACFD,
255  "fcvt_s_lu",
256  (uint32_t) 0xd0300053,
257  (uint32_t) 0xfff0007f,
258  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
259  {
260 
261 // -----------------------------------------------------------------------------
262 
263 // -----------------------------------------------------------------------------
264 
265 // -----------------------------------------------------------------------------
266 etiss_uint8 rd = 0;
267 static BitArrayRange R_rd_0(11, 7);
268 rd += R_rd_0.read(ba) << 0;
269 etiss_uint8 rm = 0;
270 static BitArrayRange R_rm_0(14, 12);
271 rm += R_rm_0.read(ba) << 0;
272 etiss_uint8 rs1 = 0;
273 static BitArrayRange R_rs1_0(19, 15);
274 rs1 += R_rs1_0.read(ba) << 0;
275 
276 // -----------------------------------------------------------------------------
277 
278  {
279  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
280 
281  cp.code() = std::string("//FCVT_S_LU\n");
282 
283 // -----------------------------------------------------------------------------
284 { // block
285 cp.code() += "{ // block\n";
286 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
287 cp.code() += "} // block\n";
288 } // block
289 { // block
290 cp.code() += "{ // block\n";
291 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
292 { // block
293 cp.code() += "{ // block\n";
294 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
295 cp.code() += "} // block\n";
296 } // block
297 cp.code() += "} // block\n";
298 } // block
299 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
300 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
301 // -----------------------------------------------------------------------------
302  cp.getAffectedRegisters().add("instructionPointer", 32);
303  }
304 
305  return true;
306  },
307  0,
308  [] (BitArray & ba, Instruction & instr)
309  {
310 // -----------------------------------------------------------------------------
311 etiss_uint8 rd = 0;
312 static BitArrayRange R_rd_0(11, 7);
313 rd += R_rd_0.read(ba) << 0;
314 etiss_uint8 rm = 0;
315 static BitArrayRange R_rm_0(14, 12);
316 rm += R_rm_0.read(ba) << 0;
317 etiss_uint8 rs1 = 0;
318 static BitArrayRange R_rs1_0(19, 15);
319 rs1 += R_rs1_0.read(ba) << 0;
320 
321 // -----------------------------------------------------------------------------
322 
323  std::stringstream ss;
324 // -----------------------------------------------------------------------------
325 ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
326 // -----------------------------------------------------------------------------
327  return ss.str();
328  }
329 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_s_lu_rd_rm_rs1
static InstructionDefinition fcvt_s_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_LU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";{ cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_s_rd_rm_rs1
static InstructionDefinition fcvt_lu_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_l_s_rd_rm_rs1
static InstructionDefinition fcvt_l_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_l_rd_rm_rs1
static InstructionDefinition fcvt_s_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_L\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";{ cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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