ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_RV64FInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// FCVT_L_S --------------------------------------------------------------------
16static InstructionDefinition fcvt_l_s_rd_rm_rs1 (
17 ISA32_RV64IMACFD,
18 "fcvt_l_s",
19 (uint32_t) 0xc0200053,
20 (uint32_t) 0xfff0007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rm = 0;
34static BitArrayRange R_rm_0(14, 12);
35rm += R_rm_0.read(ba) << 0;
36etiss_uint8 rs1 = 0;
37static BitArrayRange R_rs1_0(19, 15);
38rs1 += R_rs1_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//FCVT_L_S\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 214);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1169);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
54cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 8103);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
61cp.code() += "etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";
62cp.code() += "etiss_coverage_count(1, 8074);\n";
63if ((rd % 32ULL) != 0LL) { // conditional
64cp.code() += "etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";
65cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
66cp.code() += "etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";
67} // conditional
68cp.code() += "etiss_uint32 flags = fget_flags();\n";
69cp.code() += "etiss_coverage_count(2, 8090, 8089);\n";
70cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
71cp.code() += "etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";
72cp.code() += "} // block\n";
73} // block
74cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
75cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
76// -----------------------------------------------------------------------------
77 cp.getAffectedRegisters().add("instructionPointer", 32);
78 }
79
80 return true;
81 },
82 0,
83 [] (BitArray & ba, Instruction & instr)
84 {
85// -----------------------------------------------------------------------------
86etiss_uint8 rd = 0;
87static BitArrayRange R_rd_0(11, 7);
88rd += R_rd_0.read(ba) << 0;
89etiss_uint8 rm = 0;
90static BitArrayRange R_rm_0(14, 12);
91rm += R_rm_0.read(ba) << 0;
92etiss_uint8 rs1 = 0;
93static BitArrayRange R_rs1_0(19, 15);
94rs1 += R_rs1_0.read(ba) << 0;
95
96// -----------------------------------------------------------------------------
97
98 std::stringstream ss;
99// -----------------------------------------------------------------------------
100ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
101// -----------------------------------------------------------------------------
102 return ss.str();
103 }
104);
105
106// FCVT_LU_S -------------------------------------------------------------------
107static InstructionDefinition fcvt_lu_s_rd_rm_rs1 (
108 ISA32_RV64IMACFD,
109 "fcvt_lu_s",
110 (uint32_t) 0xc0300053,
111 (uint32_t) 0xfff0007f,
112 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
113 {
114
115// -----------------------------------------------------------------------------
116
117// -----------------------------------------------------------------------------
118
119// -----------------------------------------------------------------------------
120// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
121etiss_uint8 rd = 0;
122static BitArrayRange R_rd_0(11, 7);
123rd += R_rd_0.read(ba) << 0;
124etiss_uint8 rm = 0;
125static BitArrayRange R_rm_0(14, 12);
126rm += R_rm_0.read(ba) << 0;
127etiss_uint8 rs1 = 0;
128static BitArrayRange R_rs1_0(19, 15);
129rs1 += R_rs1_0.read(ba) << 0;
130
131// NOLINTEND(clang-diagnostic-unused-but-set-variable)
132// -----------------------------------------------------------------------------
133
134 {
135 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
136
137 cp.code() = std::string("//FCVT_LU_S\n");
138
139// -----------------------------------------------------------------------------
140cp.code() += "etiss_coverage_count(1, 215);\n";
141{ // block
142cp.code() += "etiss_coverage_count(1, 1169);\n";
143cp.code() += "{ // block\n";
144cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
145cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
146cp.code() += "} // block\n";
147} // block
148{ // block
149cp.code() += "etiss_coverage_count(1, 8142);\n";
150cp.code() += "{ // block\n";
151cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
152cp.code() += "etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";
153cp.code() += "etiss_coverage_count(1, 8113);\n";
154if ((rd % 32ULL) != 0LL) { // conditional
155cp.code() += "etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";
156cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
157cp.code() += "etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";
158} // conditional
159cp.code() += "etiss_uint32 flags = fget_flags();\n";
160cp.code() += "etiss_coverage_count(2, 8129, 8128);\n";
161cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
162cp.code() += "etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";
163cp.code() += "} // block\n";
164} // block
165cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
166cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
167// -----------------------------------------------------------------------------
168 cp.getAffectedRegisters().add("instructionPointer", 32);
169 }
170
171 return true;
172 },
173 0,
174 [] (BitArray & ba, Instruction & instr)
175 {
176// -----------------------------------------------------------------------------
177etiss_uint8 rd = 0;
178static BitArrayRange R_rd_0(11, 7);
179rd += R_rd_0.read(ba) << 0;
180etiss_uint8 rm = 0;
181static BitArrayRange R_rm_0(14, 12);
182rm += R_rm_0.read(ba) << 0;
183etiss_uint8 rs1 = 0;
184static BitArrayRange R_rs1_0(19, 15);
185rs1 += R_rs1_0.read(ba) << 0;
186
187// -----------------------------------------------------------------------------
188
189 std::stringstream ss;
190// -----------------------------------------------------------------------------
191ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
192// -----------------------------------------------------------------------------
193 return ss.str();
194 }
195);
196
197// FCVT_S_L --------------------------------------------------------------------
198static InstructionDefinition fcvt_s_l_rd_rm_rs1 (
199 ISA32_RV64IMACFD,
200 "fcvt_s_l",
201 (uint32_t) 0xd0200053,
202 (uint32_t) 0xfff0007f,
203 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
204 {
205
206// -----------------------------------------------------------------------------
207
208// -----------------------------------------------------------------------------
209
210// -----------------------------------------------------------------------------
211// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
212etiss_uint8 rd = 0;
213static BitArrayRange R_rd_0(11, 7);
214rd += R_rd_0.read(ba) << 0;
215etiss_uint8 rm = 0;
216static BitArrayRange R_rm_0(14, 12);
217rm += R_rm_0.read(ba) << 0;
218etiss_uint8 rs1 = 0;
219static BitArrayRange R_rs1_0(19, 15);
220rs1 += R_rs1_0.read(ba) << 0;
221
222// NOLINTEND(clang-diagnostic-unused-but-set-variable)
223// -----------------------------------------------------------------------------
224
225 {
226 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
227
228 cp.code() = std::string("//FCVT_S_L\n");
229
230// -----------------------------------------------------------------------------
231cp.code() += "etiss_coverage_count(1, 216);\n";
232{ // block
233cp.code() += "etiss_coverage_count(1, 1169);\n";
234cp.code() += "{ // block\n";
235cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
236cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
237cp.code() += "} // block\n";
238} // block
239{ // block
240cp.code() += "etiss_coverage_count(1, 8178);\n";
241cp.code() += "{ // block\n";
242cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
243cp.code() += "etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";
244{ // block
245cp.code() += "etiss_coverage_count(1, 8177);\n";
246cp.code() += "{ // block\n";
247cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
248cp.code() += "etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";
249cp.code() += "} // block\n";
250} // block
251cp.code() += "} // block\n";
252} // block
253cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
254cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
255// -----------------------------------------------------------------------------
256 cp.getAffectedRegisters().add("instructionPointer", 32);
257 }
258
259 return true;
260 },
261 0,
262 [] (BitArray & ba, Instruction & instr)
263 {
264// -----------------------------------------------------------------------------
265etiss_uint8 rd = 0;
266static BitArrayRange R_rd_0(11, 7);
267rd += R_rd_0.read(ba) << 0;
268etiss_uint8 rm = 0;
269static BitArrayRange R_rm_0(14, 12);
270rm += R_rm_0.read(ba) << 0;
271etiss_uint8 rs1 = 0;
272static BitArrayRange R_rs1_0(19, 15);
273rs1 += R_rs1_0.read(ba) << 0;
274
275// -----------------------------------------------------------------------------
276
277 std::stringstream ss;
278// -----------------------------------------------------------------------------
279ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
280// -----------------------------------------------------------------------------
281 return ss.str();
282 }
283);
284
285// FCVT_S_LU -------------------------------------------------------------------
286static InstructionDefinition fcvt_s_lu_rd_rm_rs1 (
287 ISA32_RV64IMACFD,
288 "fcvt_s_lu",
289 (uint32_t) 0xd0300053,
290 (uint32_t) 0xfff0007f,
291 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
292 {
293
294// -----------------------------------------------------------------------------
295
296// -----------------------------------------------------------------------------
297
298// -----------------------------------------------------------------------------
299// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
300etiss_uint8 rd = 0;
301static BitArrayRange R_rd_0(11, 7);
302rd += R_rd_0.read(ba) << 0;
303etiss_uint8 rm = 0;
304static BitArrayRange R_rm_0(14, 12);
305rm += R_rm_0.read(ba) << 0;
306etiss_uint8 rs1 = 0;
307static BitArrayRange R_rs1_0(19, 15);
308rs1 += R_rs1_0.read(ba) << 0;
309
310// NOLINTEND(clang-diagnostic-unused-but-set-variable)
311// -----------------------------------------------------------------------------
312
313 {
314 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
315
316 cp.code() = std::string("//FCVT_S_LU\n");
317
318// -----------------------------------------------------------------------------
319cp.code() += "etiss_coverage_count(1, 217);\n";
320{ // block
321cp.code() += "etiss_coverage_count(1, 1169);\n";
322cp.code() += "{ // block\n";
323cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
324cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
325cp.code() += "} // block\n";
326} // block
327{ // block
328cp.code() += "etiss_coverage_count(1, 8214);\n";
329cp.code() += "{ // block\n";
330cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
331cp.code() += "etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";
332{ // block
333cp.code() += "etiss_coverage_count(1, 8213);\n";
334cp.code() += "{ // block\n";
335cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
336cp.code() += "etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";
337cp.code() += "} // block\n";
338} // block
339cp.code() += "} // block\n";
340} // block
341cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
342cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
343// -----------------------------------------------------------------------------
344 cp.getAffectedRegisters().add("instructionPointer", 32);
345 }
346
347 return true;
348 },
349 0,
350 [] (BitArray & ba, Instruction & instr)
351 {
352// -----------------------------------------------------------------------------
353etiss_uint8 rd = 0;
354static BitArrayRange R_rd_0(11, 7);
355rd += R_rd_0.read(ba) << 0;
356etiss_uint8 rm = 0;
357static BitArrayRange R_rm_0(14, 12);
358rm += R_rm_0.read(ba) << 0;
359etiss_uint8 rs1 = 0;
360static BitArrayRange R_rs1_0(19, 15);
361rs1 += R_rs1_0.read(ba) << 0;
362
363// -----------------------------------------------------------------------------
364
365 std::stringstream ss;
366// -----------------------------------------------------------------------------
367ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
368// -----------------------------------------------------------------------------
369 return ss.str();
370 }
371);
372// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_s_l_rd_rm_rs1
static InstructionDefinition fcvt_s_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_L\n");cp.code()+="etiss_coverage_count(1, 216);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8178);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";{ cp.code()+="etiss_coverage_count(1, 8177);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_lu_rd_rm_rs1
static InstructionDefinition fcvt_s_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_LU\n");cp.code()+="etiss_coverage_count(1, 217);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";{ cp.code()+="etiss_coverage_count(1, 8213);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_l_s_rd_rm_rs1
static InstructionDefinition fcvt_l_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_S\n");cp.code()+="etiss_coverage_count(1, 214);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8103);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";cp.code()+="etiss_coverage_count(1, 8074);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8090, 8089);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_s_rd_rm_rs1
static InstructionDefinition fcvt_lu_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_S\n");cp.code()+="etiss_coverage_count(1, 215);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8142);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";cp.code()+="etiss_coverage_count(1, 8113);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8129, 8128);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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