ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV64IMACFD_RV64FInstr.cpp
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1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// FCVT_L_S --------------------------------------------------------------------
16static InstructionDefinition fcvt_l_s_rd_rm_rs1 (
17 ISA32_RV64IMACFD,
18 "fcvt_l_s",
19 (uint32_t) 0xc0200053,
20 (uint32_t) 0xfff0007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rm = 0;
33static BitArrayRange R_rm_0(14, 12);
34rm += R_rm_0.read(ba) << 0;
35etiss_uint8 rs1 = 0;
36static BitArrayRange R_rs1_0(19, 15);
37rs1 += R_rs1_0.read(ba) << 0;
38
39// -----------------------------------------------------------------------------
40
41 {
42 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43
44 cp.code() = std::string("//FCVT_L_S\n");
45
46// -----------------------------------------------------------------------------
47cp.code() += "etiss_coverage_count(1, 214);\n";
48{ // block
49cp.code() += "etiss_coverage_count(1, 1169);\n";
50cp.code() += "{ // block\n";
51cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53cp.code() += "} // block\n";
54} // block
55{ // block
56cp.code() += "etiss_coverage_count(1, 8103);\n";
57cp.code() += "{ // block\n";
58cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
59cp.code() += "etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";
60cp.code() += "etiss_coverage_count(1, 8074);\n";
61if ((rd % 32ULL) != 0LL) { // conditional
62cp.code() += "etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";
63cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
64cp.code() += "etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";
65} // conditional
66cp.code() += "etiss_uint32 flags = fget_flags();\n";
67cp.code() += "etiss_coverage_count(2, 8090, 8089);\n";
68cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
69cp.code() += "etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";
70cp.code() += "} // block\n";
71} // block
72cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
73cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
74// -----------------------------------------------------------------------------
75 cp.getAffectedRegisters().add("instructionPointer", 32);
76 }
77
78 return true;
79 },
80 0,
81 [] (BitArray & ba, Instruction & instr)
82 {
83// -----------------------------------------------------------------------------
84etiss_uint8 rd = 0;
85static BitArrayRange R_rd_0(11, 7);
86rd += R_rd_0.read(ba) << 0;
87etiss_uint8 rm = 0;
88static BitArrayRange R_rm_0(14, 12);
89rm += R_rm_0.read(ba) << 0;
90etiss_uint8 rs1 = 0;
91static BitArrayRange R_rs1_0(19, 15);
92rs1 += R_rs1_0.read(ba) << 0;
93
94// -----------------------------------------------------------------------------
95
96 std::stringstream ss;
97// -----------------------------------------------------------------------------
98ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
99// -----------------------------------------------------------------------------
100 return ss.str();
101 }
102);
103
104// FCVT_LU_S -------------------------------------------------------------------
105static InstructionDefinition fcvt_lu_s_rd_rm_rs1 (
106 ISA32_RV64IMACFD,
107 "fcvt_lu_s",
108 (uint32_t) 0xc0300053,
109 (uint32_t) 0xfff0007f,
110 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
111 {
112
113// -----------------------------------------------------------------------------
114
115// -----------------------------------------------------------------------------
116
117// -----------------------------------------------------------------------------
118etiss_uint8 rd = 0;
119static BitArrayRange R_rd_0(11, 7);
120rd += R_rd_0.read(ba) << 0;
121etiss_uint8 rm = 0;
122static BitArrayRange R_rm_0(14, 12);
123rm += R_rm_0.read(ba) << 0;
124etiss_uint8 rs1 = 0;
125static BitArrayRange R_rs1_0(19, 15);
126rs1 += R_rs1_0.read(ba) << 0;
127
128// -----------------------------------------------------------------------------
129
130 {
131 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
132
133 cp.code() = std::string("//FCVT_LU_S\n");
134
135// -----------------------------------------------------------------------------
136cp.code() += "etiss_coverage_count(1, 215);\n";
137{ // block
138cp.code() += "etiss_coverage_count(1, 1169);\n";
139cp.code() += "{ // block\n";
140cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
141cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
142cp.code() += "} // block\n";
143} // block
144{ // block
145cp.code() += "etiss_coverage_count(1, 8142);\n";
146cp.code() += "{ // block\n";
147cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
148cp.code() += "etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";
149cp.code() += "etiss_coverage_count(1, 8113);\n";
150if ((rd % 32ULL) != 0LL) { // conditional
151cp.code() += "etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";
152cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
153cp.code() += "etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";
154} // conditional
155cp.code() += "etiss_uint32 flags = fget_flags();\n";
156cp.code() += "etiss_coverage_count(2, 8129, 8128);\n";
157cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
158cp.code() += "etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";
159cp.code() += "} // block\n";
160} // block
161cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
162cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
163// -----------------------------------------------------------------------------
164 cp.getAffectedRegisters().add("instructionPointer", 32);
165 }
166
167 return true;
168 },
169 0,
170 [] (BitArray & ba, Instruction & instr)
171 {
172// -----------------------------------------------------------------------------
173etiss_uint8 rd = 0;
174static BitArrayRange R_rd_0(11, 7);
175rd += R_rd_0.read(ba) << 0;
176etiss_uint8 rm = 0;
177static BitArrayRange R_rm_0(14, 12);
178rm += R_rm_0.read(ba) << 0;
179etiss_uint8 rs1 = 0;
180static BitArrayRange R_rs1_0(19, 15);
181rs1 += R_rs1_0.read(ba) << 0;
182
183// -----------------------------------------------------------------------------
184
185 std::stringstream ss;
186// -----------------------------------------------------------------------------
187ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
188// -----------------------------------------------------------------------------
189 return ss.str();
190 }
191);
192
193// FCVT_S_L --------------------------------------------------------------------
194static InstructionDefinition fcvt_s_l_rd_rm_rs1 (
195 ISA32_RV64IMACFD,
196 "fcvt_s_l",
197 (uint32_t) 0xd0200053,
198 (uint32_t) 0xfff0007f,
199 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
200 {
201
202// -----------------------------------------------------------------------------
203
204// -----------------------------------------------------------------------------
205
206// -----------------------------------------------------------------------------
207etiss_uint8 rd = 0;
208static BitArrayRange R_rd_0(11, 7);
209rd += R_rd_0.read(ba) << 0;
210etiss_uint8 rm = 0;
211static BitArrayRange R_rm_0(14, 12);
212rm += R_rm_0.read(ba) << 0;
213etiss_uint8 rs1 = 0;
214static BitArrayRange R_rs1_0(19, 15);
215rs1 += R_rs1_0.read(ba) << 0;
216
217// -----------------------------------------------------------------------------
218
219 {
220 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
221
222 cp.code() = std::string("//FCVT_S_L\n");
223
224// -----------------------------------------------------------------------------
225cp.code() += "etiss_coverage_count(1, 216);\n";
226{ // block
227cp.code() += "etiss_coverage_count(1, 1169);\n";
228cp.code() += "{ // block\n";
229cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
230cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
231cp.code() += "} // block\n";
232} // block
233{ // block
234cp.code() += "etiss_coverage_count(1, 8178);\n";
235cp.code() += "{ // block\n";
236cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
237cp.code() += "etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";
238{ // block
239cp.code() += "etiss_coverage_count(1, 8177);\n";
240cp.code() += "{ // block\n";
241cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
242cp.code() += "etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";
243cp.code() += "} // block\n";
244} // block
245cp.code() += "} // block\n";
246} // block
247cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
248cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
249// -----------------------------------------------------------------------------
250 cp.getAffectedRegisters().add("instructionPointer", 32);
251 }
252
253 return true;
254 },
255 0,
256 [] (BitArray & ba, Instruction & instr)
257 {
258// -----------------------------------------------------------------------------
259etiss_uint8 rd = 0;
260static BitArrayRange R_rd_0(11, 7);
261rd += R_rd_0.read(ba) << 0;
262etiss_uint8 rm = 0;
263static BitArrayRange R_rm_0(14, 12);
264rm += R_rm_0.read(ba) << 0;
265etiss_uint8 rs1 = 0;
266static BitArrayRange R_rs1_0(19, 15);
267rs1 += R_rs1_0.read(ba) << 0;
268
269// -----------------------------------------------------------------------------
270
271 std::stringstream ss;
272// -----------------------------------------------------------------------------
273ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
274// -----------------------------------------------------------------------------
275 return ss.str();
276 }
277);
278
279// FCVT_S_LU -------------------------------------------------------------------
280static InstructionDefinition fcvt_s_lu_rd_rm_rs1 (
281 ISA32_RV64IMACFD,
282 "fcvt_s_lu",
283 (uint32_t) 0xd0300053,
284 (uint32_t) 0xfff0007f,
285 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
286 {
287
288// -----------------------------------------------------------------------------
289
290// -----------------------------------------------------------------------------
291
292// -----------------------------------------------------------------------------
293etiss_uint8 rd = 0;
294static BitArrayRange R_rd_0(11, 7);
295rd += R_rd_0.read(ba) << 0;
296etiss_uint8 rm = 0;
297static BitArrayRange R_rm_0(14, 12);
298rm += R_rm_0.read(ba) << 0;
299etiss_uint8 rs1 = 0;
300static BitArrayRange R_rs1_0(19, 15);
301rs1 += R_rs1_0.read(ba) << 0;
302
303// -----------------------------------------------------------------------------
304
305 {
306 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
307
308 cp.code() = std::string("//FCVT_S_LU\n");
309
310// -----------------------------------------------------------------------------
311cp.code() += "etiss_coverage_count(1, 217);\n";
312{ // block
313cp.code() += "etiss_coverage_count(1, 1169);\n";
314cp.code() += "{ // block\n";
315cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
316cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
317cp.code() += "} // block\n";
318} // block
319{ // block
320cp.code() += "etiss_coverage_count(1, 8214);\n";
321cp.code() += "{ // block\n";
322cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
323cp.code() += "etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";
324{ // block
325cp.code() += "etiss_coverage_count(1, 8213);\n";
326cp.code() += "{ // block\n";
327cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
328cp.code() += "etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";
329cp.code() += "} // block\n";
330} // block
331cp.code() += "} // block\n";
332} // block
333cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
334cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
335// -----------------------------------------------------------------------------
336 cp.getAffectedRegisters().add("instructionPointer", 32);
337 }
338
339 return true;
340 },
341 0,
342 [] (BitArray & ba, Instruction & instr)
343 {
344// -----------------------------------------------------------------------------
345etiss_uint8 rd = 0;
346static BitArrayRange R_rd_0(11, 7);
347rd += R_rd_0.read(ba) << 0;
348etiss_uint8 rm = 0;
349static BitArrayRange R_rm_0(14, 12);
350rm += R_rm_0.read(ba) << 0;
351etiss_uint8 rs1 = 0;
352static BitArrayRange R_rs1_0(19, 15);
353rs1 += R_rs1_0.read(ba) << 0;
354
355// -----------------------------------------------------------------------------
356
357 std::stringstream ss;
358// -----------------------------------------------------------------------------
359ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
360// -----------------------------------------------------------------------------
361 return ss.str();
362 }
363);
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_s_l_rd_rm_rs1
static InstructionDefinition fcvt_s_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_L\n");cp.code()+="etiss_coverage_count(1, 216);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8178);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";{ cp.code()+="etiss_coverage_count(1, 8177);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_lu_rd_rm_rs1
static InstructionDefinition fcvt_s_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_LU\n");cp.code()+="etiss_coverage_count(1, 217);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";{ cp.code()+="etiss_coverage_count(1, 8213);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_l_s_rd_rm_rs1
static InstructionDefinition fcvt_l_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_S\n");cp.code()+="etiss_coverage_count(1, 214);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8103);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";cp.code()+="etiss_coverage_count(1, 8074);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8090, 8089);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_s_rd_rm_rs1
static InstructionDefinition fcvt_lu_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_S\n");cp.code()+="etiss_coverage_count(1, 215);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8142);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";cp.code()+="etiss_coverage_count(1, 8113);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8129, 8128);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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