ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64FInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FCVT_L_S --------------------------------------------------------------------
16 static InstructionDefinition fcvt_l_s_rd_rm_rs1 (
17  ISA32_RV64IMACFD,
18  "fcvt_l_s",
19  (uint32_t) 0xc0200053,
20  (uint32_t) 0xfff0007f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rm = 0;
33 static BitArrayRange R_rm_0(14, 12);
34 rm += R_rm_0.read(ba) << 0;
35 etiss_uint8 rs1 = 0;
36 static BitArrayRange R_rs1_0(19, 15);
37 rs1 += R_rs1_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FCVT_L_S\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 214);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 8103);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
59 cp.code() += "etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";
60 cp.code() += "etiss_coverage_count(1, 8074);\n";
61 if ((rd % 32ULL) != 0LL) { // conditional
62 cp.code() += "etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";
63 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
64 cp.code() += "etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";
65 } // conditional
66 cp.code() += "etiss_uint32 flags = fget_flags();\n";
67 cp.code() += "etiss_coverage_count(2, 8090, 8089);\n";
68 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
69 cp.code() += "etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";
70 cp.code() += "} // block\n";
71 } // block
72 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
73 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
74 // -----------------------------------------------------------------------------
75  cp.getAffectedRegisters().add("instructionPointer", 32);
76  }
77 
78  return true;
79  },
80  0,
81  [] (BitArray & ba, Instruction & instr)
82  {
83 // -----------------------------------------------------------------------------
84 etiss_uint8 rd = 0;
85 static BitArrayRange R_rd_0(11, 7);
86 rd += R_rd_0.read(ba) << 0;
87 etiss_uint8 rm = 0;
88 static BitArrayRange R_rm_0(14, 12);
89 rm += R_rm_0.read(ba) << 0;
90 etiss_uint8 rs1 = 0;
91 static BitArrayRange R_rs1_0(19, 15);
92 rs1 += R_rs1_0.read(ba) << 0;
93 
94 // -----------------------------------------------------------------------------
95 
96  std::stringstream ss;
97 // -----------------------------------------------------------------------------
98 ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
99 // -----------------------------------------------------------------------------
100  return ss.str();
101  }
102 );
103 
104 // FCVT_LU_S -------------------------------------------------------------------
105 static InstructionDefinition fcvt_lu_s_rd_rm_rs1 (
106  ISA32_RV64IMACFD,
107  "fcvt_lu_s",
108  (uint32_t) 0xc0300053,
109  (uint32_t) 0xfff0007f,
110  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
111  {
112 
113 // -----------------------------------------------------------------------------
114 
115 // -----------------------------------------------------------------------------
116 
117 // -----------------------------------------------------------------------------
118 etiss_uint8 rd = 0;
119 static BitArrayRange R_rd_0(11, 7);
120 rd += R_rd_0.read(ba) << 0;
121 etiss_uint8 rm = 0;
122 static BitArrayRange R_rm_0(14, 12);
123 rm += R_rm_0.read(ba) << 0;
124 etiss_uint8 rs1 = 0;
125 static BitArrayRange R_rs1_0(19, 15);
126 rs1 += R_rs1_0.read(ba) << 0;
127 
128 // -----------------------------------------------------------------------------
129 
130  {
131  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
132 
133  cp.code() = std::string("//FCVT_LU_S\n");
134 
135 // -----------------------------------------------------------------------------
136 cp.code() += "etiss_coverage_count(1, 215);\n";
137 { // block
138 cp.code() += "etiss_coverage_count(1, 1169);\n";
139 cp.code() += "{ // block\n";
140 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
141 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
142 cp.code() += "} // block\n";
143 } // block
144 { // block
145 cp.code() += "etiss_coverage_count(1, 8142);\n";
146 cp.code() += "{ // block\n";
147 cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
148 cp.code() += "etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";
149 cp.code() += "etiss_coverage_count(1, 8113);\n";
150 if ((rd % 32ULL) != 0LL) { // conditional
151 cp.code() += "etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";
152 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
153 cp.code() += "etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";
154 } // conditional
155 cp.code() += "etiss_uint32 flags = fget_flags();\n";
156 cp.code() += "etiss_coverage_count(2, 8129, 8128);\n";
157 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
158 cp.code() += "etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";
159 cp.code() += "} // block\n";
160 } // block
161 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
162 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
163 // -----------------------------------------------------------------------------
164  cp.getAffectedRegisters().add("instructionPointer", 32);
165  }
166 
167  return true;
168  },
169  0,
170  [] (BitArray & ba, Instruction & instr)
171  {
172 // -----------------------------------------------------------------------------
173 etiss_uint8 rd = 0;
174 static BitArrayRange R_rd_0(11, 7);
175 rd += R_rd_0.read(ba) << 0;
176 etiss_uint8 rm = 0;
177 static BitArrayRange R_rm_0(14, 12);
178 rm += R_rm_0.read(ba) << 0;
179 etiss_uint8 rs1 = 0;
180 static BitArrayRange R_rs1_0(19, 15);
181 rs1 += R_rs1_0.read(ba) << 0;
182 
183 // -----------------------------------------------------------------------------
184 
185  std::stringstream ss;
186 // -----------------------------------------------------------------------------
187 ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
188 // -----------------------------------------------------------------------------
189  return ss.str();
190  }
191 );
192 
193 // FCVT_S_L --------------------------------------------------------------------
194 static InstructionDefinition fcvt_s_l_rd_rm_rs1 (
195  ISA32_RV64IMACFD,
196  "fcvt_s_l",
197  (uint32_t) 0xd0200053,
198  (uint32_t) 0xfff0007f,
199  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
200  {
201 
202 // -----------------------------------------------------------------------------
203 
204 // -----------------------------------------------------------------------------
205 
206 // -----------------------------------------------------------------------------
207 etiss_uint8 rd = 0;
208 static BitArrayRange R_rd_0(11, 7);
209 rd += R_rd_0.read(ba) << 0;
210 etiss_uint8 rm = 0;
211 static BitArrayRange R_rm_0(14, 12);
212 rm += R_rm_0.read(ba) << 0;
213 etiss_uint8 rs1 = 0;
214 static BitArrayRange R_rs1_0(19, 15);
215 rs1 += R_rs1_0.read(ba) << 0;
216 
217 // -----------------------------------------------------------------------------
218 
219  {
220  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
221 
222  cp.code() = std::string("//FCVT_S_L\n");
223 
224 // -----------------------------------------------------------------------------
225 cp.code() += "etiss_coverage_count(1, 216);\n";
226 { // block
227 cp.code() += "etiss_coverage_count(1, 1169);\n";
228 cp.code() += "{ // block\n";
229 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
230 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
231 cp.code() += "} // block\n";
232 } // block
233 { // block
234 cp.code() += "etiss_coverage_count(1, 8178);\n";
235 cp.code() += "{ // block\n";
236 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
237 cp.code() += "etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";
238 { // block
239 cp.code() += "etiss_coverage_count(1, 8177);\n";
240 cp.code() += "{ // block\n";
241 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
242 cp.code() += "etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";
243 cp.code() += "} // block\n";
244 } // block
245 cp.code() += "} // block\n";
246 } // block
247 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
248 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
249 // -----------------------------------------------------------------------------
250  cp.getAffectedRegisters().add("instructionPointer", 32);
251  }
252 
253  return true;
254  },
255  0,
256  [] (BitArray & ba, Instruction & instr)
257  {
258 // -----------------------------------------------------------------------------
259 etiss_uint8 rd = 0;
260 static BitArrayRange R_rd_0(11, 7);
261 rd += R_rd_0.read(ba) << 0;
262 etiss_uint8 rm = 0;
263 static BitArrayRange R_rm_0(14, 12);
264 rm += R_rm_0.read(ba) << 0;
265 etiss_uint8 rs1 = 0;
266 static BitArrayRange R_rs1_0(19, 15);
267 rs1 += R_rs1_0.read(ba) << 0;
268 
269 // -----------------------------------------------------------------------------
270 
271  std::stringstream ss;
272 // -----------------------------------------------------------------------------
273 ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
274 // -----------------------------------------------------------------------------
275  return ss.str();
276  }
277 );
278 
279 // FCVT_S_LU -------------------------------------------------------------------
280 static InstructionDefinition fcvt_s_lu_rd_rm_rs1 (
281  ISA32_RV64IMACFD,
282  "fcvt_s_lu",
283  (uint32_t) 0xd0300053,
284  (uint32_t) 0xfff0007f,
285  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
286  {
287 
288 // -----------------------------------------------------------------------------
289 
290 // -----------------------------------------------------------------------------
291 
292 // -----------------------------------------------------------------------------
293 etiss_uint8 rd = 0;
294 static BitArrayRange R_rd_0(11, 7);
295 rd += R_rd_0.read(ba) << 0;
296 etiss_uint8 rm = 0;
297 static BitArrayRange R_rm_0(14, 12);
298 rm += R_rm_0.read(ba) << 0;
299 etiss_uint8 rs1 = 0;
300 static BitArrayRange R_rs1_0(19, 15);
301 rs1 += R_rs1_0.read(ba) << 0;
302 
303 // -----------------------------------------------------------------------------
304 
305  {
306  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
307 
308  cp.code() = std::string("//FCVT_S_LU\n");
309 
310 // -----------------------------------------------------------------------------
311 cp.code() += "etiss_coverage_count(1, 217);\n";
312 { // block
313 cp.code() += "etiss_coverage_count(1, 1169);\n";
314 cp.code() += "{ // block\n";
315 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
316 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
317 cp.code() += "} // block\n";
318 } // block
319 { // block
320 cp.code() += "etiss_coverage_count(1, 8214);\n";
321 cp.code() += "{ // block\n";
322 cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
323 cp.code() += "etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";
324 { // block
325 cp.code() += "etiss_coverage_count(1, 8213);\n";
326 cp.code() += "{ // block\n";
327 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
328 cp.code() += "etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";
329 cp.code() += "} // block\n";
330 } // block
331 cp.code() += "} // block\n";
332 } // block
333 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
334 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
335 // -----------------------------------------------------------------------------
336  cp.getAffectedRegisters().add("instructionPointer", 32);
337  }
338 
339  return true;
340  },
341  0,
342  [] (BitArray & ba, Instruction & instr)
343  {
344 // -----------------------------------------------------------------------------
345 etiss_uint8 rd = 0;
346 static BitArrayRange R_rd_0(11, 7);
347 rd += R_rd_0.read(ba) << 0;
348 etiss_uint8 rm = 0;
349 static BitArrayRange R_rm_0(14, 12);
350 rm += R_rm_0.read(ba) << 0;
351 etiss_uint8 rs1 = 0;
352 static BitArrayRange R_rs1_0(19, 15);
353 rs1 += R_rs1_0.read(ba) << 0;
354 
355 // -----------------------------------------------------------------------------
356 
357  std::stringstream ss;
358 // -----------------------------------------------------------------------------
359 ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
360 // -----------------------------------------------------------------------------
361  return ss.str();
362  }
363 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_s_l_rd_rm_rs1
static InstructionDefinition fcvt_s_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_L\n");cp.code()+="etiss_coverage_count(1, 216);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8178);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8152, 8151, 8148, 8147, 8145, 8149, 8150);\n";{ cp.code()+="etiss_coverage_count(1, 8177);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8176, 8164, 8163, 8175, 8174, 8172);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_lu_rd_rm_rs1
static InstructionDefinition fcvt_s_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_s_lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_LU\n");cp.code()+="etiss_coverage_count(1, 217);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8188, 8187, 8184, 8183, 8181, 8185, 8186);\n";{ cp.code()+="etiss_coverage_count(1, 8213);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 8212, 8200, 8199, 8211, 8210, 8208);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_l_s_rd_rm_rs1
static InstructionDefinition fcvt_l_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_S\n");cp.code()+="etiss_coverage_count(1, 214);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8103);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8073, 8072, 8069, 8068, 8067, 8070, 8071);\n";cp.code()+="etiss_coverage_count(1, 8074);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8080, 8077, 8075, 8078, 8079);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8087, 8085, 8084, 8082, 8086);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8090, 8089);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8102, 8091, 8101, 8095, 8092, 8096, 8099, 8097, 8100);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_s_rd_rm_rs1
static InstructionDefinition fcvt_lu_s_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_S\n");cp.code()+="etiss_coverage_count(1, 215);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8142);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8112, 8111, 8108, 8107, 8106, 8109, 8110);\n";cp.code()+="etiss_coverage_count(1, 8113);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8119, 8116, 8114, 8117, 8118);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8126, 8124, 8123, 8121, 8125);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8129, 8128);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8141, 8130, 8140, 8134, 8131, 8135, 8138, 8136, 8139);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Oct 24 2024 09:40:11 for ETISS 0.8.0 by doxygen 1.9.1