ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_RV32IInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// LUI -------------------------------------------------------------------------
16static InstructionDefinition lui_rd_imm (
17 ISA32_RV64IMACFD,
18 "lui",
19 (uint32_t) 0x000037,
20 (uint32_t) 0x00007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint32 imm = 0;
34static BitArrayRange R_imm_12(31, 12);
35imm += R_imm_12.read(ba) << 12;
36
37// NOLINTEND(clang-diagnostic-unused-but-set-variable)
38// -----------------------------------------------------------------------------
39
40 {
41 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
42
43 cp.code() = std::string("//LUI\n");
44
45// -----------------------------------------------------------------------------
46cp.code() += "etiss_coverage_count(1, 0);\n";
47{ // block
48cp.code() += "etiss_coverage_count(1, 1169);\n";
49cp.code() += "{ // block\n";
50cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
51cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
52cp.code() += "} // block\n";
53} // block
54cp.code() += "etiss_coverage_count(1, 1170);\n";
55if ((rd % 32ULL) != 0LL) { // conditional
56cp.code() += "etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";
57cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n";
58cp.code() += "etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";
59} // conditional
60cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
61cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
62// -----------------------------------------------------------------------------
63 cp.getAffectedRegisters().add("instructionPointer", 32);
64 }
65
66 return true;
67 },
68 0,
69 [] (BitArray & ba, Instruction & instr)
70 {
71// -----------------------------------------------------------------------------
72etiss_uint8 rd = 0;
73static BitArrayRange R_rd_0(11, 7);
74rd += R_rd_0.read(ba) << 0;
75etiss_uint32 imm = 0;
76static BitArrayRange R_imm_12(31, 12);
77imm += R_imm_12.read(ba) << 12;
78
79// -----------------------------------------------------------------------------
80
81 std::stringstream ss;
82// -----------------------------------------------------------------------------
83ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
84// -----------------------------------------------------------------------------
85 return ss.str();
86 }
87);
88
89// AUIPC -----------------------------------------------------------------------
90static InstructionDefinition auipc_rd_imm (
91 ISA32_RV64IMACFD,
92 "auipc",
93 (uint32_t) 0x000017,
94 (uint32_t) 0x00007f,
95 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
96 {
97
98// -----------------------------------------------------------------------------
99
100// -----------------------------------------------------------------------------
101
102// -----------------------------------------------------------------------------
103// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
104etiss_uint8 rd = 0;
105static BitArrayRange R_rd_0(11, 7);
106rd += R_rd_0.read(ba) << 0;
107etiss_uint32 imm = 0;
108static BitArrayRange R_imm_12(31, 12);
109imm += R_imm_12.read(ba) << 12;
110
111// NOLINTEND(clang-diagnostic-unused-but-set-variable)
112// -----------------------------------------------------------------------------
113
114 {
115 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
116
117 cp.code() = std::string("//AUIPC\n");
118
119// -----------------------------------------------------------------------------
120cp.code() += "etiss_coverage_count(1, 1);\n";
121{ // block
122cp.code() += "etiss_coverage_count(1, 1169);\n";
123cp.code() += "{ // block\n";
124cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
125cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
126cp.code() += "} // block\n";
127} // block
128cp.code() += "etiss_coverage_count(1, 1188);\n";
129if ((rd % 32ULL) != 0LL) { // conditional
130cp.code() += "etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";
131cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
132cp.code() += "etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";
133} // conditional
134cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
135cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
136// -----------------------------------------------------------------------------
137 cp.getAffectedRegisters().add("instructionPointer", 32);
138 }
139
140 return true;
141 },
142 0,
143 [] (BitArray & ba, Instruction & instr)
144 {
145// -----------------------------------------------------------------------------
146etiss_uint8 rd = 0;
147static BitArrayRange R_rd_0(11, 7);
148rd += R_rd_0.read(ba) << 0;
149etiss_uint32 imm = 0;
150static BitArrayRange R_imm_12(31, 12);
151imm += R_imm_12.read(ba) << 12;
152
153// -----------------------------------------------------------------------------
154
155 std::stringstream ss;
156// -----------------------------------------------------------------------------
157ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
158// -----------------------------------------------------------------------------
159 return ss.str();
160 }
161);
162
163// JAL -------------------------------------------------------------------------
164static InstructionDefinition jal_rd_imm (
165 ISA32_RV64IMACFD,
166 "jal",
167 (uint32_t) 0x00006f,
168 (uint32_t) 0x00007f,
169 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
170 {
171
172// -----------------------------------------------------------------------------
173
174// -----------------------------------------------------------------------------
175
176// -----------------------------------------------------------------------------
177// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
178etiss_uint8 rd = 0;
179static BitArrayRange R_rd_0(11, 7);
180rd += R_rd_0.read(ba) << 0;
181etiss_uint32 imm = 0;
182static BitArrayRange R_imm_12(19, 12);
183imm += R_imm_12.read(ba) << 12;
184static BitArrayRange R_imm_11(20, 20);
185imm += R_imm_11.read(ba) << 11;
186static BitArrayRange R_imm_1(30, 21);
187imm += R_imm_1.read(ba) << 1;
188static BitArrayRange R_imm_20(31, 31);
189imm += R_imm_20.read(ba) << 20;
190
191// NOLINTEND(clang-diagnostic-unused-but-set-variable)
192// -----------------------------------------------------------------------------
193
194 {
195 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
196
197 cp.code() = std::string("//JAL\n");
198
199// -----------------------------------------------------------------------------
200cp.code() += "etiss_coverage_count(1, 2);\n";
201{ // block
202cp.code() += "etiss_coverage_count(1, 1169);\n";
203cp.code() += "{ // block\n";
204cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
205cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
206cp.code() += "} // block\n";
207} // block
208{ // block
209cp.code() += "etiss_coverage_count(1, 1236);\n";
210cp.code() += "{ // block\n";
211cp.code() += "etiss_coverage_count(1, 1205);\n";
212if (imm % 2ULL) { // conditional
213cp.code() += "etiss_coverage_count(2, 1208, 1206);\n";
214{ // block
215cp.code() += "etiss_coverage_count(1, 1212);\n";
216cp.code() += "{ // block\n";
217{ // procedure
218cp.code() += "{ // procedure\n";
219cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
220cp.code() += "etiss_coverage_count(2, 1211, 1209);\n";
221cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
222cp.code() += "} // procedure\n";
223} // procedure
224cp.code() += "} // block\n";
225} // block
226} // conditional
227else { // conditional
228{ // block
229cp.code() += "etiss_coverage_count(1, 1235);\n";
230cp.code() += "{ // block\n";
231cp.code() += "etiss_coverage_count(1, 1213);\n";
232if ((rd % 32ULL) != 0LL) { // conditional
233cp.code() += "etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";
234cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
235cp.code() += "etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";
236} // conditional
237cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
238cp.code() += "etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";
239cp.code() += "} // block\n";
240} // block
241} // conditional
242cp.code() += "} // block\n";
243} // block
244cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
245cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
246// -----------------------------------------------------------------------------
247 cp.getAffectedRegisters().add("instructionPointer", 32);
248 }
249 {
250 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
251
252 cp.code() = std::string("//JAL\n");
253
254// -----------------------------------------------------------------------------
255cp.code() += "return cpu->exception;\n";
256// -----------------------------------------------------------------------------
257 }
258
259 return true;
260 },
261 0,
262 [] (BitArray & ba, Instruction & instr)
263 {
264// -----------------------------------------------------------------------------
265etiss_uint8 rd = 0;
266static BitArrayRange R_rd_0(11, 7);
267rd += R_rd_0.read(ba) << 0;
268etiss_uint32 imm = 0;
269static BitArrayRange R_imm_12(19, 12);
270imm += R_imm_12.read(ba) << 12;
271static BitArrayRange R_imm_11(20, 20);
272imm += R_imm_11.read(ba) << 11;
273static BitArrayRange R_imm_1(30, 21);
274imm += R_imm_1.read(ba) << 1;
275static BitArrayRange R_imm_20(31, 31);
276imm += R_imm_20.read(ba) << 20;
277
278// -----------------------------------------------------------------------------
279
280 std::stringstream ss;
281// -----------------------------------------------------------------------------
282ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
283// -----------------------------------------------------------------------------
284 return ss.str();
285 }
286);
287
288// JALR ------------------------------------------------------------------------
289static InstructionDefinition jalr_rd_rs1_imm (
290 ISA32_RV64IMACFD,
291 "jalr",
292 (uint32_t) 0x000067,
293 (uint32_t) 0x00707f,
294 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
295 {
296
297// -----------------------------------------------------------------------------
298
299// -----------------------------------------------------------------------------
300
301// -----------------------------------------------------------------------------
302// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
303etiss_uint8 rd = 0;
304static BitArrayRange R_rd_0(11, 7);
305rd += R_rd_0.read(ba) << 0;
306etiss_uint8 rs1 = 0;
307static BitArrayRange R_rs1_0(19, 15);
308rs1 += R_rs1_0.read(ba) << 0;
309etiss_uint16 imm = 0;
310static BitArrayRange R_imm_0(31, 20);
311imm += R_imm_0.read(ba) << 0;
312
313// NOLINTEND(clang-diagnostic-unused-but-set-variable)
314// -----------------------------------------------------------------------------
315
316 {
317 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
318
319 cp.code() = std::string("//JALR\n");
320
321// -----------------------------------------------------------------------------
322cp.code() += "etiss_coverage_count(1, 3);\n";
323{ // block
324cp.code() += "etiss_coverage_count(1, 1169);\n";
325cp.code() += "{ // block\n";
326cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
327cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
328cp.code() += "} // block\n";
329} // block
330{ // block
331cp.code() += "etiss_coverage_count(1, 1282);\n";
332cp.code() += "{ // block\n";
333cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
334cp.code() += "etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";
335cp.code() += "etiss_coverage_count(1, 1251);\n";
336cp.code() += "if (new_pc % 2ULL) { // conditional\n";
337cp.code() += "etiss_coverage_count(2, 1254, 1252);\n";
338{ // block
339cp.code() += "etiss_coverage_count(1, 1258);\n";
340cp.code() += "{ // block\n";
341{ // procedure
342cp.code() += "{ // procedure\n";
343cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
344cp.code() += "etiss_coverage_count(2, 1257, 1255);\n";
345cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
346cp.code() += "} // procedure\n";
347} // procedure
348cp.code() += "} // block\n";
349} // block
350cp.code() += "} // conditional\n";
351cp.code() += "else { // conditional\n";
352{ // block
353cp.code() += "etiss_coverage_count(1, 1281);\n";
354cp.code() += "{ // block\n";
355cp.code() += "etiss_coverage_count(1, 1259);\n";
356if ((rd % 32ULL) != 0LL) { // conditional
357cp.code() += "etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";
358cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
359cp.code() += "etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";
360} // conditional
361cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
362cp.code() += "etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";
363cp.code() += "} // block\n";
364} // block
365cp.code() += "} // conditional\n";
366cp.code() += "} // block\n";
367} // block
368cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
369cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
370// -----------------------------------------------------------------------------
371 cp.getAffectedRegisters().add("instructionPointer", 32);
372 }
373 {
374 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
375
376 cp.code() = std::string("//JALR\n");
377
378// -----------------------------------------------------------------------------
379cp.code() += "return cpu->exception;\n";
380// -----------------------------------------------------------------------------
381 }
382
383 return true;
384 },
385 0,
386 [] (BitArray & ba, Instruction & instr)
387 {
388// -----------------------------------------------------------------------------
389etiss_uint8 rd = 0;
390static BitArrayRange R_rd_0(11, 7);
391rd += R_rd_0.read(ba) << 0;
392etiss_uint8 rs1 = 0;
393static BitArrayRange R_rs1_0(19, 15);
394rs1 += R_rs1_0.read(ba) << 0;
395etiss_uint16 imm = 0;
396static BitArrayRange R_imm_0(31, 20);
397imm += R_imm_0.read(ba) << 0;
398
399// -----------------------------------------------------------------------------
400
401 std::stringstream ss;
402// -----------------------------------------------------------------------------
403ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
404// -----------------------------------------------------------------------------
405 return ss.str();
406 }
407);
408
409// BEQ -------------------------------------------------------------------------
410static InstructionDefinition beq_imm_rs1_rs2 (
411 ISA32_RV64IMACFD,
412 "beq",
413 (uint32_t) 0x000063,
414 (uint32_t) 0x00707f,
415 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
416 {
417
418// -----------------------------------------------------------------------------
419
420// -----------------------------------------------------------------------------
421
422// -----------------------------------------------------------------------------
423// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
424etiss_uint16 imm = 0;
425static BitArrayRange R_imm_11(7, 7);
426imm += R_imm_11.read(ba) << 11;
427static BitArrayRange R_imm_1(11, 8);
428imm += R_imm_1.read(ba) << 1;
429etiss_uint8 rs1 = 0;
430static BitArrayRange R_rs1_0(19, 15);
431rs1 += R_rs1_0.read(ba) << 0;
432etiss_uint8 rs2 = 0;
433static BitArrayRange R_rs2_0(24, 20);
434rs2 += R_rs2_0.read(ba) << 0;
435static BitArrayRange R_imm_5(30, 25);
436imm += R_imm_5.read(ba) << 5;
437static BitArrayRange R_imm_12(31, 31);
438imm += R_imm_12.read(ba) << 12;
439
440// NOLINTEND(clang-diagnostic-unused-but-set-variable)
441// -----------------------------------------------------------------------------
442
443 {
444 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
445
446 cp.code() = std::string("//BEQ\n");
447
448// -----------------------------------------------------------------------------
449cp.code() += "etiss_coverage_count(1, 4);\n";
450{ // block
451cp.code() += "etiss_coverage_count(1, 1169);\n";
452cp.code() += "{ // block\n";
453cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
454cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
455cp.code() += "} // block\n";
456} // block
457{ // block
458cp.code() += "etiss_coverage_count(1, 1311);\n";
459cp.code() += "{ // block\n";
460cp.code() += "etiss_coverage_count(1, 1283);\n";
461cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
462cp.code() += "etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";
463{ // block
464cp.code() += "etiss_coverage_count(1, 1310);\n";
465cp.code() += "{ // block\n";
466cp.code() += "etiss_coverage_count(1, 1295);\n";
467if (imm % 2ULL) { // conditional
468cp.code() += "etiss_coverage_count(2, 1298, 1296);\n";
469{ // block
470cp.code() += "etiss_coverage_count(1, 1302);\n";
471cp.code() += "{ // block\n";
472{ // procedure
473cp.code() += "{ // procedure\n";
474cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
475cp.code() += "etiss_coverage_count(2, 1301, 1299);\n";
476cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
477cp.code() += "} // procedure\n";
478} // procedure
479cp.code() += "} // block\n";
480} // block
481} // conditional
482else { // conditional
483{ // block
484cp.code() += "etiss_coverage_count(1, 1309);\n";
485cp.code() += "{ // block\n";
486cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
487cp.code() += "etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";
488cp.code() += "} // block\n";
489} // block
490} // conditional
491cp.code() += "} // block\n";
492} // block
493cp.code() += "} // conditional\n";
494cp.code() += "} // block\n";
495} // block
496cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
497cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
498// -----------------------------------------------------------------------------
499 cp.getAffectedRegisters().add("instructionPointer", 32);
500 }
501 {
502 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
503
504 cp.code() = std::string("//BEQ\n");
505
506// -----------------------------------------------------------------------------
507cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
508// -----------------------------------------------------------------------------
509 }
510
511 return true;
512 },
513 0,
514 [] (BitArray & ba, Instruction & instr)
515 {
516// -----------------------------------------------------------------------------
517etiss_uint16 imm = 0;
518static BitArrayRange R_imm_11(7, 7);
519imm += R_imm_11.read(ba) << 11;
520static BitArrayRange R_imm_1(11, 8);
521imm += R_imm_1.read(ba) << 1;
522etiss_uint8 rs1 = 0;
523static BitArrayRange R_rs1_0(19, 15);
524rs1 += R_rs1_0.read(ba) << 0;
525etiss_uint8 rs2 = 0;
526static BitArrayRange R_rs2_0(24, 20);
527rs2 += R_rs2_0.read(ba) << 0;
528static BitArrayRange R_imm_5(30, 25);
529imm += R_imm_5.read(ba) << 5;
530static BitArrayRange R_imm_12(31, 31);
531imm += R_imm_12.read(ba) << 12;
532
533// -----------------------------------------------------------------------------
534
535 std::stringstream ss;
536// -----------------------------------------------------------------------------
537ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
538// -----------------------------------------------------------------------------
539 return ss.str();
540 }
541);
542
543// BNE -------------------------------------------------------------------------
544static InstructionDefinition bne_imm_rs1_rs2 (
545 ISA32_RV64IMACFD,
546 "bne",
547 (uint32_t) 0x001063,
548 (uint32_t) 0x00707f,
549 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
550 {
551
552// -----------------------------------------------------------------------------
553
554// -----------------------------------------------------------------------------
555
556// -----------------------------------------------------------------------------
557// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
558etiss_uint16 imm = 0;
559static BitArrayRange R_imm_11(7, 7);
560imm += R_imm_11.read(ba) << 11;
561static BitArrayRange R_imm_1(11, 8);
562imm += R_imm_1.read(ba) << 1;
563etiss_uint8 rs1 = 0;
564static BitArrayRange R_rs1_0(19, 15);
565rs1 += R_rs1_0.read(ba) << 0;
566etiss_uint8 rs2 = 0;
567static BitArrayRange R_rs2_0(24, 20);
568rs2 += R_rs2_0.read(ba) << 0;
569static BitArrayRange R_imm_5(30, 25);
570imm += R_imm_5.read(ba) << 5;
571static BitArrayRange R_imm_12(31, 31);
572imm += R_imm_12.read(ba) << 12;
573
574// NOLINTEND(clang-diagnostic-unused-but-set-variable)
575// -----------------------------------------------------------------------------
576
577 {
578 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
579
580 cp.code() = std::string("//BNE\n");
581
582// -----------------------------------------------------------------------------
583cp.code() += "etiss_coverage_count(1, 5);\n";
584{ // block
585cp.code() += "etiss_coverage_count(1, 1169);\n";
586cp.code() += "{ // block\n";
587cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
588cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
589cp.code() += "} // block\n";
590} // block
591{ // block
592cp.code() += "etiss_coverage_count(1, 1340);\n";
593cp.code() += "{ // block\n";
594cp.code() += "etiss_coverage_count(1, 1312);\n";
595cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
596cp.code() += "etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";
597{ // block
598cp.code() += "etiss_coverage_count(1, 1339);\n";
599cp.code() += "{ // block\n";
600cp.code() += "etiss_coverage_count(1, 1324);\n";
601if (imm % 2ULL) { // conditional
602cp.code() += "etiss_coverage_count(2, 1327, 1325);\n";
603{ // block
604cp.code() += "etiss_coverage_count(1, 1331);\n";
605cp.code() += "{ // block\n";
606{ // procedure
607cp.code() += "{ // procedure\n";
608cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
609cp.code() += "etiss_coverage_count(2, 1330, 1328);\n";
610cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
611cp.code() += "} // procedure\n";
612} // procedure
613cp.code() += "} // block\n";
614} // block
615} // conditional
616else { // conditional
617{ // block
618cp.code() += "etiss_coverage_count(1, 1338);\n";
619cp.code() += "{ // block\n";
620cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
621cp.code() += "etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";
622cp.code() += "} // block\n";
623} // block
624} // conditional
625cp.code() += "} // block\n";
626} // block
627cp.code() += "} // conditional\n";
628cp.code() += "} // block\n";
629} // block
630cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
631cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
632// -----------------------------------------------------------------------------
633 cp.getAffectedRegisters().add("instructionPointer", 32);
634 }
635 {
636 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
637
638 cp.code() = std::string("//BNE\n");
639
640// -----------------------------------------------------------------------------
641cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
642// -----------------------------------------------------------------------------
643 }
644
645 return true;
646 },
647 0,
648 [] (BitArray & ba, Instruction & instr)
649 {
650// -----------------------------------------------------------------------------
651etiss_uint16 imm = 0;
652static BitArrayRange R_imm_11(7, 7);
653imm += R_imm_11.read(ba) << 11;
654static BitArrayRange R_imm_1(11, 8);
655imm += R_imm_1.read(ba) << 1;
656etiss_uint8 rs1 = 0;
657static BitArrayRange R_rs1_0(19, 15);
658rs1 += R_rs1_0.read(ba) << 0;
659etiss_uint8 rs2 = 0;
660static BitArrayRange R_rs2_0(24, 20);
661rs2 += R_rs2_0.read(ba) << 0;
662static BitArrayRange R_imm_5(30, 25);
663imm += R_imm_5.read(ba) << 5;
664static BitArrayRange R_imm_12(31, 31);
665imm += R_imm_12.read(ba) << 12;
666
667// -----------------------------------------------------------------------------
668
669 std::stringstream ss;
670// -----------------------------------------------------------------------------
671ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
672// -----------------------------------------------------------------------------
673 return ss.str();
674 }
675);
676
677// BLT -------------------------------------------------------------------------
678static InstructionDefinition blt_imm_rs1_rs2 (
679 ISA32_RV64IMACFD,
680 "blt",
681 (uint32_t) 0x004063,
682 (uint32_t) 0x00707f,
683 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
684 {
685
686// -----------------------------------------------------------------------------
687
688// -----------------------------------------------------------------------------
689
690// -----------------------------------------------------------------------------
691// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
692etiss_uint16 imm = 0;
693static BitArrayRange R_imm_11(7, 7);
694imm += R_imm_11.read(ba) << 11;
695static BitArrayRange R_imm_1(11, 8);
696imm += R_imm_1.read(ba) << 1;
697etiss_uint8 rs1 = 0;
698static BitArrayRange R_rs1_0(19, 15);
699rs1 += R_rs1_0.read(ba) << 0;
700etiss_uint8 rs2 = 0;
701static BitArrayRange R_rs2_0(24, 20);
702rs2 += R_rs2_0.read(ba) << 0;
703static BitArrayRange R_imm_5(30, 25);
704imm += R_imm_5.read(ba) << 5;
705static BitArrayRange R_imm_12(31, 31);
706imm += R_imm_12.read(ba) << 12;
707
708// NOLINTEND(clang-diagnostic-unused-but-set-variable)
709// -----------------------------------------------------------------------------
710
711 {
712 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
713
714 cp.code() = std::string("//BLT\n");
715
716// -----------------------------------------------------------------------------
717cp.code() += "etiss_coverage_count(1, 6);\n";
718{ // block
719cp.code() += "etiss_coverage_count(1, 1169);\n";
720cp.code() += "{ // block\n";
721cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
722cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
723cp.code() += "} // block\n";
724} // block
725{ // block
726cp.code() += "etiss_coverage_count(1, 1373);\n";
727cp.code() += "{ // block\n";
728cp.code() += "etiss_coverage_count(1, 1341);\n";
729cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
730cp.code() += "etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";
731{ // block
732cp.code() += "etiss_coverage_count(1, 1372);\n";
733cp.code() += "{ // block\n";
734cp.code() += "etiss_coverage_count(1, 1357);\n";
735if (imm % 2ULL) { // conditional
736cp.code() += "etiss_coverage_count(2, 1360, 1358);\n";
737{ // block
738cp.code() += "etiss_coverage_count(1, 1364);\n";
739cp.code() += "{ // block\n";
740{ // procedure
741cp.code() += "{ // procedure\n";
742cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
743cp.code() += "etiss_coverage_count(2, 1363, 1361);\n";
744cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
745cp.code() += "} // procedure\n";
746} // procedure
747cp.code() += "} // block\n";
748} // block
749} // conditional
750else { // conditional
751{ // block
752cp.code() += "etiss_coverage_count(1, 1371);\n";
753cp.code() += "{ // block\n";
754cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
755cp.code() += "etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";
756cp.code() += "} // block\n";
757} // block
758} // conditional
759cp.code() += "} // block\n";
760} // block
761cp.code() += "} // conditional\n";
762cp.code() += "} // block\n";
763} // block
764cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
765cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
766// -----------------------------------------------------------------------------
767 cp.getAffectedRegisters().add("instructionPointer", 32);
768 }
769 {
770 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
771
772 cp.code() = std::string("//BLT\n");
773
774// -----------------------------------------------------------------------------
775cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
776// -----------------------------------------------------------------------------
777 }
778
779 return true;
780 },
781 0,
782 [] (BitArray & ba, Instruction & instr)
783 {
784// -----------------------------------------------------------------------------
785etiss_uint16 imm = 0;
786static BitArrayRange R_imm_11(7, 7);
787imm += R_imm_11.read(ba) << 11;
788static BitArrayRange R_imm_1(11, 8);
789imm += R_imm_1.read(ba) << 1;
790etiss_uint8 rs1 = 0;
791static BitArrayRange R_rs1_0(19, 15);
792rs1 += R_rs1_0.read(ba) << 0;
793etiss_uint8 rs2 = 0;
794static BitArrayRange R_rs2_0(24, 20);
795rs2 += R_rs2_0.read(ba) << 0;
796static BitArrayRange R_imm_5(30, 25);
797imm += R_imm_5.read(ba) << 5;
798static BitArrayRange R_imm_12(31, 31);
799imm += R_imm_12.read(ba) << 12;
800
801// -----------------------------------------------------------------------------
802
803 std::stringstream ss;
804// -----------------------------------------------------------------------------
805ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
806// -----------------------------------------------------------------------------
807 return ss.str();
808 }
809);
810
811// BGE -------------------------------------------------------------------------
812static InstructionDefinition bge_imm_rs1_rs2 (
813 ISA32_RV64IMACFD,
814 "bge",
815 (uint32_t) 0x005063,
816 (uint32_t) 0x00707f,
817 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
818 {
819
820// -----------------------------------------------------------------------------
821
822// -----------------------------------------------------------------------------
823
824// -----------------------------------------------------------------------------
825// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
826etiss_uint16 imm = 0;
827static BitArrayRange R_imm_11(7, 7);
828imm += R_imm_11.read(ba) << 11;
829static BitArrayRange R_imm_1(11, 8);
830imm += R_imm_1.read(ba) << 1;
831etiss_uint8 rs1 = 0;
832static BitArrayRange R_rs1_0(19, 15);
833rs1 += R_rs1_0.read(ba) << 0;
834etiss_uint8 rs2 = 0;
835static BitArrayRange R_rs2_0(24, 20);
836rs2 += R_rs2_0.read(ba) << 0;
837static BitArrayRange R_imm_5(30, 25);
838imm += R_imm_5.read(ba) << 5;
839static BitArrayRange R_imm_12(31, 31);
840imm += R_imm_12.read(ba) << 12;
841
842// NOLINTEND(clang-diagnostic-unused-but-set-variable)
843// -----------------------------------------------------------------------------
844
845 {
846 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
847
848 cp.code() = std::string("//BGE\n");
849
850// -----------------------------------------------------------------------------
851cp.code() += "etiss_coverage_count(1, 7);\n";
852{ // block
853cp.code() += "etiss_coverage_count(1, 1169);\n";
854cp.code() += "{ // block\n";
855cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
856cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
857cp.code() += "} // block\n";
858} // block
859{ // block
860cp.code() += "etiss_coverage_count(1, 1406);\n";
861cp.code() += "{ // block\n";
862cp.code() += "etiss_coverage_count(1, 1374);\n";
863cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
864cp.code() += "etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";
865{ // block
866cp.code() += "etiss_coverage_count(1, 1405);\n";
867cp.code() += "{ // block\n";
868cp.code() += "etiss_coverage_count(1, 1390);\n";
869if (imm % 2ULL) { // conditional
870cp.code() += "etiss_coverage_count(2, 1393, 1391);\n";
871{ // block
872cp.code() += "etiss_coverage_count(1, 1397);\n";
873cp.code() += "{ // block\n";
874{ // procedure
875cp.code() += "{ // procedure\n";
876cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
877cp.code() += "etiss_coverage_count(2, 1396, 1394);\n";
878cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
879cp.code() += "} // procedure\n";
880} // procedure
881cp.code() += "} // block\n";
882} // block
883} // conditional
884else { // conditional
885{ // block
886cp.code() += "etiss_coverage_count(1, 1404);\n";
887cp.code() += "{ // block\n";
888cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
889cp.code() += "etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";
890cp.code() += "} // block\n";
891} // block
892} // conditional
893cp.code() += "} // block\n";
894} // block
895cp.code() += "} // conditional\n";
896cp.code() += "} // block\n";
897} // block
898cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
899cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
900// -----------------------------------------------------------------------------
901 cp.getAffectedRegisters().add("instructionPointer", 32);
902 }
903 {
904 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
905
906 cp.code() = std::string("//BGE\n");
907
908// -----------------------------------------------------------------------------
909cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
910// -----------------------------------------------------------------------------
911 }
912
913 return true;
914 },
915 0,
916 [] (BitArray & ba, Instruction & instr)
917 {
918// -----------------------------------------------------------------------------
919etiss_uint16 imm = 0;
920static BitArrayRange R_imm_11(7, 7);
921imm += R_imm_11.read(ba) << 11;
922static BitArrayRange R_imm_1(11, 8);
923imm += R_imm_1.read(ba) << 1;
924etiss_uint8 rs1 = 0;
925static BitArrayRange R_rs1_0(19, 15);
926rs1 += R_rs1_0.read(ba) << 0;
927etiss_uint8 rs2 = 0;
928static BitArrayRange R_rs2_0(24, 20);
929rs2 += R_rs2_0.read(ba) << 0;
930static BitArrayRange R_imm_5(30, 25);
931imm += R_imm_5.read(ba) << 5;
932static BitArrayRange R_imm_12(31, 31);
933imm += R_imm_12.read(ba) << 12;
934
935// -----------------------------------------------------------------------------
936
937 std::stringstream ss;
938// -----------------------------------------------------------------------------
939ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
940// -----------------------------------------------------------------------------
941 return ss.str();
942 }
943);
944
945// BLTU ------------------------------------------------------------------------
946static InstructionDefinition bltu_imm_rs1_rs2 (
947 ISA32_RV64IMACFD,
948 "bltu",
949 (uint32_t) 0x006063,
950 (uint32_t) 0x00707f,
951 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
952 {
953
954// -----------------------------------------------------------------------------
955
956// -----------------------------------------------------------------------------
957
958// -----------------------------------------------------------------------------
959// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
960etiss_uint16 imm = 0;
961static BitArrayRange R_imm_11(7, 7);
962imm += R_imm_11.read(ba) << 11;
963static BitArrayRange R_imm_1(11, 8);
964imm += R_imm_1.read(ba) << 1;
965etiss_uint8 rs1 = 0;
966static BitArrayRange R_rs1_0(19, 15);
967rs1 += R_rs1_0.read(ba) << 0;
968etiss_uint8 rs2 = 0;
969static BitArrayRange R_rs2_0(24, 20);
970rs2 += R_rs2_0.read(ba) << 0;
971static BitArrayRange R_imm_5(30, 25);
972imm += R_imm_5.read(ba) << 5;
973static BitArrayRange R_imm_12(31, 31);
974imm += R_imm_12.read(ba) << 12;
975
976// NOLINTEND(clang-diagnostic-unused-but-set-variable)
977// -----------------------------------------------------------------------------
978
979 {
980 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
981
982 cp.code() = std::string("//BLTU\n");
983
984// -----------------------------------------------------------------------------
985cp.code() += "etiss_coverage_count(1, 8);\n";
986{ // block
987cp.code() += "etiss_coverage_count(1, 1169);\n";
988cp.code() += "{ // block\n";
989cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
990cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
991cp.code() += "} // block\n";
992} // block
993{ // block
994cp.code() += "etiss_coverage_count(1, 1435);\n";
995cp.code() += "{ // block\n";
996cp.code() += "etiss_coverage_count(1, 1407);\n";
997cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
998cp.code() += "etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";
999{ // block
1000cp.code() += "etiss_coverage_count(1, 1434);\n";
1001cp.code() += "{ // block\n";
1002cp.code() += "etiss_coverage_count(1, 1419);\n";
1003if (imm % 2ULL) { // conditional
1004cp.code() += "etiss_coverage_count(2, 1422, 1420);\n";
1005{ // block
1006cp.code() += "etiss_coverage_count(1, 1426);\n";
1007cp.code() += "{ // block\n";
1008{ // procedure
1009cp.code() += "{ // procedure\n";
1010cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
1011cp.code() += "etiss_coverage_count(2, 1425, 1423);\n";
1012cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1013cp.code() += "} // procedure\n";
1014} // procedure
1015cp.code() += "} // block\n";
1016} // block
1017} // conditional
1018else { // conditional
1019{ // block
1020cp.code() += "etiss_coverage_count(1, 1433);\n";
1021cp.code() += "{ // block\n";
1022cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1023cp.code() += "etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";
1024cp.code() += "} // block\n";
1025} // block
1026} // conditional
1027cp.code() += "} // block\n";
1028} // block
1029cp.code() += "} // conditional\n";
1030cp.code() += "} // block\n";
1031} // block
1032cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1033cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1034// -----------------------------------------------------------------------------
1035 cp.getAffectedRegisters().add("instructionPointer", 32);
1036 }
1037 {
1038 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1039
1040 cp.code() = std::string("//BLTU\n");
1041
1042// -----------------------------------------------------------------------------
1043cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1044// -----------------------------------------------------------------------------
1045 }
1046
1047 return true;
1048 },
1049 0,
1050 [] (BitArray & ba, Instruction & instr)
1051 {
1052// -----------------------------------------------------------------------------
1053etiss_uint16 imm = 0;
1054static BitArrayRange R_imm_11(7, 7);
1055imm += R_imm_11.read(ba) << 11;
1056static BitArrayRange R_imm_1(11, 8);
1057imm += R_imm_1.read(ba) << 1;
1058etiss_uint8 rs1 = 0;
1059static BitArrayRange R_rs1_0(19, 15);
1060rs1 += R_rs1_0.read(ba) << 0;
1061etiss_uint8 rs2 = 0;
1062static BitArrayRange R_rs2_0(24, 20);
1063rs2 += R_rs2_0.read(ba) << 0;
1064static BitArrayRange R_imm_5(30, 25);
1065imm += R_imm_5.read(ba) << 5;
1066static BitArrayRange R_imm_12(31, 31);
1067imm += R_imm_12.read(ba) << 12;
1068
1069// -----------------------------------------------------------------------------
1070
1071 std::stringstream ss;
1072// -----------------------------------------------------------------------------
1073ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1074// -----------------------------------------------------------------------------
1075 return ss.str();
1076 }
1077);
1078
1079// BGEU ------------------------------------------------------------------------
1080static InstructionDefinition bgeu_imm_rs1_rs2 (
1081 ISA32_RV64IMACFD,
1082 "bgeu",
1083 (uint32_t) 0x007063,
1084 (uint32_t) 0x00707f,
1085 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1086 {
1087
1088// -----------------------------------------------------------------------------
1089
1090// -----------------------------------------------------------------------------
1091
1092// -----------------------------------------------------------------------------
1093// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1094etiss_uint16 imm = 0;
1095static BitArrayRange R_imm_11(7, 7);
1096imm += R_imm_11.read(ba) << 11;
1097static BitArrayRange R_imm_1(11, 8);
1098imm += R_imm_1.read(ba) << 1;
1099etiss_uint8 rs1 = 0;
1100static BitArrayRange R_rs1_0(19, 15);
1101rs1 += R_rs1_0.read(ba) << 0;
1102etiss_uint8 rs2 = 0;
1103static BitArrayRange R_rs2_0(24, 20);
1104rs2 += R_rs2_0.read(ba) << 0;
1105static BitArrayRange R_imm_5(30, 25);
1106imm += R_imm_5.read(ba) << 5;
1107static BitArrayRange R_imm_12(31, 31);
1108imm += R_imm_12.read(ba) << 12;
1109
1110// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1111// -----------------------------------------------------------------------------
1112
1113 {
1114 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1115
1116 cp.code() = std::string("//BGEU\n");
1117
1118// -----------------------------------------------------------------------------
1119cp.code() += "etiss_coverage_count(1, 9);\n";
1120{ // block
1121cp.code() += "etiss_coverage_count(1, 1169);\n";
1122cp.code() += "{ // block\n";
1123cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1124cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1125cp.code() += "} // block\n";
1126} // block
1127{ // block
1128cp.code() += "etiss_coverage_count(1, 1464);\n";
1129cp.code() += "{ // block\n";
1130cp.code() += "etiss_coverage_count(1, 1436);\n";
1131cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
1132cp.code() += "etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";
1133{ // block
1134cp.code() += "etiss_coverage_count(1, 1463);\n";
1135cp.code() += "{ // block\n";
1136cp.code() += "etiss_coverage_count(1, 1448);\n";
1137if (imm % 2ULL) { // conditional
1138cp.code() += "etiss_coverage_count(2, 1451, 1449);\n";
1139{ // block
1140cp.code() += "etiss_coverage_count(1, 1455);\n";
1141cp.code() += "{ // block\n";
1142{ // procedure
1143cp.code() += "{ // procedure\n";
1144cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
1145cp.code() += "etiss_coverage_count(2, 1454, 1452);\n";
1146cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1147cp.code() += "} // procedure\n";
1148} // procedure
1149cp.code() += "} // block\n";
1150} // block
1151} // conditional
1152else { // conditional
1153{ // block
1154cp.code() += "etiss_coverage_count(1, 1462);\n";
1155cp.code() += "{ // block\n";
1156cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1157cp.code() += "etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";
1158cp.code() += "} // block\n";
1159} // block
1160} // conditional
1161cp.code() += "} // block\n";
1162} // block
1163cp.code() += "} // conditional\n";
1164cp.code() += "} // block\n";
1165} // block
1166cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1167cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1168// -----------------------------------------------------------------------------
1169 cp.getAffectedRegisters().add("instructionPointer", 32);
1170 }
1171 {
1172 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1173
1174 cp.code() = std::string("//BGEU\n");
1175
1176// -----------------------------------------------------------------------------
1177cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1178// -----------------------------------------------------------------------------
1179 }
1180
1181 return true;
1182 },
1183 0,
1184 [] (BitArray & ba, Instruction & instr)
1185 {
1186// -----------------------------------------------------------------------------
1187etiss_uint16 imm = 0;
1188static BitArrayRange R_imm_11(7, 7);
1189imm += R_imm_11.read(ba) << 11;
1190static BitArrayRange R_imm_1(11, 8);
1191imm += R_imm_1.read(ba) << 1;
1192etiss_uint8 rs1 = 0;
1193static BitArrayRange R_rs1_0(19, 15);
1194rs1 += R_rs1_0.read(ba) << 0;
1195etiss_uint8 rs2 = 0;
1196static BitArrayRange R_rs2_0(24, 20);
1197rs2 += R_rs2_0.read(ba) << 0;
1198static BitArrayRange R_imm_5(30, 25);
1199imm += R_imm_5.read(ba) << 5;
1200static BitArrayRange R_imm_12(31, 31);
1201imm += R_imm_12.read(ba) << 12;
1202
1203// -----------------------------------------------------------------------------
1204
1205 std::stringstream ss;
1206// -----------------------------------------------------------------------------
1207ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1208// -----------------------------------------------------------------------------
1209 return ss.str();
1210 }
1211);
1212
1213// LB --------------------------------------------------------------------------
1214static InstructionDefinition lb_rd_rs1_imm (
1215 ISA32_RV64IMACFD,
1216 "lb",
1217 (uint32_t) 0x000003,
1218 (uint32_t) 0x00707f,
1219 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1220 {
1221
1222// -----------------------------------------------------------------------------
1223
1224// -----------------------------------------------------------------------------
1225
1226// -----------------------------------------------------------------------------
1227// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1228etiss_uint8 rd = 0;
1229static BitArrayRange R_rd_0(11, 7);
1230rd += R_rd_0.read(ba) << 0;
1231etiss_uint8 rs1 = 0;
1232static BitArrayRange R_rs1_0(19, 15);
1233rs1 += R_rs1_0.read(ba) << 0;
1234etiss_uint16 imm = 0;
1235static BitArrayRange R_imm_0(31, 20);
1236imm += R_imm_0.read(ba) << 0;
1237
1238// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1239// -----------------------------------------------------------------------------
1240
1241 {
1242 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1243
1244 cp.code() = std::string("//LB\n");
1245
1246// -----------------------------------------------------------------------------
1247cp.code() += "etiss_coverage_count(1, 10);\n";
1248{ // block
1249cp.code() += "etiss_coverage_count(1, 1169);\n";
1250cp.code() += "{ // block\n";
1251cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1252cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1253cp.code() += "} // block\n";
1254} // block
1255{ // block
1256cp.code() += "etiss_coverage_count(1, 1498);\n";
1257cp.code() += "{ // block\n";
1258cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1259cp.code() += "etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";
1260cp.code() += "etiss_uint8 mem_val_0;\n";
1261cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1262cp.code() += "if (cpu->exception) { // conditional\n";
1263{ // procedure
1264cp.code() += "{ // procedure\n";
1265cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1266cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1267cp.code() += "} // procedure\n";
1268} // procedure
1269cp.code() += "} // conditional\n";
1270cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
1271cp.code() += "etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";
1272cp.code() += "etiss_coverage_count(1, 1482);\n";
1273if ((rd % 32ULL) != 0LL) { // conditional
1274cp.code() += "etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";
1275cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1276cp.code() += "etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";
1277} // conditional
1278cp.code() += "} // block\n";
1279} // block
1280cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1281cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1282// -----------------------------------------------------------------------------
1283 cp.getAffectedRegisters().add("instructionPointer", 32);
1284 }
1285 {
1286 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1287
1288 cp.code() = std::string("//LB\n");
1289
1290// -----------------------------------------------------------------------------
1291cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1292// -----------------------------------------------------------------------------
1293 }
1294
1295 return true;
1296 },
1297 0,
1298 [] (BitArray & ba, Instruction & instr)
1299 {
1300// -----------------------------------------------------------------------------
1301etiss_uint8 rd = 0;
1302static BitArrayRange R_rd_0(11, 7);
1303rd += R_rd_0.read(ba) << 0;
1304etiss_uint8 rs1 = 0;
1305static BitArrayRange R_rs1_0(19, 15);
1306rs1 += R_rs1_0.read(ba) << 0;
1307etiss_uint16 imm = 0;
1308static BitArrayRange R_imm_0(31, 20);
1309imm += R_imm_0.read(ba) << 0;
1310
1311// -----------------------------------------------------------------------------
1312
1313 std::stringstream ss;
1314// -----------------------------------------------------------------------------
1315ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1316// -----------------------------------------------------------------------------
1317 return ss.str();
1318 }
1319);
1320
1321// LH --------------------------------------------------------------------------
1322static InstructionDefinition lh_rd_rs1_imm (
1323 ISA32_RV64IMACFD,
1324 "lh",
1325 (uint32_t) 0x001003,
1326 (uint32_t) 0x00707f,
1327 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1328 {
1329
1330// -----------------------------------------------------------------------------
1331
1332// -----------------------------------------------------------------------------
1333
1334// -----------------------------------------------------------------------------
1335// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1336etiss_uint8 rd = 0;
1337static BitArrayRange R_rd_0(11, 7);
1338rd += R_rd_0.read(ba) << 0;
1339etiss_uint8 rs1 = 0;
1340static BitArrayRange R_rs1_0(19, 15);
1341rs1 += R_rs1_0.read(ba) << 0;
1342etiss_uint16 imm = 0;
1343static BitArrayRange R_imm_0(31, 20);
1344imm += R_imm_0.read(ba) << 0;
1345
1346// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1347// -----------------------------------------------------------------------------
1348
1349 {
1350 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1351
1352 cp.code() = std::string("//LH\n");
1353
1354// -----------------------------------------------------------------------------
1355cp.code() += "etiss_coverage_count(1, 11);\n";
1356{ // block
1357cp.code() += "etiss_coverage_count(1, 1169);\n";
1358cp.code() += "{ // block\n";
1359cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1360cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1361cp.code() += "} // block\n";
1362} // block
1363{ // block
1364cp.code() += "etiss_coverage_count(1, 1532);\n";
1365cp.code() += "{ // block\n";
1366cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1367cp.code() += "etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";
1368cp.code() += "etiss_uint16 mem_val_0;\n";
1369cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1370cp.code() += "if (cpu->exception) { // conditional\n";
1371{ // procedure
1372cp.code() += "{ // procedure\n";
1373cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1374cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1375cp.code() += "} // procedure\n";
1376} // procedure
1377cp.code() += "} // conditional\n";
1378cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
1379cp.code() += "etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";
1380cp.code() += "etiss_coverage_count(1, 1516);\n";
1381if ((rd % 32ULL) != 0LL) { // conditional
1382cp.code() += "etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";
1383cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1384cp.code() += "etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";
1385} // conditional
1386cp.code() += "} // block\n";
1387} // block
1388cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1389cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1390// -----------------------------------------------------------------------------
1391 cp.getAffectedRegisters().add("instructionPointer", 32);
1392 }
1393 {
1394 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1395
1396 cp.code() = std::string("//LH\n");
1397
1398// -----------------------------------------------------------------------------
1399cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1400// -----------------------------------------------------------------------------
1401 }
1402
1403 return true;
1404 },
1405 0,
1406 [] (BitArray & ba, Instruction & instr)
1407 {
1408// -----------------------------------------------------------------------------
1409etiss_uint8 rd = 0;
1410static BitArrayRange R_rd_0(11, 7);
1411rd += R_rd_0.read(ba) << 0;
1412etiss_uint8 rs1 = 0;
1413static BitArrayRange R_rs1_0(19, 15);
1414rs1 += R_rs1_0.read(ba) << 0;
1415etiss_uint16 imm = 0;
1416static BitArrayRange R_imm_0(31, 20);
1417imm += R_imm_0.read(ba) << 0;
1418
1419// -----------------------------------------------------------------------------
1420
1421 std::stringstream ss;
1422// -----------------------------------------------------------------------------
1423ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1424// -----------------------------------------------------------------------------
1425 return ss.str();
1426 }
1427);
1428
1429// LW --------------------------------------------------------------------------
1430static InstructionDefinition lw_rd_rs1_imm (
1431 ISA32_RV64IMACFD,
1432 "lw",
1433 (uint32_t) 0x002003,
1434 (uint32_t) 0x00707f,
1435 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1436 {
1437
1438// -----------------------------------------------------------------------------
1439
1440// -----------------------------------------------------------------------------
1441
1442// -----------------------------------------------------------------------------
1443// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1444etiss_uint8 rd = 0;
1445static BitArrayRange R_rd_0(11, 7);
1446rd += R_rd_0.read(ba) << 0;
1447etiss_uint8 rs1 = 0;
1448static BitArrayRange R_rs1_0(19, 15);
1449rs1 += R_rs1_0.read(ba) << 0;
1450etiss_uint16 imm = 0;
1451static BitArrayRange R_imm_0(31, 20);
1452imm += R_imm_0.read(ba) << 0;
1453
1454// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1455// -----------------------------------------------------------------------------
1456
1457 {
1458 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1459
1460 cp.code() = std::string("//LW\n");
1461
1462// -----------------------------------------------------------------------------
1463cp.code() += "etiss_coverage_count(1, 12);\n";
1464{ // block
1465cp.code() += "etiss_coverage_count(1, 1169);\n";
1466cp.code() += "{ // block\n";
1467cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1468cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1469cp.code() += "} // block\n";
1470} // block
1471{ // block
1472cp.code() += "etiss_coverage_count(1, 1566);\n";
1473cp.code() += "{ // block\n";
1474cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1475cp.code() += "etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";
1476cp.code() += "etiss_uint32 mem_val_0;\n";
1477cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
1478cp.code() += "if (cpu->exception) { // conditional\n";
1479{ // procedure
1480cp.code() += "{ // procedure\n";
1481cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1482cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1483cp.code() += "} // procedure\n";
1484} // procedure
1485cp.code() += "} // conditional\n";
1486cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
1487cp.code() += "etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";
1488cp.code() += "etiss_coverage_count(1, 1550);\n";
1489if ((rd % 32ULL) != 0LL) { // conditional
1490cp.code() += "etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";
1491cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1492cp.code() += "etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";
1493} // conditional
1494cp.code() += "} // block\n";
1495} // block
1496cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1497cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1498// -----------------------------------------------------------------------------
1499 cp.getAffectedRegisters().add("instructionPointer", 32);
1500 }
1501 {
1502 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1503
1504 cp.code() = std::string("//LW\n");
1505
1506// -----------------------------------------------------------------------------
1507cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1508// -----------------------------------------------------------------------------
1509 }
1510
1511 return true;
1512 },
1513 0,
1514 [] (BitArray & ba, Instruction & instr)
1515 {
1516// -----------------------------------------------------------------------------
1517etiss_uint8 rd = 0;
1518static BitArrayRange R_rd_0(11, 7);
1519rd += R_rd_0.read(ba) << 0;
1520etiss_uint8 rs1 = 0;
1521static BitArrayRange R_rs1_0(19, 15);
1522rs1 += R_rs1_0.read(ba) << 0;
1523etiss_uint16 imm = 0;
1524static BitArrayRange R_imm_0(31, 20);
1525imm += R_imm_0.read(ba) << 0;
1526
1527// -----------------------------------------------------------------------------
1528
1529 std::stringstream ss;
1530// -----------------------------------------------------------------------------
1531ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1532// -----------------------------------------------------------------------------
1533 return ss.str();
1534 }
1535);
1536
1537// LBU -------------------------------------------------------------------------
1538static InstructionDefinition lbu_rd_rs1_imm (
1539 ISA32_RV64IMACFD,
1540 "lbu",
1541 (uint32_t) 0x004003,
1542 (uint32_t) 0x00707f,
1543 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1544 {
1545
1546// -----------------------------------------------------------------------------
1547
1548// -----------------------------------------------------------------------------
1549
1550// -----------------------------------------------------------------------------
1551// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1552etiss_uint8 rd = 0;
1553static BitArrayRange R_rd_0(11, 7);
1554rd += R_rd_0.read(ba) << 0;
1555etiss_uint8 rs1 = 0;
1556static BitArrayRange R_rs1_0(19, 15);
1557rs1 += R_rs1_0.read(ba) << 0;
1558etiss_uint16 imm = 0;
1559static BitArrayRange R_imm_0(31, 20);
1560imm += R_imm_0.read(ba) << 0;
1561
1562// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1563// -----------------------------------------------------------------------------
1564
1565 {
1566 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1567
1568 cp.code() = std::string("//LBU\n");
1569
1570// -----------------------------------------------------------------------------
1571cp.code() += "etiss_coverage_count(1, 13);\n";
1572{ // block
1573cp.code() += "etiss_coverage_count(1, 1169);\n";
1574cp.code() += "{ // block\n";
1575cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1576cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1577cp.code() += "} // block\n";
1578} // block
1579{ // block
1580cp.code() += "etiss_coverage_count(1, 1600);\n";
1581cp.code() += "{ // block\n";
1582cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1583cp.code() += "etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";
1584cp.code() += "etiss_uint8 mem_val_0;\n";
1585cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1586cp.code() += "if (cpu->exception) { // conditional\n";
1587{ // procedure
1588cp.code() += "{ // procedure\n";
1589cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1590cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1591cp.code() += "} // procedure\n";
1592} // procedure
1593cp.code() += "} // conditional\n";
1594cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
1595cp.code() += "etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";
1596cp.code() += "etiss_coverage_count(1, 1584);\n";
1597if ((rd % 32ULL) != 0LL) { // conditional
1598cp.code() += "etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";
1599cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1600cp.code() += "etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";
1601} // conditional
1602cp.code() += "} // block\n";
1603} // block
1604cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1605cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1606// -----------------------------------------------------------------------------
1607 cp.getAffectedRegisters().add("instructionPointer", 32);
1608 }
1609 {
1610 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1611
1612 cp.code() = std::string("//LBU\n");
1613
1614// -----------------------------------------------------------------------------
1615cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1616// -----------------------------------------------------------------------------
1617 }
1618
1619 return true;
1620 },
1621 0,
1622 [] (BitArray & ba, Instruction & instr)
1623 {
1624// -----------------------------------------------------------------------------
1625etiss_uint8 rd = 0;
1626static BitArrayRange R_rd_0(11, 7);
1627rd += R_rd_0.read(ba) << 0;
1628etiss_uint8 rs1 = 0;
1629static BitArrayRange R_rs1_0(19, 15);
1630rs1 += R_rs1_0.read(ba) << 0;
1631etiss_uint16 imm = 0;
1632static BitArrayRange R_imm_0(31, 20);
1633imm += R_imm_0.read(ba) << 0;
1634
1635// -----------------------------------------------------------------------------
1636
1637 std::stringstream ss;
1638// -----------------------------------------------------------------------------
1639ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1640// -----------------------------------------------------------------------------
1641 return ss.str();
1642 }
1643);
1644
1645// LHU -------------------------------------------------------------------------
1646static InstructionDefinition lhu_rd_rs1_imm (
1647 ISA32_RV64IMACFD,
1648 "lhu",
1649 (uint32_t) 0x005003,
1650 (uint32_t) 0x00707f,
1651 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1652 {
1653
1654// -----------------------------------------------------------------------------
1655
1656// -----------------------------------------------------------------------------
1657
1658// -----------------------------------------------------------------------------
1659// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1660etiss_uint8 rd = 0;
1661static BitArrayRange R_rd_0(11, 7);
1662rd += R_rd_0.read(ba) << 0;
1663etiss_uint8 rs1 = 0;
1664static BitArrayRange R_rs1_0(19, 15);
1665rs1 += R_rs1_0.read(ba) << 0;
1666etiss_uint16 imm = 0;
1667static BitArrayRange R_imm_0(31, 20);
1668imm += R_imm_0.read(ba) << 0;
1669
1670// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1671// -----------------------------------------------------------------------------
1672
1673 {
1674 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1675
1676 cp.code() = std::string("//LHU\n");
1677
1678// -----------------------------------------------------------------------------
1679cp.code() += "etiss_coverage_count(1, 14);\n";
1680{ // block
1681cp.code() += "etiss_coverage_count(1, 1169);\n";
1682cp.code() += "{ // block\n";
1683cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1684cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1685cp.code() += "} // block\n";
1686} // block
1687{ // block
1688cp.code() += "etiss_coverage_count(1, 1634);\n";
1689cp.code() += "{ // block\n";
1690cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1691cp.code() += "etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";
1692cp.code() += "etiss_uint16 mem_val_0;\n";
1693cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1694cp.code() += "if (cpu->exception) { // conditional\n";
1695{ // procedure
1696cp.code() += "{ // procedure\n";
1697cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1698cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1699cp.code() += "} // procedure\n";
1700} // procedure
1701cp.code() += "} // conditional\n";
1702cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
1703cp.code() += "etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";
1704cp.code() += "etiss_coverage_count(1, 1618);\n";
1705if ((rd % 32ULL) != 0LL) { // conditional
1706cp.code() += "etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";
1707cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1708cp.code() += "etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";
1709} // conditional
1710cp.code() += "} // block\n";
1711} // block
1712cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1713cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1714// -----------------------------------------------------------------------------
1715 cp.getAffectedRegisters().add("instructionPointer", 32);
1716 }
1717 {
1718 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1719
1720 cp.code() = std::string("//LHU\n");
1721
1722// -----------------------------------------------------------------------------
1723cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1724// -----------------------------------------------------------------------------
1725 }
1726
1727 return true;
1728 },
1729 0,
1730 [] (BitArray & ba, Instruction & instr)
1731 {
1732// -----------------------------------------------------------------------------
1733etiss_uint8 rd = 0;
1734static BitArrayRange R_rd_0(11, 7);
1735rd += R_rd_0.read(ba) << 0;
1736etiss_uint8 rs1 = 0;
1737static BitArrayRange R_rs1_0(19, 15);
1738rs1 += R_rs1_0.read(ba) << 0;
1739etiss_uint16 imm = 0;
1740static BitArrayRange R_imm_0(31, 20);
1741imm += R_imm_0.read(ba) << 0;
1742
1743// -----------------------------------------------------------------------------
1744
1745 std::stringstream ss;
1746// -----------------------------------------------------------------------------
1747ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1748// -----------------------------------------------------------------------------
1749 return ss.str();
1750 }
1751);
1752
1753// SB --------------------------------------------------------------------------
1754static InstructionDefinition sb_imm_rs1_rs2 (
1755 ISA32_RV64IMACFD,
1756 "sb",
1757 (uint32_t) 0x000023,
1758 (uint32_t) 0x00707f,
1759 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1760 {
1761
1762// -----------------------------------------------------------------------------
1763
1764// -----------------------------------------------------------------------------
1765
1766// -----------------------------------------------------------------------------
1767// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1768etiss_uint16 imm = 0;
1769static BitArrayRange R_imm_0(11, 7);
1770imm += R_imm_0.read(ba) << 0;
1771etiss_uint8 rs1 = 0;
1772static BitArrayRange R_rs1_0(19, 15);
1773rs1 += R_rs1_0.read(ba) << 0;
1774etiss_uint8 rs2 = 0;
1775static BitArrayRange R_rs2_0(24, 20);
1776rs2 += R_rs2_0.read(ba) << 0;
1777static BitArrayRange R_imm_5(31, 25);
1778imm += R_imm_5.read(ba) << 5;
1779
1780// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1781// -----------------------------------------------------------------------------
1782
1783 {
1784 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1785
1786 cp.code() = std::string("//SB\n");
1787
1788// -----------------------------------------------------------------------------
1789cp.code() += "etiss_coverage_count(1, 15);\n";
1790{ // block
1791cp.code() += "etiss_coverage_count(1, 1169);\n";
1792cp.code() += "{ // block\n";
1793cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1794cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1795cp.code() += "} // block\n";
1796} // block
1797{ // block
1798cp.code() += "etiss_coverage_count(1, 1656);\n";
1799cp.code() += "{ // block\n";
1800cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1801cp.code() += "etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";
1802cp.code() += "etiss_uint8 mem_val_0;\n";
1803cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1804cp.code() += "etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";
1805cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
1806cp.code() += "if (cpu->exception) { // conditional\n";
1807{ // procedure
1808cp.code() += "{ // procedure\n";
1809cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1810cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1811cp.code() += "} // procedure\n";
1812} // procedure
1813cp.code() += "} // conditional\n";
1814cp.code() += "} // block\n";
1815} // block
1816cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1817cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1818// -----------------------------------------------------------------------------
1819 cp.getAffectedRegisters().add("instructionPointer", 32);
1820 }
1821 {
1822 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1823
1824 cp.code() = std::string("//SB\n");
1825
1826// -----------------------------------------------------------------------------
1827cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1828// -----------------------------------------------------------------------------
1829 }
1830
1831 return true;
1832 },
1833 0,
1834 [] (BitArray & ba, Instruction & instr)
1835 {
1836// -----------------------------------------------------------------------------
1837etiss_uint16 imm = 0;
1838static BitArrayRange R_imm_0(11, 7);
1839imm += R_imm_0.read(ba) << 0;
1840etiss_uint8 rs1 = 0;
1841static BitArrayRange R_rs1_0(19, 15);
1842rs1 += R_rs1_0.read(ba) << 0;
1843etiss_uint8 rs2 = 0;
1844static BitArrayRange R_rs2_0(24, 20);
1845rs2 += R_rs2_0.read(ba) << 0;
1846static BitArrayRange R_imm_5(31, 25);
1847imm += R_imm_5.read(ba) << 5;
1848
1849// -----------------------------------------------------------------------------
1850
1851 std::stringstream ss;
1852// -----------------------------------------------------------------------------
1853ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1854// -----------------------------------------------------------------------------
1855 return ss.str();
1856 }
1857);
1858
1859// SH --------------------------------------------------------------------------
1860static InstructionDefinition sh_imm_rs1_rs2 (
1861 ISA32_RV64IMACFD,
1862 "sh",
1863 (uint32_t) 0x001023,
1864 (uint32_t) 0x00707f,
1865 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1866 {
1867
1868// -----------------------------------------------------------------------------
1869
1870// -----------------------------------------------------------------------------
1871
1872// -----------------------------------------------------------------------------
1873// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1874etiss_uint16 imm = 0;
1875static BitArrayRange R_imm_0(11, 7);
1876imm += R_imm_0.read(ba) << 0;
1877etiss_uint8 rs1 = 0;
1878static BitArrayRange R_rs1_0(19, 15);
1879rs1 += R_rs1_0.read(ba) << 0;
1880etiss_uint8 rs2 = 0;
1881static BitArrayRange R_rs2_0(24, 20);
1882rs2 += R_rs2_0.read(ba) << 0;
1883static BitArrayRange R_imm_5(31, 25);
1884imm += R_imm_5.read(ba) << 5;
1885
1886// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1887// -----------------------------------------------------------------------------
1888
1889 {
1890 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1891
1892 cp.code() = std::string("//SH\n");
1893
1894// -----------------------------------------------------------------------------
1895cp.code() += "etiss_coverage_count(1, 16);\n";
1896{ // block
1897cp.code() += "etiss_coverage_count(1, 1169);\n";
1898cp.code() += "{ // block\n";
1899cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1900cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1901cp.code() += "} // block\n";
1902} // block
1903{ // block
1904cp.code() += "etiss_coverage_count(1, 1678);\n";
1905cp.code() += "{ // block\n";
1906cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1907cp.code() += "etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";
1908cp.code() += "etiss_uint16 mem_val_0;\n";
1909cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1910cp.code() += "etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";
1911cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
1912cp.code() += "if (cpu->exception) { // conditional\n";
1913{ // procedure
1914cp.code() += "{ // procedure\n";
1915cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1916cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1917cp.code() += "} // procedure\n";
1918} // procedure
1919cp.code() += "} // conditional\n";
1920cp.code() += "} // block\n";
1921} // block
1922cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1923cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1924// -----------------------------------------------------------------------------
1925 cp.getAffectedRegisters().add("instructionPointer", 32);
1926 }
1927 {
1928 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1929
1930 cp.code() = std::string("//SH\n");
1931
1932// -----------------------------------------------------------------------------
1933cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1934// -----------------------------------------------------------------------------
1935 }
1936
1937 return true;
1938 },
1939 0,
1940 [] (BitArray & ba, Instruction & instr)
1941 {
1942// -----------------------------------------------------------------------------
1943etiss_uint16 imm = 0;
1944static BitArrayRange R_imm_0(11, 7);
1945imm += R_imm_0.read(ba) << 0;
1946etiss_uint8 rs1 = 0;
1947static BitArrayRange R_rs1_0(19, 15);
1948rs1 += R_rs1_0.read(ba) << 0;
1949etiss_uint8 rs2 = 0;
1950static BitArrayRange R_rs2_0(24, 20);
1951rs2 += R_rs2_0.read(ba) << 0;
1952static BitArrayRange R_imm_5(31, 25);
1953imm += R_imm_5.read(ba) << 5;
1954
1955// -----------------------------------------------------------------------------
1956
1957 std::stringstream ss;
1958// -----------------------------------------------------------------------------
1959ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1960// -----------------------------------------------------------------------------
1961 return ss.str();
1962 }
1963);
1964
1965// SW --------------------------------------------------------------------------
1966static InstructionDefinition sw_imm_rs1_rs2 (
1967 ISA32_RV64IMACFD,
1968 "sw",
1969 (uint32_t) 0x002023,
1970 (uint32_t) 0x00707f,
1971 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1972 {
1973
1974// -----------------------------------------------------------------------------
1975
1976// -----------------------------------------------------------------------------
1977
1978// -----------------------------------------------------------------------------
1979// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1980etiss_uint16 imm = 0;
1981static BitArrayRange R_imm_0(11, 7);
1982imm += R_imm_0.read(ba) << 0;
1983etiss_uint8 rs1 = 0;
1984static BitArrayRange R_rs1_0(19, 15);
1985rs1 += R_rs1_0.read(ba) << 0;
1986etiss_uint8 rs2 = 0;
1987static BitArrayRange R_rs2_0(24, 20);
1988rs2 += R_rs2_0.read(ba) << 0;
1989static BitArrayRange R_imm_5(31, 25);
1990imm += R_imm_5.read(ba) << 5;
1991
1992// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1993// -----------------------------------------------------------------------------
1994
1995 {
1996 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1997
1998 cp.code() = std::string("//SW\n");
1999
2000// -----------------------------------------------------------------------------
2001cp.code() += "etiss_coverage_count(1, 17);\n";
2002{ // block
2003cp.code() += "etiss_coverage_count(1, 1169);\n";
2004cp.code() += "{ // block\n";
2005cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2006cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2007cp.code() += "} // block\n";
2008} // block
2009{ // block
2010cp.code() += "etiss_coverage_count(1, 1700);\n";
2011cp.code() += "{ // block\n";
2012cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
2013cp.code() += "etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";
2014cp.code() += "etiss_uint32 mem_val_0;\n";
2015cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
2016cp.code() += "etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";
2017cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
2018cp.code() += "if (cpu->exception) { // conditional\n";
2019{ // procedure
2020cp.code() += "{ // procedure\n";
2021cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
2022cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2023cp.code() += "} // procedure\n";
2024} // procedure
2025cp.code() += "} // conditional\n";
2026cp.code() += "} // block\n";
2027} // block
2028cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2029cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2030// -----------------------------------------------------------------------------
2031 cp.getAffectedRegisters().add("instructionPointer", 32);
2032 }
2033 {
2034 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2035
2036 cp.code() = std::string("//SW\n");
2037
2038// -----------------------------------------------------------------------------
2039cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2040// -----------------------------------------------------------------------------
2041 }
2042
2043 return true;
2044 },
2045 0,
2046 [] (BitArray & ba, Instruction & instr)
2047 {
2048// -----------------------------------------------------------------------------
2049etiss_uint16 imm = 0;
2050static BitArrayRange R_imm_0(11, 7);
2051imm += R_imm_0.read(ba) << 0;
2052etiss_uint8 rs1 = 0;
2053static BitArrayRange R_rs1_0(19, 15);
2054rs1 += R_rs1_0.read(ba) << 0;
2055etiss_uint8 rs2 = 0;
2056static BitArrayRange R_rs2_0(24, 20);
2057rs2 += R_rs2_0.read(ba) << 0;
2058static BitArrayRange R_imm_5(31, 25);
2059imm += R_imm_5.read(ba) << 5;
2060
2061// -----------------------------------------------------------------------------
2062
2063 std::stringstream ss;
2064// -----------------------------------------------------------------------------
2065ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2066// -----------------------------------------------------------------------------
2067 return ss.str();
2068 }
2069);
2070
2071// ADDI ------------------------------------------------------------------------
2072static InstructionDefinition addi_rd_rs1_imm (
2073 ISA32_RV64IMACFD,
2074 "addi",
2075 (uint32_t) 0x000013,
2076 (uint32_t) 0x00707f,
2077 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2078 {
2079
2080// -----------------------------------------------------------------------------
2081
2082// -----------------------------------------------------------------------------
2083
2084// -----------------------------------------------------------------------------
2085// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2086etiss_uint8 rd = 0;
2087static BitArrayRange R_rd_0(11, 7);
2088rd += R_rd_0.read(ba) << 0;
2089etiss_uint8 rs1 = 0;
2090static BitArrayRange R_rs1_0(19, 15);
2091rs1 += R_rs1_0.read(ba) << 0;
2092etiss_uint16 imm = 0;
2093static BitArrayRange R_imm_0(31, 20);
2094imm += R_imm_0.read(ba) << 0;
2095
2096// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2097// -----------------------------------------------------------------------------
2098
2099 {
2100 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2101
2102 cp.code() = std::string("//ADDI\n");
2103
2104// -----------------------------------------------------------------------------
2105cp.code() += "etiss_coverage_count(1, 18);\n";
2106{ // block
2107cp.code() += "etiss_coverage_count(1, 1169);\n";
2108cp.code() += "{ // block\n";
2109cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2110cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2111cp.code() += "} // block\n";
2112} // block
2113cp.code() += "etiss_coverage_count(1, 1701);\n";
2114if ((rd % 32ULL) != 0LL) { // conditional
2115cp.code() += "etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";
2116cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
2117cp.code() += "etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";
2118} // conditional
2119cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2120cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2121// -----------------------------------------------------------------------------
2122 cp.getAffectedRegisters().add("instructionPointer", 32);
2123 }
2124
2125 return true;
2126 },
2127 0,
2128 [] (BitArray & ba, Instruction & instr)
2129 {
2130// -----------------------------------------------------------------------------
2131etiss_uint8 rd = 0;
2132static BitArrayRange R_rd_0(11, 7);
2133rd += R_rd_0.read(ba) << 0;
2134etiss_uint8 rs1 = 0;
2135static BitArrayRange R_rs1_0(19, 15);
2136rs1 += R_rs1_0.read(ba) << 0;
2137etiss_uint16 imm = 0;
2138static BitArrayRange R_imm_0(31, 20);
2139imm += R_imm_0.read(ba) << 0;
2140
2141// -----------------------------------------------------------------------------
2142
2143 std::stringstream ss;
2144// -----------------------------------------------------------------------------
2145ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2146// -----------------------------------------------------------------------------
2147 return ss.str();
2148 }
2149);
2150
2151// SLTI ------------------------------------------------------------------------
2152static InstructionDefinition slti_rd_rs1_imm (
2153 ISA32_RV64IMACFD,
2154 "slti",
2155 (uint32_t) 0x002013,
2156 (uint32_t) 0x00707f,
2157 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2158 {
2159
2160// -----------------------------------------------------------------------------
2161
2162// -----------------------------------------------------------------------------
2163
2164// -----------------------------------------------------------------------------
2165// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2166etiss_uint8 rd = 0;
2167static BitArrayRange R_rd_0(11, 7);
2168rd += R_rd_0.read(ba) << 0;
2169etiss_uint8 rs1 = 0;
2170static BitArrayRange R_rs1_0(19, 15);
2171rs1 += R_rs1_0.read(ba) << 0;
2172etiss_uint16 imm = 0;
2173static BitArrayRange R_imm_0(31, 20);
2174imm += R_imm_0.read(ba) << 0;
2175
2176// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2177// -----------------------------------------------------------------------------
2178
2179 {
2180 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2181
2182 cp.code() = std::string("//SLTI\n");
2183
2184// -----------------------------------------------------------------------------
2185cp.code() += "etiss_coverage_count(1, 19);\n";
2186{ // block
2187cp.code() += "etiss_coverage_count(1, 1169);\n";
2188cp.code() += "{ // block\n";
2189cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2190cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2191cp.code() += "} // block\n";
2192} // block
2193cp.code() += "etiss_coverage_count(1, 1722);\n";
2194if ((rd % 32ULL) != 0LL) { // conditional
2195cp.code() += "etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";
2196cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0LL);\n";
2197cp.code() += "etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";
2198} // conditional
2199cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2200cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2201// -----------------------------------------------------------------------------
2202 cp.getAffectedRegisters().add("instructionPointer", 32);
2203 }
2204
2205 return true;
2206 },
2207 0,
2208 [] (BitArray & ba, Instruction & instr)
2209 {
2210// -----------------------------------------------------------------------------
2211etiss_uint8 rd = 0;
2212static BitArrayRange R_rd_0(11, 7);
2213rd += R_rd_0.read(ba) << 0;
2214etiss_uint8 rs1 = 0;
2215static BitArrayRange R_rs1_0(19, 15);
2216rs1 += R_rs1_0.read(ba) << 0;
2217etiss_uint16 imm = 0;
2218static BitArrayRange R_imm_0(31, 20);
2219imm += R_imm_0.read(ba) << 0;
2220
2221// -----------------------------------------------------------------------------
2222
2223 std::stringstream ss;
2224// -----------------------------------------------------------------------------
2225ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2226// -----------------------------------------------------------------------------
2227 return ss.str();
2228 }
2229);
2230
2231// SLTIU -----------------------------------------------------------------------
2232static InstructionDefinition sltiu_rd_rs1_imm (
2233 ISA32_RV64IMACFD,
2234 "sltiu",
2235 (uint32_t) 0x003013,
2236 (uint32_t) 0x00707f,
2237 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2238 {
2239
2240// -----------------------------------------------------------------------------
2241
2242// -----------------------------------------------------------------------------
2243
2244// -----------------------------------------------------------------------------
2245// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2246etiss_uint8 rd = 0;
2247static BitArrayRange R_rd_0(11, 7);
2248rd += R_rd_0.read(ba) << 0;
2249etiss_uint8 rs1 = 0;
2250static BitArrayRange R_rs1_0(19, 15);
2251rs1 += R_rs1_0.read(ba) << 0;
2252etiss_uint16 imm = 0;
2253static BitArrayRange R_imm_0(31, 20);
2254imm += R_imm_0.read(ba) << 0;
2255
2256// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2257// -----------------------------------------------------------------------------
2258
2259 {
2260 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2261
2262 cp.code() = std::string("//SLTIU\n");
2263
2264// -----------------------------------------------------------------------------
2265cp.code() += "etiss_coverage_count(1, 20);\n";
2266{ // block
2267cp.code() += "etiss_coverage_count(1, 1169);\n";
2268cp.code() += "{ // block\n";
2269cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2270cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2271cp.code() += "} // block\n";
2272} // block
2273cp.code() += "etiss_coverage_count(1, 1748);\n";
2274if ((rd % 32ULL) != 0LL) { // conditional
2275cp.code() += "etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";
2276cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0LL);\n";
2277cp.code() += "etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";
2278} // conditional
2279cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2280cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2281// -----------------------------------------------------------------------------
2282 cp.getAffectedRegisters().add("instructionPointer", 32);
2283 }
2284
2285 return true;
2286 },
2287 0,
2288 [] (BitArray & ba, Instruction & instr)
2289 {
2290// -----------------------------------------------------------------------------
2291etiss_uint8 rd = 0;
2292static BitArrayRange R_rd_0(11, 7);
2293rd += R_rd_0.read(ba) << 0;
2294etiss_uint8 rs1 = 0;
2295static BitArrayRange R_rs1_0(19, 15);
2296rs1 += R_rs1_0.read(ba) << 0;
2297etiss_uint16 imm = 0;
2298static BitArrayRange R_imm_0(31, 20);
2299imm += R_imm_0.read(ba) << 0;
2300
2301// -----------------------------------------------------------------------------
2302
2303 std::stringstream ss;
2304// -----------------------------------------------------------------------------
2305ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2306// -----------------------------------------------------------------------------
2307 return ss.str();
2308 }
2309);
2310
2311// XORI ------------------------------------------------------------------------
2312static InstructionDefinition xori_rd_rs1_imm (
2313 ISA32_RV64IMACFD,
2314 "xori",
2315 (uint32_t) 0x004013,
2316 (uint32_t) 0x00707f,
2317 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2318 {
2319
2320// -----------------------------------------------------------------------------
2321
2322// -----------------------------------------------------------------------------
2323
2324// -----------------------------------------------------------------------------
2325// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2326etiss_uint8 rd = 0;
2327static BitArrayRange R_rd_0(11, 7);
2328rd += R_rd_0.read(ba) << 0;
2329etiss_uint8 rs1 = 0;
2330static BitArrayRange R_rs1_0(19, 15);
2331rs1 += R_rs1_0.read(ba) << 0;
2332etiss_uint16 imm = 0;
2333static BitArrayRange R_imm_0(31, 20);
2334imm += R_imm_0.read(ba) << 0;
2335
2336// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2337// -----------------------------------------------------------------------------
2338
2339 {
2340 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2341
2342 cp.code() = std::string("//XORI\n");
2343
2344// -----------------------------------------------------------------------------
2345cp.code() += "etiss_coverage_count(1, 21);\n";
2346{ // block
2347cp.code() += "etiss_coverage_count(1, 1169);\n";
2348cp.code() += "{ // block\n";
2349cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2350cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2351cp.code() += "} // block\n";
2352} // block
2353cp.code() += "etiss_coverage_count(1, 1776);\n";
2354if ((rd % 32ULL) != 0LL) { // conditional
2355cp.code() += "etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";
2356cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2357cp.code() += "etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";
2358} // conditional
2359cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2360cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2361// -----------------------------------------------------------------------------
2362 cp.getAffectedRegisters().add("instructionPointer", 32);
2363 }
2364
2365 return true;
2366 },
2367 0,
2368 [] (BitArray & ba, Instruction & instr)
2369 {
2370// -----------------------------------------------------------------------------
2371etiss_uint8 rd = 0;
2372static BitArrayRange R_rd_0(11, 7);
2373rd += R_rd_0.read(ba) << 0;
2374etiss_uint8 rs1 = 0;
2375static BitArrayRange R_rs1_0(19, 15);
2376rs1 += R_rs1_0.read(ba) << 0;
2377etiss_uint16 imm = 0;
2378static BitArrayRange R_imm_0(31, 20);
2379imm += R_imm_0.read(ba) << 0;
2380
2381// -----------------------------------------------------------------------------
2382
2383 std::stringstream ss;
2384// -----------------------------------------------------------------------------
2385ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2386// -----------------------------------------------------------------------------
2387 return ss.str();
2388 }
2389);
2390
2391// ORI -------------------------------------------------------------------------
2392static InstructionDefinition ori_rd_rs1_imm (
2393 ISA32_RV64IMACFD,
2394 "ori",
2395 (uint32_t) 0x006013,
2396 (uint32_t) 0x00707f,
2397 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2398 {
2399
2400// -----------------------------------------------------------------------------
2401
2402// -----------------------------------------------------------------------------
2403
2404// -----------------------------------------------------------------------------
2405// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2406etiss_uint8 rd = 0;
2407static BitArrayRange R_rd_0(11, 7);
2408rd += R_rd_0.read(ba) << 0;
2409etiss_uint8 rs1 = 0;
2410static BitArrayRange R_rs1_0(19, 15);
2411rs1 += R_rs1_0.read(ba) << 0;
2412etiss_uint16 imm = 0;
2413static BitArrayRange R_imm_0(31, 20);
2414imm += R_imm_0.read(ba) << 0;
2415
2416// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2417// -----------------------------------------------------------------------------
2418
2419 {
2420 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2421
2422 cp.code() = std::string("//ORI\n");
2423
2424// -----------------------------------------------------------------------------
2425cp.code() += "etiss_coverage_count(1, 22);\n";
2426{ // block
2427cp.code() += "etiss_coverage_count(1, 1169);\n";
2428cp.code() += "{ // block\n";
2429cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2430cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2431cp.code() += "} // block\n";
2432} // block
2433cp.code() += "etiss_coverage_count(1, 1800);\n";
2434if ((rd % 32ULL) != 0LL) { // conditional
2435cp.code() += "etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";
2436cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2437cp.code() += "etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";
2438} // conditional
2439cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2440cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2441// -----------------------------------------------------------------------------
2442 cp.getAffectedRegisters().add("instructionPointer", 32);
2443 }
2444
2445 return true;
2446 },
2447 0,
2448 [] (BitArray & ba, Instruction & instr)
2449 {
2450// -----------------------------------------------------------------------------
2451etiss_uint8 rd = 0;
2452static BitArrayRange R_rd_0(11, 7);
2453rd += R_rd_0.read(ba) << 0;
2454etiss_uint8 rs1 = 0;
2455static BitArrayRange R_rs1_0(19, 15);
2456rs1 += R_rs1_0.read(ba) << 0;
2457etiss_uint16 imm = 0;
2458static BitArrayRange R_imm_0(31, 20);
2459imm += R_imm_0.read(ba) << 0;
2460
2461// -----------------------------------------------------------------------------
2462
2463 std::stringstream ss;
2464// -----------------------------------------------------------------------------
2465ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2466// -----------------------------------------------------------------------------
2467 return ss.str();
2468 }
2469);
2470
2471// ANDI ------------------------------------------------------------------------
2472static InstructionDefinition andi_rd_rs1_imm (
2473 ISA32_RV64IMACFD,
2474 "andi",
2475 (uint32_t) 0x007013,
2476 (uint32_t) 0x00707f,
2477 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2478 {
2479
2480// -----------------------------------------------------------------------------
2481
2482// -----------------------------------------------------------------------------
2483
2484// -----------------------------------------------------------------------------
2485// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2486etiss_uint8 rd = 0;
2487static BitArrayRange R_rd_0(11, 7);
2488rd += R_rd_0.read(ba) << 0;
2489etiss_uint8 rs1 = 0;
2490static BitArrayRange R_rs1_0(19, 15);
2491rs1 += R_rs1_0.read(ba) << 0;
2492etiss_uint16 imm = 0;
2493static BitArrayRange R_imm_0(31, 20);
2494imm += R_imm_0.read(ba) << 0;
2495
2496// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2497// -----------------------------------------------------------------------------
2498
2499 {
2500 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2501
2502 cp.code() = std::string("//ANDI\n");
2503
2504// -----------------------------------------------------------------------------
2505cp.code() += "etiss_coverage_count(1, 23);\n";
2506{ // block
2507cp.code() += "etiss_coverage_count(1, 1169);\n";
2508cp.code() += "{ // block\n";
2509cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2510cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2511cp.code() += "} // block\n";
2512} // block
2513cp.code() += "etiss_coverage_count(1, 1824);\n";
2514if ((rd % 32ULL) != 0LL) { // conditional
2515cp.code() += "etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";
2516cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2517cp.code() += "etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";
2518} // conditional
2519cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2520cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2521// -----------------------------------------------------------------------------
2522 cp.getAffectedRegisters().add("instructionPointer", 32);
2523 }
2524
2525 return true;
2526 },
2527 0,
2528 [] (BitArray & ba, Instruction & instr)
2529 {
2530// -----------------------------------------------------------------------------
2531etiss_uint8 rd = 0;
2532static BitArrayRange R_rd_0(11, 7);
2533rd += R_rd_0.read(ba) << 0;
2534etiss_uint8 rs1 = 0;
2535static BitArrayRange R_rs1_0(19, 15);
2536rs1 += R_rs1_0.read(ba) << 0;
2537etiss_uint16 imm = 0;
2538static BitArrayRange R_imm_0(31, 20);
2539imm += R_imm_0.read(ba) << 0;
2540
2541// -----------------------------------------------------------------------------
2542
2543 std::stringstream ss;
2544// -----------------------------------------------------------------------------
2545ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2546// -----------------------------------------------------------------------------
2547 return ss.str();
2548 }
2549);
2550
2551// SLLI ------------------------------------------------------------------------
2552static InstructionDefinition slli_rd_rs1_shamt (
2553 ISA32_RV64IMACFD,
2554 "slli",
2555 (uint32_t) 0x001013,
2556 (uint32_t) 0xfe00707f,
2557 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2558 {
2559
2560// -----------------------------------------------------------------------------
2561
2562// -----------------------------------------------------------------------------
2563
2564// -----------------------------------------------------------------------------
2565// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2566etiss_uint8 rd = 0;
2567static BitArrayRange R_rd_0(11, 7);
2568rd += R_rd_0.read(ba) << 0;
2569etiss_uint8 rs1 = 0;
2570static BitArrayRange R_rs1_0(19, 15);
2571rs1 += R_rs1_0.read(ba) << 0;
2572etiss_uint8 shamt = 0;
2573static BitArrayRange R_shamt_0(24, 20);
2574shamt += R_shamt_0.read(ba) << 0;
2575
2576// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2577// -----------------------------------------------------------------------------
2578
2579 {
2580 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2581
2582 cp.code() = std::string("//SLLI\n");
2583
2584// -----------------------------------------------------------------------------
2585cp.code() += "etiss_coverage_count(1, 24);\n";
2586{ // block
2587cp.code() += "etiss_coverage_count(1, 1169);\n";
2588cp.code() += "{ // block\n";
2589cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2590cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2591cp.code() += "} // block\n";
2592} // block
2593cp.code() += "etiss_coverage_count(1, 1848);\n";
2594if ((rd % 32ULL) != 0LL) { // conditional
2595cp.code() += "etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";
2596cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
2597cp.code() += "etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";
2598} // conditional
2599cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2600cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2601// -----------------------------------------------------------------------------
2602 cp.getAffectedRegisters().add("instructionPointer", 32);
2603 }
2604
2605 return true;
2606 },
2607 0,
2608 [] (BitArray & ba, Instruction & instr)
2609 {
2610// -----------------------------------------------------------------------------
2611etiss_uint8 rd = 0;
2612static BitArrayRange R_rd_0(11, 7);
2613rd += R_rd_0.read(ba) << 0;
2614etiss_uint8 rs1 = 0;
2615static BitArrayRange R_rs1_0(19, 15);
2616rs1 += R_rs1_0.read(ba) << 0;
2617etiss_uint8 shamt = 0;
2618static BitArrayRange R_shamt_0(24, 20);
2619shamt += R_shamt_0.read(ba) << 0;
2620
2621// -----------------------------------------------------------------------------
2622
2623 std::stringstream ss;
2624// -----------------------------------------------------------------------------
2625ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2626// -----------------------------------------------------------------------------
2627 return ss.str();
2628 }
2629);
2630
2631// SRLI ------------------------------------------------------------------------
2632static InstructionDefinition srli_rd_rs1_shamt (
2633 ISA32_RV64IMACFD,
2634 "srli",
2635 (uint32_t) 0x005013,
2636 (uint32_t) 0xfe00707f,
2637 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2638 {
2639
2640// -----------------------------------------------------------------------------
2641
2642// -----------------------------------------------------------------------------
2643
2644// -----------------------------------------------------------------------------
2645// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2646etiss_uint8 rd = 0;
2647static BitArrayRange R_rd_0(11, 7);
2648rd += R_rd_0.read(ba) << 0;
2649etiss_uint8 rs1 = 0;
2650static BitArrayRange R_rs1_0(19, 15);
2651rs1 += R_rs1_0.read(ba) << 0;
2652etiss_uint8 shamt = 0;
2653static BitArrayRange R_shamt_0(24, 20);
2654shamt += R_shamt_0.read(ba) << 0;
2655
2656// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2657// -----------------------------------------------------------------------------
2658
2659 {
2660 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2661
2662 cp.code() = std::string("//SRLI\n");
2663
2664// -----------------------------------------------------------------------------
2665cp.code() += "etiss_coverage_count(1, 25);\n";
2666{ // block
2667cp.code() += "etiss_coverage_count(1, 1169);\n";
2668cp.code() += "{ // block\n";
2669cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2670cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2671cp.code() += "} // block\n";
2672} // block
2673cp.code() += "etiss_coverage_count(1, 1868);\n";
2674if ((rd % 32ULL) != 0LL) { // conditional
2675cp.code() += "etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";
2676cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
2677cp.code() += "etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";
2678} // conditional
2679cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2680cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2681// -----------------------------------------------------------------------------
2682 cp.getAffectedRegisters().add("instructionPointer", 32);
2683 }
2684
2685 return true;
2686 },
2687 0,
2688 [] (BitArray & ba, Instruction & instr)
2689 {
2690// -----------------------------------------------------------------------------
2691etiss_uint8 rd = 0;
2692static BitArrayRange R_rd_0(11, 7);
2693rd += R_rd_0.read(ba) << 0;
2694etiss_uint8 rs1 = 0;
2695static BitArrayRange R_rs1_0(19, 15);
2696rs1 += R_rs1_0.read(ba) << 0;
2697etiss_uint8 shamt = 0;
2698static BitArrayRange R_shamt_0(24, 20);
2699shamt += R_shamt_0.read(ba) << 0;
2700
2701// -----------------------------------------------------------------------------
2702
2703 std::stringstream ss;
2704// -----------------------------------------------------------------------------
2705ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2706// -----------------------------------------------------------------------------
2707 return ss.str();
2708 }
2709);
2710
2711// SRAI ------------------------------------------------------------------------
2712static InstructionDefinition srai_rd_rs1_shamt (
2713 ISA32_RV64IMACFD,
2714 "srai",
2715 (uint32_t) 0x40005013,
2716 (uint32_t) 0xfe00707f,
2717 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2718 {
2719
2720// -----------------------------------------------------------------------------
2721
2722// -----------------------------------------------------------------------------
2723
2724// -----------------------------------------------------------------------------
2725// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2726etiss_uint8 rd = 0;
2727static BitArrayRange R_rd_0(11, 7);
2728rd += R_rd_0.read(ba) << 0;
2729etiss_uint8 rs1 = 0;
2730static BitArrayRange R_rs1_0(19, 15);
2731rs1 += R_rs1_0.read(ba) << 0;
2732etiss_uint8 shamt = 0;
2733static BitArrayRange R_shamt_0(24, 20);
2734shamt += R_shamt_0.read(ba) << 0;
2735
2736// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2737// -----------------------------------------------------------------------------
2738
2739 {
2740 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2741
2742 cp.code() = std::string("//SRAI\n");
2743
2744// -----------------------------------------------------------------------------
2745cp.code() += "etiss_coverage_count(1, 26);\n";
2746{ // block
2747cp.code() += "etiss_coverage_count(1, 1169);\n";
2748cp.code() += "{ // block\n";
2749cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2750cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2751cp.code() += "} // block\n";
2752} // block
2753cp.code() += "etiss_coverage_count(1, 1888);\n";
2754if ((rd % 32ULL) != 0LL) { // conditional
2755cp.code() += "etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";
2756cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
2757cp.code() += "etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";
2758} // conditional
2759cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2760cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2761// -----------------------------------------------------------------------------
2762 cp.getAffectedRegisters().add("instructionPointer", 32);
2763 }
2764
2765 return true;
2766 },
2767 0,
2768 [] (BitArray & ba, Instruction & instr)
2769 {
2770// -----------------------------------------------------------------------------
2771etiss_uint8 rd = 0;
2772static BitArrayRange R_rd_0(11, 7);
2773rd += R_rd_0.read(ba) << 0;
2774etiss_uint8 rs1 = 0;
2775static BitArrayRange R_rs1_0(19, 15);
2776rs1 += R_rs1_0.read(ba) << 0;
2777etiss_uint8 shamt = 0;
2778static BitArrayRange R_shamt_0(24, 20);
2779shamt += R_shamt_0.read(ba) << 0;
2780
2781// -----------------------------------------------------------------------------
2782
2783 std::stringstream ss;
2784// -----------------------------------------------------------------------------
2785ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2786// -----------------------------------------------------------------------------
2787 return ss.str();
2788 }
2789);
2790
2791// ADD -------------------------------------------------------------------------
2792static InstructionDefinition add_rd_rs1_rs2 (
2793 ISA32_RV64IMACFD,
2794 "add",
2795 (uint32_t) 0x000033,
2796 (uint32_t) 0xfe00707f,
2797 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2798 {
2799
2800// -----------------------------------------------------------------------------
2801
2802// -----------------------------------------------------------------------------
2803
2804// -----------------------------------------------------------------------------
2805// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2806etiss_uint8 rd = 0;
2807static BitArrayRange R_rd_0(11, 7);
2808rd += R_rd_0.read(ba) << 0;
2809etiss_uint8 rs1 = 0;
2810static BitArrayRange R_rs1_0(19, 15);
2811rs1 += R_rs1_0.read(ba) << 0;
2812etiss_uint8 rs2 = 0;
2813static BitArrayRange R_rs2_0(24, 20);
2814rs2 += R_rs2_0.read(ba) << 0;
2815
2816// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2817// -----------------------------------------------------------------------------
2818
2819 {
2820 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2821
2822 cp.code() = std::string("//ADD\n");
2823
2824// -----------------------------------------------------------------------------
2825cp.code() += "etiss_coverage_count(1, 27);\n";
2826{ // block
2827cp.code() += "etiss_coverage_count(1, 1169);\n";
2828cp.code() += "{ // block\n";
2829cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2830cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2831cp.code() += "} // block\n";
2832} // block
2833cp.code() += "etiss_coverage_count(1, 1910);\n";
2834if ((rd % 32ULL) != 0LL) { // conditional
2835cp.code() += "etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";
2836cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2837cp.code() += "etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";
2838} // conditional
2839cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2840cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2841// -----------------------------------------------------------------------------
2842 cp.getAffectedRegisters().add("instructionPointer", 32);
2843 }
2844
2845 return true;
2846 },
2847 0,
2848 [] (BitArray & ba, Instruction & instr)
2849 {
2850// -----------------------------------------------------------------------------
2851etiss_uint8 rd = 0;
2852static BitArrayRange R_rd_0(11, 7);
2853rd += R_rd_0.read(ba) << 0;
2854etiss_uint8 rs1 = 0;
2855static BitArrayRange R_rs1_0(19, 15);
2856rs1 += R_rs1_0.read(ba) << 0;
2857etiss_uint8 rs2 = 0;
2858static BitArrayRange R_rs2_0(24, 20);
2859rs2 += R_rs2_0.read(ba) << 0;
2860
2861// -----------------------------------------------------------------------------
2862
2863 std::stringstream ss;
2864// -----------------------------------------------------------------------------
2865ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2866// -----------------------------------------------------------------------------
2867 return ss.str();
2868 }
2869);
2870
2871// SUB -------------------------------------------------------------------------
2872static InstructionDefinition sub_rd_rs1_rs2 (
2873 ISA32_RV64IMACFD,
2874 "sub",
2875 (uint32_t) 0x40000033,
2876 (uint32_t) 0xfe00707f,
2877 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2878 {
2879
2880// -----------------------------------------------------------------------------
2881
2882// -----------------------------------------------------------------------------
2883
2884// -----------------------------------------------------------------------------
2885// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2886etiss_uint8 rd = 0;
2887static BitArrayRange R_rd_0(11, 7);
2888rd += R_rd_0.read(ba) << 0;
2889etiss_uint8 rs1 = 0;
2890static BitArrayRange R_rs1_0(19, 15);
2891rs1 += R_rs1_0.read(ba) << 0;
2892etiss_uint8 rs2 = 0;
2893static BitArrayRange R_rs2_0(24, 20);
2894rs2 += R_rs2_0.read(ba) << 0;
2895
2896// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2897// -----------------------------------------------------------------------------
2898
2899 {
2900 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2901
2902 cp.code() = std::string("//SUB\n");
2903
2904// -----------------------------------------------------------------------------
2905cp.code() += "etiss_coverage_count(1, 28);\n";
2906{ // block
2907cp.code() += "etiss_coverage_count(1, 1169);\n";
2908cp.code() += "{ // block\n";
2909cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2910cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2911cp.code() += "} // block\n";
2912} // block
2913cp.code() += "etiss_coverage_count(1, 1934);\n";
2914if ((rd % 32ULL) != 0LL) { // conditional
2915cp.code() += "etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";
2916cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2917cp.code() += "etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";
2918} // conditional
2919cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2920cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2921// -----------------------------------------------------------------------------
2922 cp.getAffectedRegisters().add("instructionPointer", 32);
2923 }
2924
2925 return true;
2926 },
2927 0,
2928 [] (BitArray & ba, Instruction & instr)
2929 {
2930// -----------------------------------------------------------------------------
2931etiss_uint8 rd = 0;
2932static BitArrayRange R_rd_0(11, 7);
2933rd += R_rd_0.read(ba) << 0;
2934etiss_uint8 rs1 = 0;
2935static BitArrayRange R_rs1_0(19, 15);
2936rs1 += R_rs1_0.read(ba) << 0;
2937etiss_uint8 rs2 = 0;
2938static BitArrayRange R_rs2_0(24, 20);
2939rs2 += R_rs2_0.read(ba) << 0;
2940
2941// -----------------------------------------------------------------------------
2942
2943 std::stringstream ss;
2944// -----------------------------------------------------------------------------
2945ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2946// -----------------------------------------------------------------------------
2947 return ss.str();
2948 }
2949);
2950
2951// SLL -------------------------------------------------------------------------
2952static InstructionDefinition sll_rd_rs1_rs2 (
2953 ISA32_RV64IMACFD,
2954 "sll",
2955 (uint32_t) 0x001033,
2956 (uint32_t) 0xfe00707f,
2957 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2958 {
2959
2960// -----------------------------------------------------------------------------
2961
2962// -----------------------------------------------------------------------------
2963
2964// -----------------------------------------------------------------------------
2965// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2966etiss_uint8 rd = 0;
2967static BitArrayRange R_rd_0(11, 7);
2968rd += R_rd_0.read(ba) << 0;
2969etiss_uint8 rs1 = 0;
2970static BitArrayRange R_rs1_0(19, 15);
2971rs1 += R_rs1_0.read(ba) << 0;
2972etiss_uint8 rs2 = 0;
2973static BitArrayRange R_rs2_0(24, 20);
2974rs2 += R_rs2_0.read(ba) << 0;
2975
2976// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2977// -----------------------------------------------------------------------------
2978
2979 {
2980 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2981
2982 cp.code() = std::string("//SLL\n");
2983
2984// -----------------------------------------------------------------------------
2985cp.code() += "etiss_coverage_count(1, 29);\n";
2986{ // block
2987cp.code() += "etiss_coverage_count(1, 1169);\n";
2988cp.code() += "{ // block\n";
2989cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2990cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2991cp.code() += "} // block\n";
2992} // block
2993cp.code() += "etiss_coverage_count(1, 1958);\n";
2994if ((rd % 32ULL) != 0LL) { // conditional
2995cp.code() += "etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";
2996cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
2997cp.code() += "etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";
2998} // conditional
2999cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3000cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3001// -----------------------------------------------------------------------------
3002 cp.getAffectedRegisters().add("instructionPointer", 32);
3003 }
3004
3005 return true;
3006 },
3007 0,
3008 [] (BitArray & ba, Instruction & instr)
3009 {
3010// -----------------------------------------------------------------------------
3011etiss_uint8 rd = 0;
3012static BitArrayRange R_rd_0(11, 7);
3013rd += R_rd_0.read(ba) << 0;
3014etiss_uint8 rs1 = 0;
3015static BitArrayRange R_rs1_0(19, 15);
3016rs1 += R_rs1_0.read(ba) << 0;
3017etiss_uint8 rs2 = 0;
3018static BitArrayRange R_rs2_0(24, 20);
3019rs2 += R_rs2_0.read(ba) << 0;
3020
3021// -----------------------------------------------------------------------------
3022
3023 std::stringstream ss;
3024// -----------------------------------------------------------------------------
3025ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3026// -----------------------------------------------------------------------------
3027 return ss.str();
3028 }
3029);
3030
3031// SLT -------------------------------------------------------------------------
3032static InstructionDefinition slt_rd_rs1_rs2 (
3033 ISA32_RV64IMACFD,
3034 "slt",
3035 (uint32_t) 0x002033,
3036 (uint32_t) 0xfe00707f,
3037 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3038 {
3039
3040// -----------------------------------------------------------------------------
3041
3042// -----------------------------------------------------------------------------
3043
3044// -----------------------------------------------------------------------------
3045// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3046etiss_uint8 rd = 0;
3047static BitArrayRange R_rd_0(11, 7);
3048rd += R_rd_0.read(ba) << 0;
3049etiss_uint8 rs1 = 0;
3050static BitArrayRange R_rs1_0(19, 15);
3051rs1 += R_rs1_0.read(ba) << 0;
3052etiss_uint8 rs2 = 0;
3053static BitArrayRange R_rs2_0(24, 20);
3054rs2 += R_rs2_0.read(ba) << 0;
3055
3056// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3057// -----------------------------------------------------------------------------
3058
3059 {
3060 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3061
3062 cp.code() = std::string("//SLT\n");
3063
3064// -----------------------------------------------------------------------------
3065cp.code() += "etiss_coverage_count(1, 30);\n";
3066{ // block
3067cp.code() += "etiss_coverage_count(1, 1169);\n";
3068cp.code() += "{ // block\n";
3069cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3070cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3071cp.code() += "} // block\n";
3072} // block
3073cp.code() += "etiss_coverage_count(1, 1988);\n";
3074if ((rd % 32ULL) != 0LL) { // conditional
3075cp.code() += "etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";
3076cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0LL);\n";
3077cp.code() += "etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";
3078} // conditional
3079cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3080cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3081// -----------------------------------------------------------------------------
3082 cp.getAffectedRegisters().add("instructionPointer", 32);
3083 }
3084
3085 return true;
3086 },
3087 0,
3088 [] (BitArray & ba, Instruction & instr)
3089 {
3090// -----------------------------------------------------------------------------
3091etiss_uint8 rd = 0;
3092static BitArrayRange R_rd_0(11, 7);
3093rd += R_rd_0.read(ba) << 0;
3094etiss_uint8 rs1 = 0;
3095static BitArrayRange R_rs1_0(19, 15);
3096rs1 += R_rs1_0.read(ba) << 0;
3097etiss_uint8 rs2 = 0;
3098static BitArrayRange R_rs2_0(24, 20);
3099rs2 += R_rs2_0.read(ba) << 0;
3100
3101// -----------------------------------------------------------------------------
3102
3103 std::stringstream ss;
3104// -----------------------------------------------------------------------------
3105ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3106// -----------------------------------------------------------------------------
3107 return ss.str();
3108 }
3109);
3110
3111// SLTU ------------------------------------------------------------------------
3112static InstructionDefinition sltu_rd_rs1_rs2 (
3113 ISA32_RV64IMACFD,
3114 "sltu",
3115 (uint32_t) 0x003033,
3116 (uint32_t) 0xfe00707f,
3117 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3118 {
3119
3120// -----------------------------------------------------------------------------
3121
3122// -----------------------------------------------------------------------------
3123
3124// -----------------------------------------------------------------------------
3125// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3126etiss_uint8 rd = 0;
3127static BitArrayRange R_rd_0(11, 7);
3128rd += R_rd_0.read(ba) << 0;
3129etiss_uint8 rs1 = 0;
3130static BitArrayRange R_rs1_0(19, 15);
3131rs1 += R_rs1_0.read(ba) << 0;
3132etiss_uint8 rs2 = 0;
3133static BitArrayRange R_rs2_0(24, 20);
3134rs2 += R_rs2_0.read(ba) << 0;
3135
3136// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3137// -----------------------------------------------------------------------------
3138
3139 {
3140 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3141
3142 cp.code() = std::string("//SLTU\n");
3143
3144// -----------------------------------------------------------------------------
3145cp.code() += "etiss_coverage_count(1, 31);\n";
3146{ // block
3147cp.code() += "etiss_coverage_count(1, 1169);\n";
3148cp.code() += "{ // block\n";
3149cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3150cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3151cp.code() += "} // block\n";
3152} // block
3153cp.code() += "etiss_coverage_count(1, 2017);\n";
3154if ((rd % 32ULL) != 0LL) { // conditional
3155cp.code() += "etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";
3156cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0LL);\n";
3157cp.code() += "etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";
3158} // conditional
3159cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3160cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3161// -----------------------------------------------------------------------------
3162 cp.getAffectedRegisters().add("instructionPointer", 32);
3163 }
3164
3165 return true;
3166 },
3167 0,
3168 [] (BitArray & ba, Instruction & instr)
3169 {
3170// -----------------------------------------------------------------------------
3171etiss_uint8 rd = 0;
3172static BitArrayRange R_rd_0(11, 7);
3173rd += R_rd_0.read(ba) << 0;
3174etiss_uint8 rs1 = 0;
3175static BitArrayRange R_rs1_0(19, 15);
3176rs1 += R_rs1_0.read(ba) << 0;
3177etiss_uint8 rs2 = 0;
3178static BitArrayRange R_rs2_0(24, 20);
3179rs2 += R_rs2_0.read(ba) << 0;
3180
3181// -----------------------------------------------------------------------------
3182
3183 std::stringstream ss;
3184// -----------------------------------------------------------------------------
3185ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3186// -----------------------------------------------------------------------------
3187 return ss.str();
3188 }
3189);
3190
3191// XOR -------------------------------------------------------------------------
3192static InstructionDefinition xor_rd_rs1_rs2 (
3193 ISA32_RV64IMACFD,
3194 "xor",
3195 (uint32_t) 0x004033,
3196 (uint32_t) 0xfe00707f,
3197 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3198 {
3199
3200// -----------------------------------------------------------------------------
3201
3202// -----------------------------------------------------------------------------
3203
3204// -----------------------------------------------------------------------------
3205// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3206etiss_uint8 rd = 0;
3207static BitArrayRange R_rd_0(11, 7);
3208rd += R_rd_0.read(ba) << 0;
3209etiss_uint8 rs1 = 0;
3210static BitArrayRange R_rs1_0(19, 15);
3211rs1 += R_rs1_0.read(ba) << 0;
3212etiss_uint8 rs2 = 0;
3213static BitArrayRange R_rs2_0(24, 20);
3214rs2 += R_rs2_0.read(ba) << 0;
3215
3216// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3217// -----------------------------------------------------------------------------
3218
3219 {
3220 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3221
3222 cp.code() = std::string("//XOR\n");
3223
3224// -----------------------------------------------------------------------------
3225cp.code() += "etiss_coverage_count(1, 32);\n";
3226{ // block
3227cp.code() += "etiss_coverage_count(1, 1169);\n";
3228cp.code() += "{ // block\n";
3229cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3230cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3231cp.code() += "} // block\n";
3232} // block
3233cp.code() += "etiss_coverage_count(1, 2044);\n";
3234if ((rd % 32ULL) != 0LL) { // conditional
3235cp.code() += "etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";
3236cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3237cp.code() += "etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";
3238} // conditional
3239cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3240cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3241// -----------------------------------------------------------------------------
3242 cp.getAffectedRegisters().add("instructionPointer", 32);
3243 }
3244
3245 return true;
3246 },
3247 0,
3248 [] (BitArray & ba, Instruction & instr)
3249 {
3250// -----------------------------------------------------------------------------
3251etiss_uint8 rd = 0;
3252static BitArrayRange R_rd_0(11, 7);
3253rd += R_rd_0.read(ba) << 0;
3254etiss_uint8 rs1 = 0;
3255static BitArrayRange R_rs1_0(19, 15);
3256rs1 += R_rs1_0.read(ba) << 0;
3257etiss_uint8 rs2 = 0;
3258static BitArrayRange R_rs2_0(24, 20);
3259rs2 += R_rs2_0.read(ba) << 0;
3260
3261// -----------------------------------------------------------------------------
3262
3263 std::stringstream ss;
3264// -----------------------------------------------------------------------------
3265ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3266// -----------------------------------------------------------------------------
3267 return ss.str();
3268 }
3269);
3270
3271// SRL -------------------------------------------------------------------------
3272static InstructionDefinition srl_rd_rs1_rs2 (
3273 ISA32_RV64IMACFD,
3274 "srl",
3275 (uint32_t) 0x005033,
3276 (uint32_t) 0xfe00707f,
3277 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3278 {
3279
3280// -----------------------------------------------------------------------------
3281
3282// -----------------------------------------------------------------------------
3283
3284// -----------------------------------------------------------------------------
3285// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3286etiss_uint8 rd = 0;
3287static BitArrayRange R_rd_0(11, 7);
3288rd += R_rd_0.read(ba) << 0;
3289etiss_uint8 rs1 = 0;
3290static BitArrayRange R_rs1_0(19, 15);
3291rs1 += R_rs1_0.read(ba) << 0;
3292etiss_uint8 rs2 = 0;
3293static BitArrayRange R_rs2_0(24, 20);
3294rs2 += R_rs2_0.read(ba) << 0;
3295
3296// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3297// -----------------------------------------------------------------------------
3298
3299 {
3300 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3301
3302 cp.code() = std::string("//SRL\n");
3303
3304// -----------------------------------------------------------------------------
3305cp.code() += "etiss_coverage_count(1, 33);\n";
3306{ // block
3307cp.code() += "etiss_coverage_count(1, 1169);\n";
3308cp.code() += "{ // block\n";
3309cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3310cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3311cp.code() += "} // block\n";
3312} // block
3313cp.code() += "etiss_coverage_count(1, 2068);\n";
3314if ((rd % 32ULL) != 0LL) { // conditional
3315cp.code() += "etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";
3316cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
3317cp.code() += "etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";
3318} // conditional
3319cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3320cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3321// -----------------------------------------------------------------------------
3322 cp.getAffectedRegisters().add("instructionPointer", 32);
3323 }
3324
3325 return true;
3326 },
3327 0,
3328 [] (BitArray & ba, Instruction & instr)
3329 {
3330// -----------------------------------------------------------------------------
3331etiss_uint8 rd = 0;
3332static BitArrayRange R_rd_0(11, 7);
3333rd += R_rd_0.read(ba) << 0;
3334etiss_uint8 rs1 = 0;
3335static BitArrayRange R_rs1_0(19, 15);
3336rs1 += R_rs1_0.read(ba) << 0;
3337etiss_uint8 rs2 = 0;
3338static BitArrayRange R_rs2_0(24, 20);
3339rs2 += R_rs2_0.read(ba) << 0;
3340
3341// -----------------------------------------------------------------------------
3342
3343 std::stringstream ss;
3344// -----------------------------------------------------------------------------
3345ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3346// -----------------------------------------------------------------------------
3347 return ss.str();
3348 }
3349);
3350
3351// SRA -------------------------------------------------------------------------
3352static InstructionDefinition sra_rd_rs1_rs2 (
3353 ISA32_RV64IMACFD,
3354 "sra",
3355 (uint32_t) 0x40005033,
3356 (uint32_t) 0xfe00707f,
3357 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3358 {
3359
3360// -----------------------------------------------------------------------------
3361
3362// -----------------------------------------------------------------------------
3363
3364// -----------------------------------------------------------------------------
3365// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3366etiss_uint8 rd = 0;
3367static BitArrayRange R_rd_0(11, 7);
3368rd += R_rd_0.read(ba) << 0;
3369etiss_uint8 rs1 = 0;
3370static BitArrayRange R_rs1_0(19, 15);
3371rs1 += R_rs1_0.read(ba) << 0;
3372etiss_uint8 rs2 = 0;
3373static BitArrayRange R_rs2_0(24, 20);
3374rs2 += R_rs2_0.read(ba) << 0;
3375
3376// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3377// -----------------------------------------------------------------------------
3378
3379 {
3380 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3381
3382 cp.code() = std::string("//SRA\n");
3383
3384// -----------------------------------------------------------------------------
3385cp.code() += "etiss_coverage_count(1, 34);\n";
3386{ // block
3387cp.code() += "etiss_coverage_count(1, 1169);\n";
3388cp.code() += "{ // block\n";
3389cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3390cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3391cp.code() += "} // block\n";
3392} // block
3393cp.code() += "etiss_coverage_count(1, 2098);\n";
3394if ((rd % 32ULL) != 0LL) { // conditional
3395cp.code() += "etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";
3396cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
3397cp.code() += "etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";
3398} // conditional
3399cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3400cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3401// -----------------------------------------------------------------------------
3402 cp.getAffectedRegisters().add("instructionPointer", 32);
3403 }
3404
3405 return true;
3406 },
3407 0,
3408 [] (BitArray & ba, Instruction & instr)
3409 {
3410// -----------------------------------------------------------------------------
3411etiss_uint8 rd = 0;
3412static BitArrayRange R_rd_0(11, 7);
3413rd += R_rd_0.read(ba) << 0;
3414etiss_uint8 rs1 = 0;
3415static BitArrayRange R_rs1_0(19, 15);
3416rs1 += R_rs1_0.read(ba) << 0;
3417etiss_uint8 rs2 = 0;
3418static BitArrayRange R_rs2_0(24, 20);
3419rs2 += R_rs2_0.read(ba) << 0;
3420
3421// -----------------------------------------------------------------------------
3422
3423 std::stringstream ss;
3424// -----------------------------------------------------------------------------
3425ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3426// -----------------------------------------------------------------------------
3427 return ss.str();
3428 }
3429);
3430
3431// OR --------------------------------------------------------------------------
3432static InstructionDefinition or_rd_rs1_rs2 (
3433 ISA32_RV64IMACFD,
3434 "or",
3435 (uint32_t) 0x006033,
3436 (uint32_t) 0xfe00707f,
3437 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3438 {
3439
3440// -----------------------------------------------------------------------------
3441
3442// -----------------------------------------------------------------------------
3443
3444// -----------------------------------------------------------------------------
3445// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3446etiss_uint8 rd = 0;
3447static BitArrayRange R_rd_0(11, 7);
3448rd += R_rd_0.read(ba) << 0;
3449etiss_uint8 rs1 = 0;
3450static BitArrayRange R_rs1_0(19, 15);
3451rs1 += R_rs1_0.read(ba) << 0;
3452etiss_uint8 rs2 = 0;
3453static BitArrayRange R_rs2_0(24, 20);
3454rs2 += R_rs2_0.read(ba) << 0;
3455
3456// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3457// -----------------------------------------------------------------------------
3458
3459 {
3460 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3461
3462 cp.code() = std::string("//OR\n");
3463
3464// -----------------------------------------------------------------------------
3465cp.code() += "etiss_coverage_count(1, 35);\n";
3466{ // block
3467cp.code() += "etiss_coverage_count(1, 1169);\n";
3468cp.code() += "{ // block\n";
3469cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3470cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3471cp.code() += "} // block\n";
3472} // block
3473cp.code() += "etiss_coverage_count(1, 2129);\n";
3474if ((rd % 32ULL) != 0LL) { // conditional
3475cp.code() += "etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";
3476cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3477cp.code() += "etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";
3478} // conditional
3479cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3480cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3481// -----------------------------------------------------------------------------
3482 cp.getAffectedRegisters().add("instructionPointer", 32);
3483 }
3484
3485 return true;
3486 },
3487 0,
3488 [] (BitArray & ba, Instruction & instr)
3489 {
3490// -----------------------------------------------------------------------------
3491etiss_uint8 rd = 0;
3492static BitArrayRange R_rd_0(11, 7);
3493rd += R_rd_0.read(ba) << 0;
3494etiss_uint8 rs1 = 0;
3495static BitArrayRange R_rs1_0(19, 15);
3496rs1 += R_rs1_0.read(ba) << 0;
3497etiss_uint8 rs2 = 0;
3498static BitArrayRange R_rs2_0(24, 20);
3499rs2 += R_rs2_0.read(ba) << 0;
3500
3501// -----------------------------------------------------------------------------
3502
3503 std::stringstream ss;
3504// -----------------------------------------------------------------------------
3505ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3506// -----------------------------------------------------------------------------
3507 return ss.str();
3508 }
3509);
3510
3511// AND -------------------------------------------------------------------------
3512static InstructionDefinition and_rd_rs1_rs2 (
3513 ISA32_RV64IMACFD,
3514 "and",
3515 (uint32_t) 0x007033,
3516 (uint32_t) 0xfe00707f,
3517 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3518 {
3519
3520// -----------------------------------------------------------------------------
3521
3522// -----------------------------------------------------------------------------
3523
3524// -----------------------------------------------------------------------------
3525// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3526etiss_uint8 rd = 0;
3527static BitArrayRange R_rd_0(11, 7);
3528rd += R_rd_0.read(ba) << 0;
3529etiss_uint8 rs1 = 0;
3530static BitArrayRange R_rs1_0(19, 15);
3531rs1 += R_rs1_0.read(ba) << 0;
3532etiss_uint8 rs2 = 0;
3533static BitArrayRange R_rs2_0(24, 20);
3534rs2 += R_rs2_0.read(ba) << 0;
3535
3536// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3537// -----------------------------------------------------------------------------
3538
3539 {
3540 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3541
3542 cp.code() = std::string("//AND\n");
3543
3544// -----------------------------------------------------------------------------
3545cp.code() += "etiss_coverage_count(1, 36);\n";
3546{ // block
3547cp.code() += "etiss_coverage_count(1, 1169);\n";
3548cp.code() += "{ // block\n";
3549cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3550cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3551cp.code() += "} // block\n";
3552} // block
3553cp.code() += "etiss_coverage_count(1, 2153);\n";
3554if ((rd % 32ULL) != 0LL) { // conditional
3555cp.code() += "etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";
3556cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3557cp.code() += "etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";
3558} // conditional
3559cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3560cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3561// -----------------------------------------------------------------------------
3562 cp.getAffectedRegisters().add("instructionPointer", 32);
3563 }
3564
3565 return true;
3566 },
3567 0,
3568 [] (BitArray & ba, Instruction & instr)
3569 {
3570// -----------------------------------------------------------------------------
3571etiss_uint8 rd = 0;
3572static BitArrayRange R_rd_0(11, 7);
3573rd += R_rd_0.read(ba) << 0;
3574etiss_uint8 rs1 = 0;
3575static BitArrayRange R_rs1_0(19, 15);
3576rs1 += R_rs1_0.read(ba) << 0;
3577etiss_uint8 rs2 = 0;
3578static BitArrayRange R_rs2_0(24, 20);
3579rs2 += R_rs2_0.read(ba) << 0;
3580
3581// -----------------------------------------------------------------------------
3582
3583 std::stringstream ss;
3584// -----------------------------------------------------------------------------
3585ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3586// -----------------------------------------------------------------------------
3587 return ss.str();
3588 }
3589);
3590
3591// FENCE -----------------------------------------------------------------------
3592static InstructionDefinition fence_rd_rs1_succ_pred_fm (
3593 ISA32_RV64IMACFD,
3594 "fence",
3595 (uint32_t) 0x00000f,
3596 (uint32_t) 0x00707f,
3597 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3598 {
3599
3600// -----------------------------------------------------------------------------
3601
3602// -----------------------------------------------------------------------------
3603
3604// -----------------------------------------------------------------------------
3605// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
3606etiss_uint8 rd = 0;
3607static BitArrayRange R_rd_0(11, 7);
3608rd += R_rd_0.read(ba) << 0;
3609etiss_uint8 rs1 = 0;
3610static BitArrayRange R_rs1_0(19, 15);
3611rs1 += R_rs1_0.read(ba) << 0;
3612etiss_uint8 succ = 0;
3613static BitArrayRange R_succ_0(23, 20);
3614succ += R_succ_0.read(ba) << 0;
3615etiss_uint8 pred = 0;
3616static BitArrayRange R_pred_0(27, 24);
3617pred += R_pred_0.read(ba) << 0;
3618etiss_uint8 fm = 0;
3619static BitArrayRange R_fm_0(31, 28);
3620fm += R_fm_0.read(ba) << 0;
3621
3622// NOLINTEND(clang-diagnostic-unused-but-set-variable)
3623// -----------------------------------------------------------------------------
3624
3625 {
3626 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3627
3628 cp.code() = std::string("//FENCE\n");
3629
3630// -----------------------------------------------------------------------------
3631cp.code() += "etiss_coverage_count(1, 37);\n";
3632{ // block
3633cp.code() += "etiss_coverage_count(1, 1169);\n";
3634cp.code() += "{ // block\n";
3635cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3636cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3637cp.code() += "} // block\n";
3638} // block
3639cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
3640cp.code() += "etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";
3641cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3642cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3643// -----------------------------------------------------------------------------
3644 cp.getAffectedRegisters().add("instructionPointer", 32);
3645 }
3646
3647 return true;
3648 },
3649 0,
3650 [] (BitArray & ba, Instruction & instr)
3651 {
3652// -----------------------------------------------------------------------------
3653etiss_uint8 rd = 0;
3654static BitArrayRange R_rd_0(11, 7);
3655rd += R_rd_0.read(ba) << 0;
3656etiss_uint8 rs1 = 0;
3657static BitArrayRange R_rs1_0(19, 15);
3658rs1 += R_rs1_0.read(ba) << 0;
3659etiss_uint8 succ = 0;
3660static BitArrayRange R_succ_0(23, 20);
3661succ += R_succ_0.read(ba) << 0;
3662etiss_uint8 pred = 0;
3663static BitArrayRange R_pred_0(27, 24);
3664pred += R_pred_0.read(ba) << 0;
3665etiss_uint8 fm = 0;
3666static BitArrayRange R_fm_0(31, 28);
3667fm += R_fm_0.read(ba) << 0;
3668
3669// -----------------------------------------------------------------------------
3670
3671 std::stringstream ss;
3672// -----------------------------------------------------------------------------
3673ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
3674// -----------------------------------------------------------------------------
3675 return ss.str();
3676 }
3677);
3678// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
sb_imm_rs1_rs2
static InstructionDefinition sb_imm_rs1_rs2(ISA32_RV64IMACFD, "sb",(uint32_t) 0x000023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="etiss_coverage_count(1, 15);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1656);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sb"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lhu_rd_rs1_imm
static InstructionDefinition lhu_rd_rs1_imm(ISA32_RV64IMACFD, "lhu",(uint32_t) 0x005003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="etiss_coverage_count(1, 14);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1634);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";cp.code()+="etiss_coverage_count(1, 1618);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV64IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");cp.code()+="etiss_coverage_count(1, 25);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1868);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RV64IMACFD, "andi",(uint32_t) 0x007013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ANDI\n");cp.code()+="etiss_coverage_count(1, 23);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1824);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "andi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RV64IMACFD, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUB\n");cp.code()+="etiss_coverage_count(1, 28);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1934);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] - *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sub"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lbu_rd_rs1_imm
static InstructionDefinition lbu_rd_rs1_imm(ISA32_RV64IMACFD, "lbu",(uint32_t) 0x004003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="etiss_coverage_count(1, 13);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1600);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";cp.code()+="etiss_coverage_count(1, 1584);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lbu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RV64IMACFD, "ori",(uint32_t) 0x006013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ORI\n");cp.code()+="etiss_coverage_count(1, 22);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1800);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RV64IMACFD, "slt",(uint32_t) 0x002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLT\n");cp.code()+="etiss_coverage_count(1, 30);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1988);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "slt"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bne_imm_rs1_rs2
static InstructionDefinition bne_imm_rs1_rs2(ISA32_RV64IMACFD, "bne",(uint32_t) 0x001063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="etiss_coverage_count(1, 5);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1340);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1312);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] != *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";{ cp.code()+="etiss_coverage_count(1, 1339);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1324);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1327, 1325);\n";{ cp.code()+="etiss_coverage_count(1, 1331);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1330, 1328);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1338);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bne"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RV64IMACFD, "xori",(uint32_t) 0x004013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XORI\n");cp.code()+="etiss_coverage_count(1, 21);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1776);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "xori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RV64IMACFD, "sltiu",(uint32_t) 0x003013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTIU\n");cp.code()+="etiss_coverage_count(1, 20);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1748);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "sltiu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RV64IMACFD, "addi",(uint32_t) 0x000013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDI\n");cp.code()+="etiss_coverage_count(1, 18);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1701);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bltu_imm_rs1_rs2
static InstructionDefinition bltu_imm_rs1_rs2(ISA32_RV64IMACFD, "bltu",(uint32_t) 0x006063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="etiss_coverage_count(1, 8);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1435);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1407);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";{ cp.code()+="etiss_coverage_count(1, 1434);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1419);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1422, 1420);\n";{ cp.code()+="etiss_coverage_count(1, 1426);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1425, 1423);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1433);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bltu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RV64IMACFD, "lui",(uint32_t) 0x000037,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LUI\n");cp.code()+="etiss_coverage_count(1, 0);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1170);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string((etiss_uint64)(((etiss_int32)(imm))))+"ULL;\n";cp.code()+="etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "lui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lb_rd_rs1_imm
static InstructionDefinition lb_rd_rs1_imm(ISA32_RV64IMACFD, "lb",(uint32_t) 0x000003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="etiss_coverage_count(1, 10);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1498);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int8 res = (etiss_int8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";cp.code()+="etiss_coverage_count(1, 1482);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lb"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lw_rd_rs1_imm
static InstructionDefinition lw_rd_rs1_imm(ISA32_RV64IMACFD, "lw",(uint32_t) 0x002003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="etiss_coverage_count(1, 12);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1566);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";cp.code()+="etiss_coverage_count(1, 1550);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bge_imm_rs1_rs2
static InstructionDefinition bge_imm_rs1_rs2(ISA32_RV64IMACFD, "bge",(uint32_t) 0x005063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="etiss_coverage_count(1, 7);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1374);\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";{ cp.code()+="etiss_coverage_count(1, 1405);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1390);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1393, 1391);\n";{ cp.code()+="etiss_coverage_count(1, 1397);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1396, 1394);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1404);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bge"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lh_rd_rs1_imm
static InstructionDefinition lh_rd_rs1_imm(ISA32_RV64IMACFD, "lh",(uint32_t) 0x001003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="etiss_coverage_count(1, 11);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1532);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int16 res = (etiss_int16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";cp.code()+="etiss_coverage_count(1, 1516);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fence_rd_rs1_succ_pred_fm
static InstructionDefinition fence_rd_rs1_succ_pred_fm(ISA32_RV64IMACFD, "fence",(uint32_t) 0x00000f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE\n");cp.code()+="etiss_coverage_count(1, 37);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="((RV64IMACFD*)cpu)->FENCE[0ULL] = "+std::to_string(pred<< 4ULL|succ)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | succ="+std::to_string(succ)+" | pred="+std::to_string(pred)+" | fm="+std::to_string(fm)+"]");return ss.str();})
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RV64IMACFD, "srl",(uint32_t) 0x005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRL\n");cp.code()+="etiss_coverage_count(1, 33);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2068);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srl"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bgeu_imm_rs1_rs2
static InstructionDefinition bgeu_imm_rs1_rs2(ISA32_RV64IMACFD, "bgeu",(uint32_t) 0x007063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="etiss_coverage_count(1, 9);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1464);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1436);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >= *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";{ cp.code()+="etiss_coverage_count(1, 1463);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1448);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1451, 1449);\n";{ cp.code()+="etiss_coverage_count(1, 1455);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1454, 1452);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1462);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bgeu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RV64IMACFD, "jalr",(uint32_t) 0x000067,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="etiss_coverage_count(1, 3);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1282);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL) & -2LL;\n";cp.code()+="etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";cp.code()+="etiss_coverage_count(1, 1251);\n";cp.code()+="if (new_pc % 2ULL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 1254, 1252);\n";{ cp.code()+="etiss_coverage_count(1, 1258);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1257, 1255);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 1281);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1259);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";} cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "jalr"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RV64IMACFD, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRA\n");cp.code()+="etiss_coverage_count(1, 34);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2098);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sra"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RV64IMACFD, "xor",(uint32_t) 0x004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XOR\n");cp.code()+="etiss_coverage_count(1, 32);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2044);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "xor"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV64IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");cp.code()+="etiss_coverage_count(1, 24);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1848);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RV64IMACFD, "jal",(uint32_t) 0x00006f,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="etiss_coverage_count(1, 2);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1236);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1205);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1208, 1206);\n";{ cp.code()+="etiss_coverage_count(1, 1212);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1211, 1209);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1235);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1213);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int32)(((etiss_int32) imm)<<(11)) > >(11)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;std::stringstream ss;ss<< "jal"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sh_imm_rs1_rs2
static InstructionDefinition sh_imm_rs1_rs2(ISA32_RV64IMACFD, "sh",(uint32_t) 0x001023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="etiss_coverage_count(1, 16);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1678);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sh"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RV64IMACFD, "slti",(uint32_t) 0x002013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTI\n");cp.code()+="etiss_coverage_count(1, 19);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1722);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "slti"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
beq_imm_rs1_rs2
static InstructionDefinition beq_imm_rs1_rs2(ISA32_RV64IMACFD, "beq",(uint32_t) 0x000063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="etiss_coverage_count(1, 4);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1311);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1283);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";{ cp.code()+="etiss_coverage_count(1, 1310);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1295);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1298, 1296);\n";{ cp.code()+="etiss_coverage_count(1, 1302);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1301, 1299);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1309);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "beq"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RV64IMACFD, "sltu",(uint32_t) 0x003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTU\n");cp.code()+="etiss_coverage_count(1, 31);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2017);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sltu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sw_imm_rs1_rs2
static InstructionDefinition sw_imm_rs1_rs2(ISA32_RV64IMACFD, "sw",(uint32_t) 0x002023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="etiss_coverage_count(1, 17);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1700);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RV64IMACFD, "or",(uint32_t) 0x006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//OR\n");cp.code()+="etiss_coverage_count(1, 35);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2129);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "or"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RV64IMACFD, "add",(uint32_t) 0x000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADD\n");cp.code()+="etiss_coverage_count(1, 27);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1910);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "add"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RV64IMACFD, "and",(uint32_t) 0x007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AND\n");cp.code()+="etiss_coverage_count(1, 36);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2153);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "and"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RV64IMACFD, "auipc",(uint32_t) 0x000017,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AUIPC\n");cp.code()+="etiss_coverage_count(1, 1);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1188);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+(etiss_int32)(imm))+"LL;\n";cp.code()+="etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "auipc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
blt_imm_rs1_rs2
static InstructionDefinition blt_imm_rs1_rs2(ISA32_RV64IMACFD, "blt",(uint32_t) 0x004063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="etiss_coverage_count(1, 6);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1373);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1341);\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";{ cp.code()+="etiss_coverage_count(1, 1372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1357);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1360, 1358);\n";{ cp.code()+="etiss_coverage_count(1, 1364);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1363, 1361);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1371);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "blt"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RV64IMACFD, "sll",(uint32_t) 0x001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLL\n");cp.code()+="etiss_coverage_count(1, 29);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1958);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sll"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV64IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");cp.code()+="etiss_coverage_count(1, 26);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1888);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:51
etiss_uint64
uint64_t etiss_uint64
Definition types.h:58
etiss_uint32
uint32_t etiss_uint32
Definition types.h:55
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_int32
int32_t etiss_int32
Definition types.h:54
etiss_uint16
uint16_t etiss_uint16
Definition types.h:52
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:364
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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