ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32IInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LUI -------------------------------------------------------------------------
16 static InstructionDefinition lui_rd_imm (
17  ISA32_RV64IMACFD,
18  "lui",
19  (uint32_t) 0x000037,
20  (uint32_t) 0x00007f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint32 imm = 0;
33 static BitArrayRange R_imm_12(31, 12);
34 imm += R_imm_12.read(ba) << 12;
35 
36 // -----------------------------------------------------------------------------
37 
38  {
39  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
40 
41  cp.code() = std::string("//LUI\n");
42 
43 // -----------------------------------------------------------------------------
44 cp.code() += "etiss_coverage_count(1, 0);\n";
45 { // block
46 cp.code() += "etiss_coverage_count(1, 1169);\n";
47 cp.code() += "{ // block\n";
48 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
49 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
50 cp.code() += "} // block\n";
51 } // block
52 cp.code() += "etiss_coverage_count(1, 1170);\n";
53 if ((rd % 32ULL) != 0LL) { // conditional
54 cp.code() += "etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";
55 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n";
56 cp.code() += "etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";
57 } // conditional
58 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
59 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
60 // -----------------------------------------------------------------------------
61  cp.getAffectedRegisters().add("instructionPointer", 32);
62  }
63 
64  return true;
65  },
66  0,
67  [] (BitArray & ba, Instruction & instr)
68  {
69 // -----------------------------------------------------------------------------
70 etiss_uint8 rd = 0;
71 static BitArrayRange R_rd_0(11, 7);
72 rd += R_rd_0.read(ba) << 0;
73 etiss_uint32 imm = 0;
74 static BitArrayRange R_imm_12(31, 12);
75 imm += R_imm_12.read(ba) << 12;
76 
77 // -----------------------------------------------------------------------------
78 
79  std::stringstream ss;
80 // -----------------------------------------------------------------------------
81 ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
82 // -----------------------------------------------------------------------------
83  return ss.str();
84  }
85 );
86 
87 // AUIPC -----------------------------------------------------------------------
88 static InstructionDefinition auipc_rd_imm (
89  ISA32_RV64IMACFD,
90  "auipc",
91  (uint32_t) 0x000017,
92  (uint32_t) 0x00007f,
93  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
94  {
95 
96 // -----------------------------------------------------------------------------
97 
98 // -----------------------------------------------------------------------------
99 
100 // -----------------------------------------------------------------------------
101 etiss_uint8 rd = 0;
102 static BitArrayRange R_rd_0(11, 7);
103 rd += R_rd_0.read(ba) << 0;
104 etiss_uint32 imm = 0;
105 static BitArrayRange R_imm_12(31, 12);
106 imm += R_imm_12.read(ba) << 12;
107 
108 // -----------------------------------------------------------------------------
109 
110  {
111  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
112 
113  cp.code() = std::string("//AUIPC\n");
114 
115 // -----------------------------------------------------------------------------
116 cp.code() += "etiss_coverage_count(1, 1);\n";
117 { // block
118 cp.code() += "etiss_coverage_count(1, 1169);\n";
119 cp.code() += "{ // block\n";
120 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
121 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
122 cp.code() += "} // block\n";
123 } // block
124 cp.code() += "etiss_coverage_count(1, 1188);\n";
125 if ((rd % 32ULL) != 0LL) { // conditional
126 cp.code() += "etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";
127 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
128 cp.code() += "etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";
129 } // conditional
130 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
131 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
132 // -----------------------------------------------------------------------------
133  cp.getAffectedRegisters().add("instructionPointer", 32);
134  }
135 
136  return true;
137  },
138  0,
139  [] (BitArray & ba, Instruction & instr)
140  {
141 // -----------------------------------------------------------------------------
142 etiss_uint8 rd = 0;
143 static BitArrayRange R_rd_0(11, 7);
144 rd += R_rd_0.read(ba) << 0;
145 etiss_uint32 imm = 0;
146 static BitArrayRange R_imm_12(31, 12);
147 imm += R_imm_12.read(ba) << 12;
148 
149 // -----------------------------------------------------------------------------
150 
151  std::stringstream ss;
152 // -----------------------------------------------------------------------------
153 ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
154 // -----------------------------------------------------------------------------
155  return ss.str();
156  }
157 );
158 
159 // JAL -------------------------------------------------------------------------
160 static InstructionDefinition jal_rd_imm (
161  ISA32_RV64IMACFD,
162  "jal",
163  (uint32_t) 0x00006f,
164  (uint32_t) 0x00007f,
165  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
166  {
167 
168 // -----------------------------------------------------------------------------
169 
170 // -----------------------------------------------------------------------------
171 
172 // -----------------------------------------------------------------------------
173 etiss_uint8 rd = 0;
174 static BitArrayRange R_rd_0(11, 7);
175 rd += R_rd_0.read(ba) << 0;
176 etiss_uint32 imm = 0;
177 static BitArrayRange R_imm_12(19, 12);
178 imm += R_imm_12.read(ba) << 12;
179 static BitArrayRange R_imm_11(20, 20);
180 imm += R_imm_11.read(ba) << 11;
181 static BitArrayRange R_imm_1(30, 21);
182 imm += R_imm_1.read(ba) << 1;
183 static BitArrayRange R_imm_20(31, 31);
184 imm += R_imm_20.read(ba) << 20;
185 
186 // -----------------------------------------------------------------------------
187 
188  {
189  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
190 
191  cp.code() = std::string("//JAL\n");
192 
193 // -----------------------------------------------------------------------------
194 cp.code() += "etiss_coverage_count(1, 2);\n";
195 { // block
196 cp.code() += "etiss_coverage_count(1, 1169);\n";
197 cp.code() += "{ // block\n";
198 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
199 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
200 cp.code() += "} // block\n";
201 } // block
202 { // block
203 cp.code() += "etiss_coverage_count(1, 1236);\n";
204 cp.code() += "{ // block\n";
205 cp.code() += "etiss_coverage_count(1, 1205);\n";
206 if (imm % 2ULL) { // conditional
207 cp.code() += "etiss_coverage_count(2, 1208, 1206);\n";
208 { // block
209 cp.code() += "etiss_coverage_count(1, 1212);\n";
210 cp.code() += "{ // block\n";
211 { // procedure
212 cp.code() += "{ // procedure\n";
213 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
214 cp.code() += "etiss_coverage_count(2, 1211, 1209);\n";
215 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
216 cp.code() += "} // procedure\n";
217 } // procedure
218 cp.code() += "} // block\n";
219 } // block
220 } // conditional
221 else { // conditional
222 { // block
223 cp.code() += "etiss_coverage_count(1, 1235);\n";
224 cp.code() += "{ // block\n";
225 cp.code() += "etiss_coverage_count(1, 1213);\n";
226 if ((rd % 32ULL) != 0LL) { // conditional
227 cp.code() += "etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";
228 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
229 cp.code() += "etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";
230 } // conditional
231 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
232 cp.code() += "etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";
233 cp.code() += "} // block\n";
234 } // block
235 } // conditional
236 cp.code() += "} // block\n";
237 } // block
238 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
239 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
240 // -----------------------------------------------------------------------------
241  cp.getAffectedRegisters().add("instructionPointer", 32);
242  }
243  {
244  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
245 
246  cp.code() = std::string("//JAL\n");
247 
248 // -----------------------------------------------------------------------------
249 cp.code() += "return cpu->exception;\n";
250 // -----------------------------------------------------------------------------
251  }
252 
253  return true;
254  },
255  0,
256  [] (BitArray & ba, Instruction & instr)
257  {
258 // -----------------------------------------------------------------------------
259 etiss_uint8 rd = 0;
260 static BitArrayRange R_rd_0(11, 7);
261 rd += R_rd_0.read(ba) << 0;
262 etiss_uint32 imm = 0;
263 static BitArrayRange R_imm_12(19, 12);
264 imm += R_imm_12.read(ba) << 12;
265 static BitArrayRange R_imm_11(20, 20);
266 imm += R_imm_11.read(ba) << 11;
267 static BitArrayRange R_imm_1(30, 21);
268 imm += R_imm_1.read(ba) << 1;
269 static BitArrayRange R_imm_20(31, 31);
270 imm += R_imm_20.read(ba) << 20;
271 
272 // -----------------------------------------------------------------------------
273 
274  std::stringstream ss;
275 // -----------------------------------------------------------------------------
276 ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
277 // -----------------------------------------------------------------------------
278  return ss.str();
279  }
280 );
281 
282 // JALR ------------------------------------------------------------------------
283 static InstructionDefinition jalr_rd_rs1_imm (
284  ISA32_RV64IMACFD,
285  "jalr",
286  (uint32_t) 0x000067,
287  (uint32_t) 0x00707f,
288  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
289  {
290 
291 // -----------------------------------------------------------------------------
292 
293 // -----------------------------------------------------------------------------
294 
295 // -----------------------------------------------------------------------------
296 etiss_uint8 rd = 0;
297 static BitArrayRange R_rd_0(11, 7);
298 rd += R_rd_0.read(ba) << 0;
299 etiss_uint8 rs1 = 0;
300 static BitArrayRange R_rs1_0(19, 15);
301 rs1 += R_rs1_0.read(ba) << 0;
302 etiss_uint16 imm = 0;
303 static BitArrayRange R_imm_0(31, 20);
304 imm += R_imm_0.read(ba) << 0;
305 
306 // -----------------------------------------------------------------------------
307 
308  {
309  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
310 
311  cp.code() = std::string("//JALR\n");
312 
313 // -----------------------------------------------------------------------------
314 cp.code() += "etiss_coverage_count(1, 3);\n";
315 { // block
316 cp.code() += "etiss_coverage_count(1, 1169);\n";
317 cp.code() += "{ // block\n";
318 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
319 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
320 cp.code() += "} // block\n";
321 } // block
322 { // block
323 cp.code() += "etiss_coverage_count(1, 1282);\n";
324 cp.code() += "{ // block\n";
325 cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
326 cp.code() += "etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";
327 cp.code() += "etiss_coverage_count(1, 1251);\n";
328 cp.code() += "if (new_pc % 2ULL) { // conditional\n";
329 cp.code() += "etiss_coverage_count(2, 1254, 1252);\n";
330 { // block
331 cp.code() += "etiss_coverage_count(1, 1258);\n";
332 cp.code() += "{ // block\n";
333 { // procedure
334 cp.code() += "{ // procedure\n";
335 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
336 cp.code() += "etiss_coverage_count(2, 1257, 1255);\n";
337 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
338 cp.code() += "} // procedure\n";
339 } // procedure
340 cp.code() += "} // block\n";
341 } // block
342 cp.code() += "} // conditional\n";
343 cp.code() += "else { // conditional\n";
344 { // block
345 cp.code() += "etiss_coverage_count(1, 1281);\n";
346 cp.code() += "{ // block\n";
347 cp.code() += "etiss_coverage_count(1, 1259);\n";
348 if ((rd % 32ULL) != 0LL) { // conditional
349 cp.code() += "etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";
350 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
351 cp.code() += "etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";
352 } // conditional
353 cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
354 cp.code() += "etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";
355 cp.code() += "} // block\n";
356 } // block
357 cp.code() += "} // conditional\n";
358 cp.code() += "} // block\n";
359 } // block
360 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
361 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
362 // -----------------------------------------------------------------------------
363  cp.getAffectedRegisters().add("instructionPointer", 32);
364  }
365  {
366  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
367 
368  cp.code() = std::string("//JALR\n");
369 
370 // -----------------------------------------------------------------------------
371 cp.code() += "return cpu->exception;\n";
372 // -----------------------------------------------------------------------------
373  }
374 
375  return true;
376  },
377  0,
378  [] (BitArray & ba, Instruction & instr)
379  {
380 // -----------------------------------------------------------------------------
381 etiss_uint8 rd = 0;
382 static BitArrayRange R_rd_0(11, 7);
383 rd += R_rd_0.read(ba) << 0;
384 etiss_uint8 rs1 = 0;
385 static BitArrayRange R_rs1_0(19, 15);
386 rs1 += R_rs1_0.read(ba) << 0;
387 etiss_uint16 imm = 0;
388 static BitArrayRange R_imm_0(31, 20);
389 imm += R_imm_0.read(ba) << 0;
390 
391 // -----------------------------------------------------------------------------
392 
393  std::stringstream ss;
394 // -----------------------------------------------------------------------------
395 ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
396 // -----------------------------------------------------------------------------
397  return ss.str();
398  }
399 );
400 
401 // BEQ -------------------------------------------------------------------------
402 static InstructionDefinition beq_imm_rs1_rs2 (
403  ISA32_RV64IMACFD,
404  "beq",
405  (uint32_t) 0x000063,
406  (uint32_t) 0x00707f,
407  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
408  {
409 
410 // -----------------------------------------------------------------------------
411 
412 // -----------------------------------------------------------------------------
413 
414 // -----------------------------------------------------------------------------
415 etiss_uint16 imm = 0;
416 static BitArrayRange R_imm_11(7, 7);
417 imm += R_imm_11.read(ba) << 11;
418 static BitArrayRange R_imm_1(11, 8);
419 imm += R_imm_1.read(ba) << 1;
420 etiss_uint8 rs1 = 0;
421 static BitArrayRange R_rs1_0(19, 15);
422 rs1 += R_rs1_0.read(ba) << 0;
423 etiss_uint8 rs2 = 0;
424 static BitArrayRange R_rs2_0(24, 20);
425 rs2 += R_rs2_0.read(ba) << 0;
426 static BitArrayRange R_imm_5(30, 25);
427 imm += R_imm_5.read(ba) << 5;
428 static BitArrayRange R_imm_12(31, 31);
429 imm += R_imm_12.read(ba) << 12;
430 
431 // -----------------------------------------------------------------------------
432 
433  {
434  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
435 
436  cp.code() = std::string("//BEQ\n");
437 
438 // -----------------------------------------------------------------------------
439 cp.code() += "etiss_coverage_count(1, 4);\n";
440 { // block
441 cp.code() += "etiss_coverage_count(1, 1169);\n";
442 cp.code() += "{ // block\n";
443 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
444 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
445 cp.code() += "} // block\n";
446 } // block
447 { // block
448 cp.code() += "etiss_coverage_count(1, 1311);\n";
449 cp.code() += "{ // block\n";
450 cp.code() += "etiss_coverage_count(1, 1283);\n";
451 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
452 cp.code() += "etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";
453 { // block
454 cp.code() += "etiss_coverage_count(1, 1310);\n";
455 cp.code() += "{ // block\n";
456 cp.code() += "etiss_coverage_count(1, 1295);\n";
457 if (imm % 2ULL) { // conditional
458 cp.code() += "etiss_coverage_count(2, 1298, 1296);\n";
459 { // block
460 cp.code() += "etiss_coverage_count(1, 1302);\n";
461 cp.code() += "{ // block\n";
462 { // procedure
463 cp.code() += "{ // procedure\n";
464 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
465 cp.code() += "etiss_coverage_count(2, 1301, 1299);\n";
466 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
467 cp.code() += "} // procedure\n";
468 } // procedure
469 cp.code() += "} // block\n";
470 } // block
471 } // conditional
472 else { // conditional
473 { // block
474 cp.code() += "etiss_coverage_count(1, 1309);\n";
475 cp.code() += "{ // block\n";
476 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
477 cp.code() += "etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";
478 cp.code() += "} // block\n";
479 } // block
480 } // conditional
481 cp.code() += "} // block\n";
482 } // block
483 cp.code() += "} // conditional\n";
484 cp.code() += "} // block\n";
485 } // block
486 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
487 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
488 // -----------------------------------------------------------------------------
489  cp.getAffectedRegisters().add("instructionPointer", 32);
490  }
491  {
492  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
493 
494  cp.code() = std::string("//BEQ\n");
495 
496 // -----------------------------------------------------------------------------
497 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
498 // -----------------------------------------------------------------------------
499  }
500 
501  return true;
502  },
503  0,
504  [] (BitArray & ba, Instruction & instr)
505  {
506 // -----------------------------------------------------------------------------
507 etiss_uint16 imm = 0;
508 static BitArrayRange R_imm_11(7, 7);
509 imm += R_imm_11.read(ba) << 11;
510 static BitArrayRange R_imm_1(11, 8);
511 imm += R_imm_1.read(ba) << 1;
512 etiss_uint8 rs1 = 0;
513 static BitArrayRange R_rs1_0(19, 15);
514 rs1 += R_rs1_0.read(ba) << 0;
515 etiss_uint8 rs2 = 0;
516 static BitArrayRange R_rs2_0(24, 20);
517 rs2 += R_rs2_0.read(ba) << 0;
518 static BitArrayRange R_imm_5(30, 25);
519 imm += R_imm_5.read(ba) << 5;
520 static BitArrayRange R_imm_12(31, 31);
521 imm += R_imm_12.read(ba) << 12;
522 
523 // -----------------------------------------------------------------------------
524 
525  std::stringstream ss;
526 // -----------------------------------------------------------------------------
527 ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
528 // -----------------------------------------------------------------------------
529  return ss.str();
530  }
531 );
532 
533 // BNE -------------------------------------------------------------------------
534 static InstructionDefinition bne_imm_rs1_rs2 (
535  ISA32_RV64IMACFD,
536  "bne",
537  (uint32_t) 0x001063,
538  (uint32_t) 0x00707f,
539  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
540  {
541 
542 // -----------------------------------------------------------------------------
543 
544 // -----------------------------------------------------------------------------
545 
546 // -----------------------------------------------------------------------------
547 etiss_uint16 imm = 0;
548 static BitArrayRange R_imm_11(7, 7);
549 imm += R_imm_11.read(ba) << 11;
550 static BitArrayRange R_imm_1(11, 8);
551 imm += R_imm_1.read(ba) << 1;
552 etiss_uint8 rs1 = 0;
553 static BitArrayRange R_rs1_0(19, 15);
554 rs1 += R_rs1_0.read(ba) << 0;
555 etiss_uint8 rs2 = 0;
556 static BitArrayRange R_rs2_0(24, 20);
557 rs2 += R_rs2_0.read(ba) << 0;
558 static BitArrayRange R_imm_5(30, 25);
559 imm += R_imm_5.read(ba) << 5;
560 static BitArrayRange R_imm_12(31, 31);
561 imm += R_imm_12.read(ba) << 12;
562 
563 // -----------------------------------------------------------------------------
564 
565  {
566  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
567 
568  cp.code() = std::string("//BNE\n");
569 
570 // -----------------------------------------------------------------------------
571 cp.code() += "etiss_coverage_count(1, 5);\n";
572 { // block
573 cp.code() += "etiss_coverage_count(1, 1169);\n";
574 cp.code() += "{ // block\n";
575 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
576 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
577 cp.code() += "} // block\n";
578 } // block
579 { // block
580 cp.code() += "etiss_coverage_count(1, 1340);\n";
581 cp.code() += "{ // block\n";
582 cp.code() += "etiss_coverage_count(1, 1312);\n";
583 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
584 cp.code() += "etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";
585 { // block
586 cp.code() += "etiss_coverage_count(1, 1339);\n";
587 cp.code() += "{ // block\n";
588 cp.code() += "etiss_coverage_count(1, 1324);\n";
589 if (imm % 2ULL) { // conditional
590 cp.code() += "etiss_coverage_count(2, 1327, 1325);\n";
591 { // block
592 cp.code() += "etiss_coverage_count(1, 1331);\n";
593 cp.code() += "{ // block\n";
594 { // procedure
595 cp.code() += "{ // procedure\n";
596 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
597 cp.code() += "etiss_coverage_count(2, 1330, 1328);\n";
598 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
599 cp.code() += "} // procedure\n";
600 } // procedure
601 cp.code() += "} // block\n";
602 } // block
603 } // conditional
604 else { // conditional
605 { // block
606 cp.code() += "etiss_coverage_count(1, 1338);\n";
607 cp.code() += "{ // block\n";
608 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
609 cp.code() += "etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";
610 cp.code() += "} // block\n";
611 } // block
612 } // conditional
613 cp.code() += "} // block\n";
614 } // block
615 cp.code() += "} // conditional\n";
616 cp.code() += "} // block\n";
617 } // block
618 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
619 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
620 // -----------------------------------------------------------------------------
621  cp.getAffectedRegisters().add("instructionPointer", 32);
622  }
623  {
624  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
625 
626  cp.code() = std::string("//BNE\n");
627 
628 // -----------------------------------------------------------------------------
629 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
630 // -----------------------------------------------------------------------------
631  }
632 
633  return true;
634  },
635  0,
636  [] (BitArray & ba, Instruction & instr)
637  {
638 // -----------------------------------------------------------------------------
639 etiss_uint16 imm = 0;
640 static BitArrayRange R_imm_11(7, 7);
641 imm += R_imm_11.read(ba) << 11;
642 static BitArrayRange R_imm_1(11, 8);
643 imm += R_imm_1.read(ba) << 1;
644 etiss_uint8 rs1 = 0;
645 static BitArrayRange R_rs1_0(19, 15);
646 rs1 += R_rs1_0.read(ba) << 0;
647 etiss_uint8 rs2 = 0;
648 static BitArrayRange R_rs2_0(24, 20);
649 rs2 += R_rs2_0.read(ba) << 0;
650 static BitArrayRange R_imm_5(30, 25);
651 imm += R_imm_5.read(ba) << 5;
652 static BitArrayRange R_imm_12(31, 31);
653 imm += R_imm_12.read(ba) << 12;
654 
655 // -----------------------------------------------------------------------------
656 
657  std::stringstream ss;
658 // -----------------------------------------------------------------------------
659 ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
660 // -----------------------------------------------------------------------------
661  return ss.str();
662  }
663 );
664 
665 // BLT -------------------------------------------------------------------------
666 static InstructionDefinition blt_imm_rs1_rs2 (
667  ISA32_RV64IMACFD,
668  "blt",
669  (uint32_t) 0x004063,
670  (uint32_t) 0x00707f,
671  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
672  {
673 
674 // -----------------------------------------------------------------------------
675 
676 // -----------------------------------------------------------------------------
677 
678 // -----------------------------------------------------------------------------
679 etiss_uint16 imm = 0;
680 static BitArrayRange R_imm_11(7, 7);
681 imm += R_imm_11.read(ba) << 11;
682 static BitArrayRange R_imm_1(11, 8);
683 imm += R_imm_1.read(ba) << 1;
684 etiss_uint8 rs1 = 0;
685 static BitArrayRange R_rs1_0(19, 15);
686 rs1 += R_rs1_0.read(ba) << 0;
687 etiss_uint8 rs2 = 0;
688 static BitArrayRange R_rs2_0(24, 20);
689 rs2 += R_rs2_0.read(ba) << 0;
690 static BitArrayRange R_imm_5(30, 25);
691 imm += R_imm_5.read(ba) << 5;
692 static BitArrayRange R_imm_12(31, 31);
693 imm += R_imm_12.read(ba) << 12;
694 
695 // -----------------------------------------------------------------------------
696 
697  {
698  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
699 
700  cp.code() = std::string("//BLT\n");
701 
702 // -----------------------------------------------------------------------------
703 cp.code() += "etiss_coverage_count(1, 6);\n";
704 { // block
705 cp.code() += "etiss_coverage_count(1, 1169);\n";
706 cp.code() += "{ // block\n";
707 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
708 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
709 cp.code() += "} // block\n";
710 } // block
711 { // block
712 cp.code() += "etiss_coverage_count(1, 1373);\n";
713 cp.code() += "{ // block\n";
714 cp.code() += "etiss_coverage_count(1, 1341);\n";
715 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
716 cp.code() += "etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";
717 { // block
718 cp.code() += "etiss_coverage_count(1, 1372);\n";
719 cp.code() += "{ // block\n";
720 cp.code() += "etiss_coverage_count(1, 1357);\n";
721 if (imm % 2ULL) { // conditional
722 cp.code() += "etiss_coverage_count(2, 1360, 1358);\n";
723 { // block
724 cp.code() += "etiss_coverage_count(1, 1364);\n";
725 cp.code() += "{ // block\n";
726 { // procedure
727 cp.code() += "{ // procedure\n";
728 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
729 cp.code() += "etiss_coverage_count(2, 1363, 1361);\n";
730 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
731 cp.code() += "} // procedure\n";
732 } // procedure
733 cp.code() += "} // block\n";
734 } // block
735 } // conditional
736 else { // conditional
737 { // block
738 cp.code() += "etiss_coverage_count(1, 1371);\n";
739 cp.code() += "{ // block\n";
740 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
741 cp.code() += "etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";
742 cp.code() += "} // block\n";
743 } // block
744 } // conditional
745 cp.code() += "} // block\n";
746 } // block
747 cp.code() += "} // conditional\n";
748 cp.code() += "} // block\n";
749 } // block
750 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
751 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
752 // -----------------------------------------------------------------------------
753  cp.getAffectedRegisters().add("instructionPointer", 32);
754  }
755  {
756  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
757 
758  cp.code() = std::string("//BLT\n");
759 
760 // -----------------------------------------------------------------------------
761 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
762 // -----------------------------------------------------------------------------
763  }
764 
765  return true;
766  },
767  0,
768  [] (BitArray & ba, Instruction & instr)
769  {
770 // -----------------------------------------------------------------------------
771 etiss_uint16 imm = 0;
772 static BitArrayRange R_imm_11(7, 7);
773 imm += R_imm_11.read(ba) << 11;
774 static BitArrayRange R_imm_1(11, 8);
775 imm += R_imm_1.read(ba) << 1;
776 etiss_uint8 rs1 = 0;
777 static BitArrayRange R_rs1_0(19, 15);
778 rs1 += R_rs1_0.read(ba) << 0;
779 etiss_uint8 rs2 = 0;
780 static BitArrayRange R_rs2_0(24, 20);
781 rs2 += R_rs2_0.read(ba) << 0;
782 static BitArrayRange R_imm_5(30, 25);
783 imm += R_imm_5.read(ba) << 5;
784 static BitArrayRange R_imm_12(31, 31);
785 imm += R_imm_12.read(ba) << 12;
786 
787 // -----------------------------------------------------------------------------
788 
789  std::stringstream ss;
790 // -----------------------------------------------------------------------------
791 ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
792 // -----------------------------------------------------------------------------
793  return ss.str();
794  }
795 );
796 
797 // BGE -------------------------------------------------------------------------
798 static InstructionDefinition bge_imm_rs1_rs2 (
799  ISA32_RV64IMACFD,
800  "bge",
801  (uint32_t) 0x005063,
802  (uint32_t) 0x00707f,
803  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
804  {
805 
806 // -----------------------------------------------------------------------------
807 
808 // -----------------------------------------------------------------------------
809 
810 // -----------------------------------------------------------------------------
811 etiss_uint16 imm = 0;
812 static BitArrayRange R_imm_11(7, 7);
813 imm += R_imm_11.read(ba) << 11;
814 static BitArrayRange R_imm_1(11, 8);
815 imm += R_imm_1.read(ba) << 1;
816 etiss_uint8 rs1 = 0;
817 static BitArrayRange R_rs1_0(19, 15);
818 rs1 += R_rs1_0.read(ba) << 0;
819 etiss_uint8 rs2 = 0;
820 static BitArrayRange R_rs2_0(24, 20);
821 rs2 += R_rs2_0.read(ba) << 0;
822 static BitArrayRange R_imm_5(30, 25);
823 imm += R_imm_5.read(ba) << 5;
824 static BitArrayRange R_imm_12(31, 31);
825 imm += R_imm_12.read(ba) << 12;
826 
827 // -----------------------------------------------------------------------------
828 
829  {
830  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
831 
832  cp.code() = std::string("//BGE\n");
833 
834 // -----------------------------------------------------------------------------
835 cp.code() += "etiss_coverage_count(1, 7);\n";
836 { // block
837 cp.code() += "etiss_coverage_count(1, 1169);\n";
838 cp.code() += "{ // block\n";
839 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
840 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
841 cp.code() += "} // block\n";
842 } // block
843 { // block
844 cp.code() += "etiss_coverage_count(1, 1406);\n";
845 cp.code() += "{ // block\n";
846 cp.code() += "etiss_coverage_count(1, 1374);\n";
847 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
848 cp.code() += "etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";
849 { // block
850 cp.code() += "etiss_coverage_count(1, 1405);\n";
851 cp.code() += "{ // block\n";
852 cp.code() += "etiss_coverage_count(1, 1390);\n";
853 if (imm % 2ULL) { // conditional
854 cp.code() += "etiss_coverage_count(2, 1393, 1391);\n";
855 { // block
856 cp.code() += "etiss_coverage_count(1, 1397);\n";
857 cp.code() += "{ // block\n";
858 { // procedure
859 cp.code() += "{ // procedure\n";
860 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
861 cp.code() += "etiss_coverage_count(2, 1396, 1394);\n";
862 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
863 cp.code() += "} // procedure\n";
864 } // procedure
865 cp.code() += "} // block\n";
866 } // block
867 } // conditional
868 else { // conditional
869 { // block
870 cp.code() += "etiss_coverage_count(1, 1404);\n";
871 cp.code() += "{ // block\n";
872 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
873 cp.code() += "etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";
874 cp.code() += "} // block\n";
875 } // block
876 } // conditional
877 cp.code() += "} // block\n";
878 } // block
879 cp.code() += "} // conditional\n";
880 cp.code() += "} // block\n";
881 } // block
882 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
883 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
884 // -----------------------------------------------------------------------------
885  cp.getAffectedRegisters().add("instructionPointer", 32);
886  }
887  {
888  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
889 
890  cp.code() = std::string("//BGE\n");
891 
892 // -----------------------------------------------------------------------------
893 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
894 // -----------------------------------------------------------------------------
895  }
896 
897  return true;
898  },
899  0,
900  [] (BitArray & ba, Instruction & instr)
901  {
902 // -----------------------------------------------------------------------------
903 etiss_uint16 imm = 0;
904 static BitArrayRange R_imm_11(7, 7);
905 imm += R_imm_11.read(ba) << 11;
906 static BitArrayRange R_imm_1(11, 8);
907 imm += R_imm_1.read(ba) << 1;
908 etiss_uint8 rs1 = 0;
909 static BitArrayRange R_rs1_0(19, 15);
910 rs1 += R_rs1_0.read(ba) << 0;
911 etiss_uint8 rs2 = 0;
912 static BitArrayRange R_rs2_0(24, 20);
913 rs2 += R_rs2_0.read(ba) << 0;
914 static BitArrayRange R_imm_5(30, 25);
915 imm += R_imm_5.read(ba) << 5;
916 static BitArrayRange R_imm_12(31, 31);
917 imm += R_imm_12.read(ba) << 12;
918 
919 // -----------------------------------------------------------------------------
920 
921  std::stringstream ss;
922 // -----------------------------------------------------------------------------
923 ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
924 // -----------------------------------------------------------------------------
925  return ss.str();
926  }
927 );
928 
929 // BLTU ------------------------------------------------------------------------
930 static InstructionDefinition bltu_imm_rs1_rs2 (
931  ISA32_RV64IMACFD,
932  "bltu",
933  (uint32_t) 0x006063,
934  (uint32_t) 0x00707f,
935  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
936  {
937 
938 // -----------------------------------------------------------------------------
939 
940 // -----------------------------------------------------------------------------
941 
942 // -----------------------------------------------------------------------------
943 etiss_uint16 imm = 0;
944 static BitArrayRange R_imm_11(7, 7);
945 imm += R_imm_11.read(ba) << 11;
946 static BitArrayRange R_imm_1(11, 8);
947 imm += R_imm_1.read(ba) << 1;
948 etiss_uint8 rs1 = 0;
949 static BitArrayRange R_rs1_0(19, 15);
950 rs1 += R_rs1_0.read(ba) << 0;
951 etiss_uint8 rs2 = 0;
952 static BitArrayRange R_rs2_0(24, 20);
953 rs2 += R_rs2_0.read(ba) << 0;
954 static BitArrayRange R_imm_5(30, 25);
955 imm += R_imm_5.read(ba) << 5;
956 static BitArrayRange R_imm_12(31, 31);
957 imm += R_imm_12.read(ba) << 12;
958 
959 // -----------------------------------------------------------------------------
960 
961  {
962  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
963 
964  cp.code() = std::string("//BLTU\n");
965 
966 // -----------------------------------------------------------------------------
967 cp.code() += "etiss_coverage_count(1, 8);\n";
968 { // block
969 cp.code() += "etiss_coverage_count(1, 1169);\n";
970 cp.code() += "{ // block\n";
971 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
972 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
973 cp.code() += "} // block\n";
974 } // block
975 { // block
976 cp.code() += "etiss_coverage_count(1, 1435);\n";
977 cp.code() += "{ // block\n";
978 cp.code() += "etiss_coverage_count(1, 1407);\n";
979 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
980 cp.code() += "etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";
981 { // block
982 cp.code() += "etiss_coverage_count(1, 1434);\n";
983 cp.code() += "{ // block\n";
984 cp.code() += "etiss_coverage_count(1, 1419);\n";
985 if (imm % 2ULL) { // conditional
986 cp.code() += "etiss_coverage_count(2, 1422, 1420);\n";
987 { // block
988 cp.code() += "etiss_coverage_count(1, 1426);\n";
989 cp.code() += "{ // block\n";
990 { // procedure
991 cp.code() += "{ // procedure\n";
992 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
993 cp.code() += "etiss_coverage_count(2, 1425, 1423);\n";
994 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
995 cp.code() += "} // procedure\n";
996 } // procedure
997 cp.code() += "} // block\n";
998 } // block
999 } // conditional
1000 else { // conditional
1001 { // block
1002 cp.code() += "etiss_coverage_count(1, 1433);\n";
1003 cp.code() += "{ // block\n";
1004 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1005 cp.code() += "etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";
1006 cp.code() += "} // block\n";
1007 } // block
1008 } // conditional
1009 cp.code() += "} // block\n";
1010 } // block
1011 cp.code() += "} // conditional\n";
1012 cp.code() += "} // block\n";
1013 } // block
1014 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1015 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1016 // -----------------------------------------------------------------------------
1017  cp.getAffectedRegisters().add("instructionPointer", 32);
1018  }
1019  {
1020  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1021 
1022  cp.code() = std::string("//BLTU\n");
1023 
1024 // -----------------------------------------------------------------------------
1025 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1026 // -----------------------------------------------------------------------------
1027  }
1028 
1029  return true;
1030  },
1031  0,
1032  [] (BitArray & ba, Instruction & instr)
1033  {
1034 // -----------------------------------------------------------------------------
1035 etiss_uint16 imm = 0;
1036 static BitArrayRange R_imm_11(7, 7);
1037 imm += R_imm_11.read(ba) << 11;
1038 static BitArrayRange R_imm_1(11, 8);
1039 imm += R_imm_1.read(ba) << 1;
1040 etiss_uint8 rs1 = 0;
1041 static BitArrayRange R_rs1_0(19, 15);
1042 rs1 += R_rs1_0.read(ba) << 0;
1043 etiss_uint8 rs2 = 0;
1044 static BitArrayRange R_rs2_0(24, 20);
1045 rs2 += R_rs2_0.read(ba) << 0;
1046 static BitArrayRange R_imm_5(30, 25);
1047 imm += R_imm_5.read(ba) << 5;
1048 static BitArrayRange R_imm_12(31, 31);
1049 imm += R_imm_12.read(ba) << 12;
1050 
1051 // -----------------------------------------------------------------------------
1052 
1053  std::stringstream ss;
1054 // -----------------------------------------------------------------------------
1055 ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1056 // -----------------------------------------------------------------------------
1057  return ss.str();
1058  }
1059 );
1060 
1061 // BGEU ------------------------------------------------------------------------
1062 static InstructionDefinition bgeu_imm_rs1_rs2 (
1063  ISA32_RV64IMACFD,
1064  "bgeu",
1065  (uint32_t) 0x007063,
1066  (uint32_t) 0x00707f,
1067  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1068  {
1069 
1070 // -----------------------------------------------------------------------------
1071 
1072 // -----------------------------------------------------------------------------
1073 
1074 // -----------------------------------------------------------------------------
1075 etiss_uint16 imm = 0;
1076 static BitArrayRange R_imm_11(7, 7);
1077 imm += R_imm_11.read(ba) << 11;
1078 static BitArrayRange R_imm_1(11, 8);
1079 imm += R_imm_1.read(ba) << 1;
1080 etiss_uint8 rs1 = 0;
1081 static BitArrayRange R_rs1_0(19, 15);
1082 rs1 += R_rs1_0.read(ba) << 0;
1083 etiss_uint8 rs2 = 0;
1084 static BitArrayRange R_rs2_0(24, 20);
1085 rs2 += R_rs2_0.read(ba) << 0;
1086 static BitArrayRange R_imm_5(30, 25);
1087 imm += R_imm_5.read(ba) << 5;
1088 static BitArrayRange R_imm_12(31, 31);
1089 imm += R_imm_12.read(ba) << 12;
1090 
1091 // -----------------------------------------------------------------------------
1092 
1093  {
1094  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1095 
1096  cp.code() = std::string("//BGEU\n");
1097 
1098 // -----------------------------------------------------------------------------
1099 cp.code() += "etiss_coverage_count(1, 9);\n";
1100 { // block
1101 cp.code() += "etiss_coverage_count(1, 1169);\n";
1102 cp.code() += "{ // block\n";
1103 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1104 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1105 cp.code() += "} // block\n";
1106 } // block
1107 { // block
1108 cp.code() += "etiss_coverage_count(1, 1464);\n";
1109 cp.code() += "{ // block\n";
1110 cp.code() += "etiss_coverage_count(1, 1436);\n";
1111 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
1112 cp.code() += "etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";
1113 { // block
1114 cp.code() += "etiss_coverage_count(1, 1463);\n";
1115 cp.code() += "{ // block\n";
1116 cp.code() += "etiss_coverage_count(1, 1448);\n";
1117 if (imm % 2ULL) { // conditional
1118 cp.code() += "etiss_coverage_count(2, 1451, 1449);\n";
1119 { // block
1120 cp.code() += "etiss_coverage_count(1, 1455);\n";
1121 cp.code() += "{ // block\n";
1122 { // procedure
1123 cp.code() += "{ // procedure\n";
1124 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
1125 cp.code() += "etiss_coverage_count(2, 1454, 1452);\n";
1126 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1127 cp.code() += "} // procedure\n";
1128 } // procedure
1129 cp.code() += "} // block\n";
1130 } // block
1131 } // conditional
1132 else { // conditional
1133 { // block
1134 cp.code() += "etiss_coverage_count(1, 1462);\n";
1135 cp.code() += "{ // block\n";
1136 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1137 cp.code() += "etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";
1138 cp.code() += "} // block\n";
1139 } // block
1140 } // conditional
1141 cp.code() += "} // block\n";
1142 } // block
1143 cp.code() += "} // conditional\n";
1144 cp.code() += "} // block\n";
1145 } // block
1146 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1147 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1148 // -----------------------------------------------------------------------------
1149  cp.getAffectedRegisters().add("instructionPointer", 32);
1150  }
1151  {
1152  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1153 
1154  cp.code() = std::string("//BGEU\n");
1155 
1156 // -----------------------------------------------------------------------------
1157 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1158 // -----------------------------------------------------------------------------
1159  }
1160 
1161  return true;
1162  },
1163  0,
1164  [] (BitArray & ba, Instruction & instr)
1165  {
1166 // -----------------------------------------------------------------------------
1167 etiss_uint16 imm = 0;
1168 static BitArrayRange R_imm_11(7, 7);
1169 imm += R_imm_11.read(ba) << 11;
1170 static BitArrayRange R_imm_1(11, 8);
1171 imm += R_imm_1.read(ba) << 1;
1172 etiss_uint8 rs1 = 0;
1173 static BitArrayRange R_rs1_0(19, 15);
1174 rs1 += R_rs1_0.read(ba) << 0;
1175 etiss_uint8 rs2 = 0;
1176 static BitArrayRange R_rs2_0(24, 20);
1177 rs2 += R_rs2_0.read(ba) << 0;
1178 static BitArrayRange R_imm_5(30, 25);
1179 imm += R_imm_5.read(ba) << 5;
1180 static BitArrayRange R_imm_12(31, 31);
1181 imm += R_imm_12.read(ba) << 12;
1182 
1183 // -----------------------------------------------------------------------------
1184 
1185  std::stringstream ss;
1186 // -----------------------------------------------------------------------------
1187 ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1188 // -----------------------------------------------------------------------------
1189  return ss.str();
1190  }
1191 );
1192 
1193 // LB --------------------------------------------------------------------------
1194 static InstructionDefinition lb_rd_rs1_imm (
1195  ISA32_RV64IMACFD,
1196  "lb",
1197  (uint32_t) 0x000003,
1198  (uint32_t) 0x00707f,
1199  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1200  {
1201 
1202 // -----------------------------------------------------------------------------
1203 
1204 // -----------------------------------------------------------------------------
1205 
1206 // -----------------------------------------------------------------------------
1207 etiss_uint8 rd = 0;
1208 static BitArrayRange R_rd_0(11, 7);
1209 rd += R_rd_0.read(ba) << 0;
1210 etiss_uint8 rs1 = 0;
1211 static BitArrayRange R_rs1_0(19, 15);
1212 rs1 += R_rs1_0.read(ba) << 0;
1213 etiss_uint16 imm = 0;
1214 static BitArrayRange R_imm_0(31, 20);
1215 imm += R_imm_0.read(ba) << 0;
1216 
1217 // -----------------------------------------------------------------------------
1218 
1219  {
1220  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1221 
1222  cp.code() = std::string("//LB\n");
1223 
1224 // -----------------------------------------------------------------------------
1225 cp.code() += "etiss_coverage_count(1, 10);\n";
1226 { // block
1227 cp.code() += "etiss_coverage_count(1, 1169);\n";
1228 cp.code() += "{ // block\n";
1229 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1230 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1231 cp.code() += "} // block\n";
1232 } // block
1233 { // block
1234 cp.code() += "etiss_coverage_count(1, 1498);\n";
1235 cp.code() += "{ // block\n";
1236 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1237 cp.code() += "etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";
1238 cp.code() += "etiss_uint8 mem_val_0;\n";
1239 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1240 cp.code() += "if (cpu->exception) { // conditional\n";
1241 { // procedure
1242 cp.code() += "{ // procedure\n";
1243 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1244 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1245 cp.code() += "} // procedure\n";
1246 } // procedure
1247 cp.code() += "} // conditional\n";
1248 cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
1249 cp.code() += "etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";
1250 cp.code() += "etiss_coverage_count(1, 1482);\n";
1251 if ((rd % 32ULL) != 0LL) { // conditional
1252 cp.code() += "etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";
1253 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1254 cp.code() += "etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";
1255 } // conditional
1256 cp.code() += "} // block\n";
1257 } // block
1258 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1259 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1260 // -----------------------------------------------------------------------------
1261  cp.getAffectedRegisters().add("instructionPointer", 32);
1262  }
1263  {
1264  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1265 
1266  cp.code() = std::string("//LB\n");
1267 
1268 // -----------------------------------------------------------------------------
1269 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1270 // -----------------------------------------------------------------------------
1271  }
1272 
1273  return true;
1274  },
1275  0,
1276  [] (BitArray & ba, Instruction & instr)
1277  {
1278 // -----------------------------------------------------------------------------
1279 etiss_uint8 rd = 0;
1280 static BitArrayRange R_rd_0(11, 7);
1281 rd += R_rd_0.read(ba) << 0;
1282 etiss_uint8 rs1 = 0;
1283 static BitArrayRange R_rs1_0(19, 15);
1284 rs1 += R_rs1_0.read(ba) << 0;
1285 etiss_uint16 imm = 0;
1286 static BitArrayRange R_imm_0(31, 20);
1287 imm += R_imm_0.read(ba) << 0;
1288 
1289 // -----------------------------------------------------------------------------
1290 
1291  std::stringstream ss;
1292 // -----------------------------------------------------------------------------
1293 ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1294 // -----------------------------------------------------------------------------
1295  return ss.str();
1296  }
1297 );
1298 
1299 // LH --------------------------------------------------------------------------
1300 static InstructionDefinition lh_rd_rs1_imm (
1301  ISA32_RV64IMACFD,
1302  "lh",
1303  (uint32_t) 0x001003,
1304  (uint32_t) 0x00707f,
1305  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1306  {
1307 
1308 // -----------------------------------------------------------------------------
1309 
1310 // -----------------------------------------------------------------------------
1311 
1312 // -----------------------------------------------------------------------------
1313 etiss_uint8 rd = 0;
1314 static BitArrayRange R_rd_0(11, 7);
1315 rd += R_rd_0.read(ba) << 0;
1316 etiss_uint8 rs1 = 0;
1317 static BitArrayRange R_rs1_0(19, 15);
1318 rs1 += R_rs1_0.read(ba) << 0;
1319 etiss_uint16 imm = 0;
1320 static BitArrayRange R_imm_0(31, 20);
1321 imm += R_imm_0.read(ba) << 0;
1322 
1323 // -----------------------------------------------------------------------------
1324 
1325  {
1326  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1327 
1328  cp.code() = std::string("//LH\n");
1329 
1330 // -----------------------------------------------------------------------------
1331 cp.code() += "etiss_coverage_count(1, 11);\n";
1332 { // block
1333 cp.code() += "etiss_coverage_count(1, 1169);\n";
1334 cp.code() += "{ // block\n";
1335 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1336 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1337 cp.code() += "} // block\n";
1338 } // block
1339 { // block
1340 cp.code() += "etiss_coverage_count(1, 1532);\n";
1341 cp.code() += "{ // block\n";
1342 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1343 cp.code() += "etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";
1344 cp.code() += "etiss_uint16 mem_val_0;\n";
1345 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1346 cp.code() += "if (cpu->exception) { // conditional\n";
1347 { // procedure
1348 cp.code() += "{ // procedure\n";
1349 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1350 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1351 cp.code() += "} // procedure\n";
1352 } // procedure
1353 cp.code() += "} // conditional\n";
1354 cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
1355 cp.code() += "etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";
1356 cp.code() += "etiss_coverage_count(1, 1516);\n";
1357 if ((rd % 32ULL) != 0LL) { // conditional
1358 cp.code() += "etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";
1359 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1360 cp.code() += "etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";
1361 } // conditional
1362 cp.code() += "} // block\n";
1363 } // block
1364 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1365 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1366 // -----------------------------------------------------------------------------
1367  cp.getAffectedRegisters().add("instructionPointer", 32);
1368  }
1369  {
1370  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1371 
1372  cp.code() = std::string("//LH\n");
1373 
1374 // -----------------------------------------------------------------------------
1375 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1376 // -----------------------------------------------------------------------------
1377  }
1378 
1379  return true;
1380  },
1381  0,
1382  [] (BitArray & ba, Instruction & instr)
1383  {
1384 // -----------------------------------------------------------------------------
1385 etiss_uint8 rd = 0;
1386 static BitArrayRange R_rd_0(11, 7);
1387 rd += R_rd_0.read(ba) << 0;
1388 etiss_uint8 rs1 = 0;
1389 static BitArrayRange R_rs1_0(19, 15);
1390 rs1 += R_rs1_0.read(ba) << 0;
1391 etiss_uint16 imm = 0;
1392 static BitArrayRange R_imm_0(31, 20);
1393 imm += R_imm_0.read(ba) << 0;
1394 
1395 // -----------------------------------------------------------------------------
1396 
1397  std::stringstream ss;
1398 // -----------------------------------------------------------------------------
1399 ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1400 // -----------------------------------------------------------------------------
1401  return ss.str();
1402  }
1403 );
1404 
1405 // LW --------------------------------------------------------------------------
1406 static InstructionDefinition lw_rd_rs1_imm (
1407  ISA32_RV64IMACFD,
1408  "lw",
1409  (uint32_t) 0x002003,
1410  (uint32_t) 0x00707f,
1411  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1412  {
1413 
1414 // -----------------------------------------------------------------------------
1415 
1416 // -----------------------------------------------------------------------------
1417 
1418 // -----------------------------------------------------------------------------
1419 etiss_uint8 rd = 0;
1420 static BitArrayRange R_rd_0(11, 7);
1421 rd += R_rd_0.read(ba) << 0;
1422 etiss_uint8 rs1 = 0;
1423 static BitArrayRange R_rs1_0(19, 15);
1424 rs1 += R_rs1_0.read(ba) << 0;
1425 etiss_uint16 imm = 0;
1426 static BitArrayRange R_imm_0(31, 20);
1427 imm += R_imm_0.read(ba) << 0;
1428 
1429 // -----------------------------------------------------------------------------
1430 
1431  {
1432  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1433 
1434  cp.code() = std::string("//LW\n");
1435 
1436 // -----------------------------------------------------------------------------
1437 cp.code() += "etiss_coverage_count(1, 12);\n";
1438 { // block
1439 cp.code() += "etiss_coverage_count(1, 1169);\n";
1440 cp.code() += "{ // block\n";
1441 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1442 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1443 cp.code() += "} // block\n";
1444 } // block
1445 { // block
1446 cp.code() += "etiss_coverage_count(1, 1566);\n";
1447 cp.code() += "{ // block\n";
1448 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1449 cp.code() += "etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";
1450 cp.code() += "etiss_uint32 mem_val_0;\n";
1451 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
1452 cp.code() += "if (cpu->exception) { // conditional\n";
1453 { // procedure
1454 cp.code() += "{ // procedure\n";
1455 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1456 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1457 cp.code() += "} // procedure\n";
1458 } // procedure
1459 cp.code() += "} // conditional\n";
1460 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
1461 cp.code() += "etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";
1462 cp.code() += "etiss_coverage_count(1, 1550);\n";
1463 if ((rd % 32ULL) != 0LL) { // conditional
1464 cp.code() += "etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";
1465 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1466 cp.code() += "etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";
1467 } // conditional
1468 cp.code() += "} // block\n";
1469 } // block
1470 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1471 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1472 // -----------------------------------------------------------------------------
1473  cp.getAffectedRegisters().add("instructionPointer", 32);
1474  }
1475  {
1476  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1477 
1478  cp.code() = std::string("//LW\n");
1479 
1480 // -----------------------------------------------------------------------------
1481 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1482 // -----------------------------------------------------------------------------
1483  }
1484 
1485  return true;
1486  },
1487  0,
1488  [] (BitArray & ba, Instruction & instr)
1489  {
1490 // -----------------------------------------------------------------------------
1491 etiss_uint8 rd = 0;
1492 static BitArrayRange R_rd_0(11, 7);
1493 rd += R_rd_0.read(ba) << 0;
1494 etiss_uint8 rs1 = 0;
1495 static BitArrayRange R_rs1_0(19, 15);
1496 rs1 += R_rs1_0.read(ba) << 0;
1497 etiss_uint16 imm = 0;
1498 static BitArrayRange R_imm_0(31, 20);
1499 imm += R_imm_0.read(ba) << 0;
1500 
1501 // -----------------------------------------------------------------------------
1502 
1503  std::stringstream ss;
1504 // -----------------------------------------------------------------------------
1505 ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1506 // -----------------------------------------------------------------------------
1507  return ss.str();
1508  }
1509 );
1510 
1511 // LBU -------------------------------------------------------------------------
1512 static InstructionDefinition lbu_rd_rs1_imm (
1513  ISA32_RV64IMACFD,
1514  "lbu",
1515  (uint32_t) 0x004003,
1516  (uint32_t) 0x00707f,
1517  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1518  {
1519 
1520 // -----------------------------------------------------------------------------
1521 
1522 // -----------------------------------------------------------------------------
1523 
1524 // -----------------------------------------------------------------------------
1525 etiss_uint8 rd = 0;
1526 static BitArrayRange R_rd_0(11, 7);
1527 rd += R_rd_0.read(ba) << 0;
1528 etiss_uint8 rs1 = 0;
1529 static BitArrayRange R_rs1_0(19, 15);
1530 rs1 += R_rs1_0.read(ba) << 0;
1531 etiss_uint16 imm = 0;
1532 static BitArrayRange R_imm_0(31, 20);
1533 imm += R_imm_0.read(ba) << 0;
1534 
1535 // -----------------------------------------------------------------------------
1536 
1537  {
1538  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1539 
1540  cp.code() = std::string("//LBU\n");
1541 
1542 // -----------------------------------------------------------------------------
1543 cp.code() += "etiss_coverage_count(1, 13);\n";
1544 { // block
1545 cp.code() += "etiss_coverage_count(1, 1169);\n";
1546 cp.code() += "{ // block\n";
1547 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1548 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1549 cp.code() += "} // block\n";
1550 } // block
1551 { // block
1552 cp.code() += "etiss_coverage_count(1, 1600);\n";
1553 cp.code() += "{ // block\n";
1554 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1555 cp.code() += "etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";
1556 cp.code() += "etiss_uint8 mem_val_0;\n";
1557 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1558 cp.code() += "if (cpu->exception) { // conditional\n";
1559 { // procedure
1560 cp.code() += "{ // procedure\n";
1561 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1562 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1563 cp.code() += "} // procedure\n";
1564 } // procedure
1565 cp.code() += "} // conditional\n";
1566 cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
1567 cp.code() += "etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";
1568 cp.code() += "etiss_coverage_count(1, 1584);\n";
1569 if ((rd % 32ULL) != 0LL) { // conditional
1570 cp.code() += "etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";
1571 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1572 cp.code() += "etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";
1573 } // conditional
1574 cp.code() += "} // block\n";
1575 } // block
1576 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1577 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1578 // -----------------------------------------------------------------------------
1579  cp.getAffectedRegisters().add("instructionPointer", 32);
1580  }
1581  {
1582  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1583 
1584  cp.code() = std::string("//LBU\n");
1585 
1586 // -----------------------------------------------------------------------------
1587 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1588 // -----------------------------------------------------------------------------
1589  }
1590 
1591  return true;
1592  },
1593  0,
1594  [] (BitArray & ba, Instruction & instr)
1595  {
1596 // -----------------------------------------------------------------------------
1597 etiss_uint8 rd = 0;
1598 static BitArrayRange R_rd_0(11, 7);
1599 rd += R_rd_0.read(ba) << 0;
1600 etiss_uint8 rs1 = 0;
1601 static BitArrayRange R_rs1_0(19, 15);
1602 rs1 += R_rs1_0.read(ba) << 0;
1603 etiss_uint16 imm = 0;
1604 static BitArrayRange R_imm_0(31, 20);
1605 imm += R_imm_0.read(ba) << 0;
1606 
1607 // -----------------------------------------------------------------------------
1608 
1609  std::stringstream ss;
1610 // -----------------------------------------------------------------------------
1611 ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1612 // -----------------------------------------------------------------------------
1613  return ss.str();
1614  }
1615 );
1616 
1617 // LHU -------------------------------------------------------------------------
1618 static InstructionDefinition lhu_rd_rs1_imm (
1619  ISA32_RV64IMACFD,
1620  "lhu",
1621  (uint32_t) 0x005003,
1622  (uint32_t) 0x00707f,
1623  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1624  {
1625 
1626 // -----------------------------------------------------------------------------
1627 
1628 // -----------------------------------------------------------------------------
1629 
1630 // -----------------------------------------------------------------------------
1631 etiss_uint8 rd = 0;
1632 static BitArrayRange R_rd_0(11, 7);
1633 rd += R_rd_0.read(ba) << 0;
1634 etiss_uint8 rs1 = 0;
1635 static BitArrayRange R_rs1_0(19, 15);
1636 rs1 += R_rs1_0.read(ba) << 0;
1637 etiss_uint16 imm = 0;
1638 static BitArrayRange R_imm_0(31, 20);
1639 imm += R_imm_0.read(ba) << 0;
1640 
1641 // -----------------------------------------------------------------------------
1642 
1643  {
1644  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1645 
1646  cp.code() = std::string("//LHU\n");
1647 
1648 // -----------------------------------------------------------------------------
1649 cp.code() += "etiss_coverage_count(1, 14);\n";
1650 { // block
1651 cp.code() += "etiss_coverage_count(1, 1169);\n";
1652 cp.code() += "{ // block\n";
1653 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1654 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1655 cp.code() += "} // block\n";
1656 } // block
1657 { // block
1658 cp.code() += "etiss_coverage_count(1, 1634);\n";
1659 cp.code() += "{ // block\n";
1660 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1661 cp.code() += "etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";
1662 cp.code() += "etiss_uint16 mem_val_0;\n";
1663 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1664 cp.code() += "if (cpu->exception) { // conditional\n";
1665 { // procedure
1666 cp.code() += "{ // procedure\n";
1667 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1668 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1669 cp.code() += "} // procedure\n";
1670 } // procedure
1671 cp.code() += "} // conditional\n";
1672 cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
1673 cp.code() += "etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";
1674 cp.code() += "etiss_coverage_count(1, 1618);\n";
1675 if ((rd % 32ULL) != 0LL) { // conditional
1676 cp.code() += "etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";
1677 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1678 cp.code() += "etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";
1679 } // conditional
1680 cp.code() += "} // block\n";
1681 } // block
1682 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1683 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1684 // -----------------------------------------------------------------------------
1685  cp.getAffectedRegisters().add("instructionPointer", 32);
1686  }
1687  {
1688  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1689 
1690  cp.code() = std::string("//LHU\n");
1691 
1692 // -----------------------------------------------------------------------------
1693 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1694 // -----------------------------------------------------------------------------
1695  }
1696 
1697  return true;
1698  },
1699  0,
1700  [] (BitArray & ba, Instruction & instr)
1701  {
1702 // -----------------------------------------------------------------------------
1703 etiss_uint8 rd = 0;
1704 static BitArrayRange R_rd_0(11, 7);
1705 rd += R_rd_0.read(ba) << 0;
1706 etiss_uint8 rs1 = 0;
1707 static BitArrayRange R_rs1_0(19, 15);
1708 rs1 += R_rs1_0.read(ba) << 0;
1709 etiss_uint16 imm = 0;
1710 static BitArrayRange R_imm_0(31, 20);
1711 imm += R_imm_0.read(ba) << 0;
1712 
1713 // -----------------------------------------------------------------------------
1714 
1715  std::stringstream ss;
1716 // -----------------------------------------------------------------------------
1717 ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1718 // -----------------------------------------------------------------------------
1719  return ss.str();
1720  }
1721 );
1722 
1723 // SB --------------------------------------------------------------------------
1724 static InstructionDefinition sb_imm_rs1_rs2 (
1725  ISA32_RV64IMACFD,
1726  "sb",
1727  (uint32_t) 0x000023,
1728  (uint32_t) 0x00707f,
1729  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1730  {
1731 
1732 // -----------------------------------------------------------------------------
1733 
1734 // -----------------------------------------------------------------------------
1735 
1736 // -----------------------------------------------------------------------------
1737 etiss_uint16 imm = 0;
1738 static BitArrayRange R_imm_0(11, 7);
1739 imm += R_imm_0.read(ba) << 0;
1740 etiss_uint8 rs1 = 0;
1741 static BitArrayRange R_rs1_0(19, 15);
1742 rs1 += R_rs1_0.read(ba) << 0;
1743 etiss_uint8 rs2 = 0;
1744 static BitArrayRange R_rs2_0(24, 20);
1745 rs2 += R_rs2_0.read(ba) << 0;
1746 static BitArrayRange R_imm_5(31, 25);
1747 imm += R_imm_5.read(ba) << 5;
1748 
1749 // -----------------------------------------------------------------------------
1750 
1751  {
1752  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1753 
1754  cp.code() = std::string("//SB\n");
1755 
1756 // -----------------------------------------------------------------------------
1757 cp.code() += "etiss_coverage_count(1, 15);\n";
1758 { // block
1759 cp.code() += "etiss_coverage_count(1, 1169);\n";
1760 cp.code() += "{ // block\n";
1761 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1762 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1763 cp.code() += "} // block\n";
1764 } // block
1765 { // block
1766 cp.code() += "etiss_coverage_count(1, 1656);\n";
1767 cp.code() += "{ // block\n";
1768 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1769 cp.code() += "etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";
1770 cp.code() += "etiss_uint8 mem_val_0;\n";
1771 cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1772 cp.code() += "etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";
1773 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
1774 cp.code() += "if (cpu->exception) { // conditional\n";
1775 { // procedure
1776 cp.code() += "{ // procedure\n";
1777 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1778 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1779 cp.code() += "} // procedure\n";
1780 } // procedure
1781 cp.code() += "} // conditional\n";
1782 cp.code() += "} // block\n";
1783 } // block
1784 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1785 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1786 // -----------------------------------------------------------------------------
1787  cp.getAffectedRegisters().add("instructionPointer", 32);
1788  }
1789  {
1790  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1791 
1792  cp.code() = std::string("//SB\n");
1793 
1794 // -----------------------------------------------------------------------------
1795 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1796 // -----------------------------------------------------------------------------
1797  }
1798 
1799  return true;
1800  },
1801  0,
1802  [] (BitArray & ba, Instruction & instr)
1803  {
1804 // -----------------------------------------------------------------------------
1805 etiss_uint16 imm = 0;
1806 static BitArrayRange R_imm_0(11, 7);
1807 imm += R_imm_0.read(ba) << 0;
1808 etiss_uint8 rs1 = 0;
1809 static BitArrayRange R_rs1_0(19, 15);
1810 rs1 += R_rs1_0.read(ba) << 0;
1811 etiss_uint8 rs2 = 0;
1812 static BitArrayRange R_rs2_0(24, 20);
1813 rs2 += R_rs2_0.read(ba) << 0;
1814 static BitArrayRange R_imm_5(31, 25);
1815 imm += R_imm_5.read(ba) << 5;
1816 
1817 // -----------------------------------------------------------------------------
1818 
1819  std::stringstream ss;
1820 // -----------------------------------------------------------------------------
1821 ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1822 // -----------------------------------------------------------------------------
1823  return ss.str();
1824  }
1825 );
1826 
1827 // SH --------------------------------------------------------------------------
1828 static InstructionDefinition sh_imm_rs1_rs2 (
1829  ISA32_RV64IMACFD,
1830  "sh",
1831  (uint32_t) 0x001023,
1832  (uint32_t) 0x00707f,
1833  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1834  {
1835 
1836 // -----------------------------------------------------------------------------
1837 
1838 // -----------------------------------------------------------------------------
1839 
1840 // -----------------------------------------------------------------------------
1841 etiss_uint16 imm = 0;
1842 static BitArrayRange R_imm_0(11, 7);
1843 imm += R_imm_0.read(ba) << 0;
1844 etiss_uint8 rs1 = 0;
1845 static BitArrayRange R_rs1_0(19, 15);
1846 rs1 += R_rs1_0.read(ba) << 0;
1847 etiss_uint8 rs2 = 0;
1848 static BitArrayRange R_rs2_0(24, 20);
1849 rs2 += R_rs2_0.read(ba) << 0;
1850 static BitArrayRange R_imm_5(31, 25);
1851 imm += R_imm_5.read(ba) << 5;
1852 
1853 // -----------------------------------------------------------------------------
1854 
1855  {
1856  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1857 
1858  cp.code() = std::string("//SH\n");
1859 
1860 // -----------------------------------------------------------------------------
1861 cp.code() += "etiss_coverage_count(1, 16);\n";
1862 { // block
1863 cp.code() += "etiss_coverage_count(1, 1169);\n";
1864 cp.code() += "{ // block\n";
1865 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1866 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1867 cp.code() += "} // block\n";
1868 } // block
1869 { // block
1870 cp.code() += "etiss_coverage_count(1, 1678);\n";
1871 cp.code() += "{ // block\n";
1872 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1873 cp.code() += "etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";
1874 cp.code() += "etiss_uint16 mem_val_0;\n";
1875 cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1876 cp.code() += "etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";
1877 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
1878 cp.code() += "if (cpu->exception) { // conditional\n";
1879 { // procedure
1880 cp.code() += "{ // procedure\n";
1881 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1882 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1883 cp.code() += "} // procedure\n";
1884 } // procedure
1885 cp.code() += "} // conditional\n";
1886 cp.code() += "} // block\n";
1887 } // block
1888 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1889 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1890 // -----------------------------------------------------------------------------
1891  cp.getAffectedRegisters().add("instructionPointer", 32);
1892  }
1893  {
1894  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1895 
1896  cp.code() = std::string("//SH\n");
1897 
1898 // -----------------------------------------------------------------------------
1899 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1900 // -----------------------------------------------------------------------------
1901  }
1902 
1903  return true;
1904  },
1905  0,
1906  [] (BitArray & ba, Instruction & instr)
1907  {
1908 // -----------------------------------------------------------------------------
1909 etiss_uint16 imm = 0;
1910 static BitArrayRange R_imm_0(11, 7);
1911 imm += R_imm_0.read(ba) << 0;
1912 etiss_uint8 rs1 = 0;
1913 static BitArrayRange R_rs1_0(19, 15);
1914 rs1 += R_rs1_0.read(ba) << 0;
1915 etiss_uint8 rs2 = 0;
1916 static BitArrayRange R_rs2_0(24, 20);
1917 rs2 += R_rs2_0.read(ba) << 0;
1918 static BitArrayRange R_imm_5(31, 25);
1919 imm += R_imm_5.read(ba) << 5;
1920 
1921 // -----------------------------------------------------------------------------
1922 
1923  std::stringstream ss;
1924 // -----------------------------------------------------------------------------
1925 ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1926 // -----------------------------------------------------------------------------
1927  return ss.str();
1928  }
1929 );
1930 
1931 // SW --------------------------------------------------------------------------
1932 static InstructionDefinition sw_imm_rs1_rs2 (
1933  ISA32_RV64IMACFD,
1934  "sw",
1935  (uint32_t) 0x002023,
1936  (uint32_t) 0x00707f,
1937  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1938  {
1939 
1940 // -----------------------------------------------------------------------------
1941 
1942 // -----------------------------------------------------------------------------
1943 
1944 // -----------------------------------------------------------------------------
1945 etiss_uint16 imm = 0;
1946 static BitArrayRange R_imm_0(11, 7);
1947 imm += R_imm_0.read(ba) << 0;
1948 etiss_uint8 rs1 = 0;
1949 static BitArrayRange R_rs1_0(19, 15);
1950 rs1 += R_rs1_0.read(ba) << 0;
1951 etiss_uint8 rs2 = 0;
1952 static BitArrayRange R_rs2_0(24, 20);
1953 rs2 += R_rs2_0.read(ba) << 0;
1954 static BitArrayRange R_imm_5(31, 25);
1955 imm += R_imm_5.read(ba) << 5;
1956 
1957 // -----------------------------------------------------------------------------
1958 
1959  {
1960  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1961 
1962  cp.code() = std::string("//SW\n");
1963 
1964 // -----------------------------------------------------------------------------
1965 cp.code() += "etiss_coverage_count(1, 17);\n";
1966 { // block
1967 cp.code() += "etiss_coverage_count(1, 1169);\n";
1968 cp.code() += "{ // block\n";
1969 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1970 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1971 cp.code() += "} // block\n";
1972 } // block
1973 { // block
1974 cp.code() += "etiss_coverage_count(1, 1700);\n";
1975 cp.code() += "{ // block\n";
1976 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1977 cp.code() += "etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";
1978 cp.code() += "etiss_uint32 mem_val_0;\n";
1979 cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1980 cp.code() += "etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";
1981 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
1982 cp.code() += "if (cpu->exception) { // conditional\n";
1983 { // procedure
1984 cp.code() += "{ // procedure\n";
1985 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1986 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1987 cp.code() += "} // procedure\n";
1988 } // procedure
1989 cp.code() += "} // conditional\n";
1990 cp.code() += "} // block\n";
1991 } // block
1992 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1993 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1994 // -----------------------------------------------------------------------------
1995  cp.getAffectedRegisters().add("instructionPointer", 32);
1996  }
1997  {
1998  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1999 
2000  cp.code() = std::string("//SW\n");
2001 
2002 // -----------------------------------------------------------------------------
2003 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2004 // -----------------------------------------------------------------------------
2005  }
2006 
2007  return true;
2008  },
2009  0,
2010  [] (BitArray & ba, Instruction & instr)
2011  {
2012 // -----------------------------------------------------------------------------
2013 etiss_uint16 imm = 0;
2014 static BitArrayRange R_imm_0(11, 7);
2015 imm += R_imm_0.read(ba) << 0;
2016 etiss_uint8 rs1 = 0;
2017 static BitArrayRange R_rs1_0(19, 15);
2018 rs1 += R_rs1_0.read(ba) << 0;
2019 etiss_uint8 rs2 = 0;
2020 static BitArrayRange R_rs2_0(24, 20);
2021 rs2 += R_rs2_0.read(ba) << 0;
2022 static BitArrayRange R_imm_5(31, 25);
2023 imm += R_imm_5.read(ba) << 5;
2024 
2025 // -----------------------------------------------------------------------------
2026 
2027  std::stringstream ss;
2028 // -----------------------------------------------------------------------------
2029 ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2030 // -----------------------------------------------------------------------------
2031  return ss.str();
2032  }
2033 );
2034 
2035 // ADDI ------------------------------------------------------------------------
2036 static InstructionDefinition addi_rd_rs1_imm (
2037  ISA32_RV64IMACFD,
2038  "addi",
2039  (uint32_t) 0x000013,
2040  (uint32_t) 0x00707f,
2041  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2042  {
2043 
2044 // -----------------------------------------------------------------------------
2045 
2046 // -----------------------------------------------------------------------------
2047 
2048 // -----------------------------------------------------------------------------
2049 etiss_uint8 rd = 0;
2050 static BitArrayRange R_rd_0(11, 7);
2051 rd += R_rd_0.read(ba) << 0;
2052 etiss_uint8 rs1 = 0;
2053 static BitArrayRange R_rs1_0(19, 15);
2054 rs1 += R_rs1_0.read(ba) << 0;
2055 etiss_uint16 imm = 0;
2056 static BitArrayRange R_imm_0(31, 20);
2057 imm += R_imm_0.read(ba) << 0;
2058 
2059 // -----------------------------------------------------------------------------
2060 
2061  {
2062  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2063 
2064  cp.code() = std::string("//ADDI\n");
2065 
2066 // -----------------------------------------------------------------------------
2067 cp.code() += "etiss_coverage_count(1, 18);\n";
2068 { // block
2069 cp.code() += "etiss_coverage_count(1, 1169);\n";
2070 cp.code() += "{ // block\n";
2071 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2072 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2073 cp.code() += "} // block\n";
2074 } // block
2075 cp.code() += "etiss_coverage_count(1, 1701);\n";
2076 if ((rd % 32ULL) != 0LL) { // conditional
2077 cp.code() += "etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";
2078 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
2079 cp.code() += "etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";
2080 } // conditional
2081 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2082 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2083 // -----------------------------------------------------------------------------
2084  cp.getAffectedRegisters().add("instructionPointer", 32);
2085  }
2086 
2087  return true;
2088  },
2089  0,
2090  [] (BitArray & ba, Instruction & instr)
2091  {
2092 // -----------------------------------------------------------------------------
2093 etiss_uint8 rd = 0;
2094 static BitArrayRange R_rd_0(11, 7);
2095 rd += R_rd_0.read(ba) << 0;
2096 etiss_uint8 rs1 = 0;
2097 static BitArrayRange R_rs1_0(19, 15);
2098 rs1 += R_rs1_0.read(ba) << 0;
2099 etiss_uint16 imm = 0;
2100 static BitArrayRange R_imm_0(31, 20);
2101 imm += R_imm_0.read(ba) << 0;
2102 
2103 // -----------------------------------------------------------------------------
2104 
2105  std::stringstream ss;
2106 // -----------------------------------------------------------------------------
2107 ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2108 // -----------------------------------------------------------------------------
2109  return ss.str();
2110  }
2111 );
2112 
2113 // SLTI ------------------------------------------------------------------------
2114 static InstructionDefinition slti_rd_rs1_imm (
2115  ISA32_RV64IMACFD,
2116  "slti",
2117  (uint32_t) 0x002013,
2118  (uint32_t) 0x00707f,
2119  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2120  {
2121 
2122 // -----------------------------------------------------------------------------
2123 
2124 // -----------------------------------------------------------------------------
2125 
2126 // -----------------------------------------------------------------------------
2127 etiss_uint8 rd = 0;
2128 static BitArrayRange R_rd_0(11, 7);
2129 rd += R_rd_0.read(ba) << 0;
2130 etiss_uint8 rs1 = 0;
2131 static BitArrayRange R_rs1_0(19, 15);
2132 rs1 += R_rs1_0.read(ba) << 0;
2133 etiss_uint16 imm = 0;
2134 static BitArrayRange R_imm_0(31, 20);
2135 imm += R_imm_0.read(ba) << 0;
2136 
2137 // -----------------------------------------------------------------------------
2138 
2139  {
2140  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2141 
2142  cp.code() = std::string("//SLTI\n");
2143 
2144 // -----------------------------------------------------------------------------
2145 cp.code() += "etiss_coverage_count(1, 19);\n";
2146 { // block
2147 cp.code() += "etiss_coverage_count(1, 1169);\n";
2148 cp.code() += "{ // block\n";
2149 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2150 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2151 cp.code() += "} // block\n";
2152 } // block
2153 cp.code() += "etiss_coverage_count(1, 1722);\n";
2154 if ((rd % 32ULL) != 0LL) { // conditional
2155 cp.code() += "etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";
2156 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0LL);\n";
2157 cp.code() += "etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";
2158 } // conditional
2159 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2160 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2161 // -----------------------------------------------------------------------------
2162  cp.getAffectedRegisters().add("instructionPointer", 32);
2163  }
2164 
2165  return true;
2166  },
2167  0,
2168  [] (BitArray & ba, Instruction & instr)
2169  {
2170 // -----------------------------------------------------------------------------
2171 etiss_uint8 rd = 0;
2172 static BitArrayRange R_rd_0(11, 7);
2173 rd += R_rd_0.read(ba) << 0;
2174 etiss_uint8 rs1 = 0;
2175 static BitArrayRange R_rs1_0(19, 15);
2176 rs1 += R_rs1_0.read(ba) << 0;
2177 etiss_uint16 imm = 0;
2178 static BitArrayRange R_imm_0(31, 20);
2179 imm += R_imm_0.read(ba) << 0;
2180 
2181 // -----------------------------------------------------------------------------
2182 
2183  std::stringstream ss;
2184 // -----------------------------------------------------------------------------
2185 ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2186 // -----------------------------------------------------------------------------
2187  return ss.str();
2188  }
2189 );
2190 
2191 // SLTIU -----------------------------------------------------------------------
2192 static InstructionDefinition sltiu_rd_rs1_imm (
2193  ISA32_RV64IMACFD,
2194  "sltiu",
2195  (uint32_t) 0x003013,
2196  (uint32_t) 0x00707f,
2197  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2198  {
2199 
2200 // -----------------------------------------------------------------------------
2201 
2202 // -----------------------------------------------------------------------------
2203 
2204 // -----------------------------------------------------------------------------
2205 etiss_uint8 rd = 0;
2206 static BitArrayRange R_rd_0(11, 7);
2207 rd += R_rd_0.read(ba) << 0;
2208 etiss_uint8 rs1 = 0;
2209 static BitArrayRange R_rs1_0(19, 15);
2210 rs1 += R_rs1_0.read(ba) << 0;
2211 etiss_uint16 imm = 0;
2212 static BitArrayRange R_imm_0(31, 20);
2213 imm += R_imm_0.read(ba) << 0;
2214 
2215 // -----------------------------------------------------------------------------
2216 
2217  {
2218  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2219 
2220  cp.code() = std::string("//SLTIU\n");
2221 
2222 // -----------------------------------------------------------------------------
2223 cp.code() += "etiss_coverage_count(1, 20);\n";
2224 { // block
2225 cp.code() += "etiss_coverage_count(1, 1169);\n";
2226 cp.code() += "{ // block\n";
2227 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2228 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2229 cp.code() += "} // block\n";
2230 } // block
2231 cp.code() += "etiss_coverage_count(1, 1748);\n";
2232 if ((rd % 32ULL) != 0LL) { // conditional
2233 cp.code() += "etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";
2234 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0LL);\n";
2235 cp.code() += "etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";
2236 } // conditional
2237 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2238 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2239 // -----------------------------------------------------------------------------
2240  cp.getAffectedRegisters().add("instructionPointer", 32);
2241  }
2242 
2243  return true;
2244  },
2245  0,
2246  [] (BitArray & ba, Instruction & instr)
2247  {
2248 // -----------------------------------------------------------------------------
2249 etiss_uint8 rd = 0;
2250 static BitArrayRange R_rd_0(11, 7);
2251 rd += R_rd_0.read(ba) << 0;
2252 etiss_uint8 rs1 = 0;
2253 static BitArrayRange R_rs1_0(19, 15);
2254 rs1 += R_rs1_0.read(ba) << 0;
2255 etiss_uint16 imm = 0;
2256 static BitArrayRange R_imm_0(31, 20);
2257 imm += R_imm_0.read(ba) << 0;
2258 
2259 // -----------------------------------------------------------------------------
2260 
2261  std::stringstream ss;
2262 // -----------------------------------------------------------------------------
2263 ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2264 // -----------------------------------------------------------------------------
2265  return ss.str();
2266  }
2267 );
2268 
2269 // XORI ------------------------------------------------------------------------
2270 static InstructionDefinition xori_rd_rs1_imm (
2271  ISA32_RV64IMACFD,
2272  "xori",
2273  (uint32_t) 0x004013,
2274  (uint32_t) 0x00707f,
2275  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2276  {
2277 
2278 // -----------------------------------------------------------------------------
2279 
2280 // -----------------------------------------------------------------------------
2281 
2282 // -----------------------------------------------------------------------------
2283 etiss_uint8 rd = 0;
2284 static BitArrayRange R_rd_0(11, 7);
2285 rd += R_rd_0.read(ba) << 0;
2286 etiss_uint8 rs1 = 0;
2287 static BitArrayRange R_rs1_0(19, 15);
2288 rs1 += R_rs1_0.read(ba) << 0;
2289 etiss_uint16 imm = 0;
2290 static BitArrayRange R_imm_0(31, 20);
2291 imm += R_imm_0.read(ba) << 0;
2292 
2293 // -----------------------------------------------------------------------------
2294 
2295  {
2296  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2297 
2298  cp.code() = std::string("//XORI\n");
2299 
2300 // -----------------------------------------------------------------------------
2301 cp.code() += "etiss_coverage_count(1, 21);\n";
2302 { // block
2303 cp.code() += "etiss_coverage_count(1, 1169);\n";
2304 cp.code() += "{ // block\n";
2305 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2306 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2307 cp.code() += "} // block\n";
2308 } // block
2309 cp.code() += "etiss_coverage_count(1, 1776);\n";
2310 if ((rd % 32ULL) != 0LL) { // conditional
2311 cp.code() += "etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";
2312 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2313 cp.code() += "etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";
2314 } // conditional
2315 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2316 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2317 // -----------------------------------------------------------------------------
2318  cp.getAffectedRegisters().add("instructionPointer", 32);
2319  }
2320 
2321  return true;
2322  },
2323  0,
2324  [] (BitArray & ba, Instruction & instr)
2325  {
2326 // -----------------------------------------------------------------------------
2327 etiss_uint8 rd = 0;
2328 static BitArrayRange R_rd_0(11, 7);
2329 rd += R_rd_0.read(ba) << 0;
2330 etiss_uint8 rs1 = 0;
2331 static BitArrayRange R_rs1_0(19, 15);
2332 rs1 += R_rs1_0.read(ba) << 0;
2333 etiss_uint16 imm = 0;
2334 static BitArrayRange R_imm_0(31, 20);
2335 imm += R_imm_0.read(ba) << 0;
2336 
2337 // -----------------------------------------------------------------------------
2338 
2339  std::stringstream ss;
2340 // -----------------------------------------------------------------------------
2341 ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2342 // -----------------------------------------------------------------------------
2343  return ss.str();
2344  }
2345 );
2346 
2347 // ORI -------------------------------------------------------------------------
2348 static InstructionDefinition ori_rd_rs1_imm (
2349  ISA32_RV64IMACFD,
2350  "ori",
2351  (uint32_t) 0x006013,
2352  (uint32_t) 0x00707f,
2353  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2354  {
2355 
2356 // -----------------------------------------------------------------------------
2357 
2358 // -----------------------------------------------------------------------------
2359 
2360 // -----------------------------------------------------------------------------
2361 etiss_uint8 rd = 0;
2362 static BitArrayRange R_rd_0(11, 7);
2363 rd += R_rd_0.read(ba) << 0;
2364 etiss_uint8 rs1 = 0;
2365 static BitArrayRange R_rs1_0(19, 15);
2366 rs1 += R_rs1_0.read(ba) << 0;
2367 etiss_uint16 imm = 0;
2368 static BitArrayRange R_imm_0(31, 20);
2369 imm += R_imm_0.read(ba) << 0;
2370 
2371 // -----------------------------------------------------------------------------
2372 
2373  {
2374  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2375 
2376  cp.code() = std::string("//ORI\n");
2377 
2378 // -----------------------------------------------------------------------------
2379 cp.code() += "etiss_coverage_count(1, 22);\n";
2380 { // block
2381 cp.code() += "etiss_coverage_count(1, 1169);\n";
2382 cp.code() += "{ // block\n";
2383 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2384 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2385 cp.code() += "} // block\n";
2386 } // block
2387 cp.code() += "etiss_coverage_count(1, 1800);\n";
2388 if ((rd % 32ULL) != 0LL) { // conditional
2389 cp.code() += "etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";
2390 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2391 cp.code() += "etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";
2392 } // conditional
2393 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2394 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2395 // -----------------------------------------------------------------------------
2396  cp.getAffectedRegisters().add("instructionPointer", 32);
2397  }
2398 
2399  return true;
2400  },
2401  0,
2402  [] (BitArray & ba, Instruction & instr)
2403  {
2404 // -----------------------------------------------------------------------------
2405 etiss_uint8 rd = 0;
2406 static BitArrayRange R_rd_0(11, 7);
2407 rd += R_rd_0.read(ba) << 0;
2408 etiss_uint8 rs1 = 0;
2409 static BitArrayRange R_rs1_0(19, 15);
2410 rs1 += R_rs1_0.read(ba) << 0;
2411 etiss_uint16 imm = 0;
2412 static BitArrayRange R_imm_0(31, 20);
2413 imm += R_imm_0.read(ba) << 0;
2414 
2415 // -----------------------------------------------------------------------------
2416 
2417  std::stringstream ss;
2418 // -----------------------------------------------------------------------------
2419 ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2420 // -----------------------------------------------------------------------------
2421  return ss.str();
2422  }
2423 );
2424 
2425 // ANDI ------------------------------------------------------------------------
2426 static InstructionDefinition andi_rd_rs1_imm (
2427  ISA32_RV64IMACFD,
2428  "andi",
2429  (uint32_t) 0x007013,
2430  (uint32_t) 0x00707f,
2431  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2432  {
2433 
2434 // -----------------------------------------------------------------------------
2435 
2436 // -----------------------------------------------------------------------------
2437 
2438 // -----------------------------------------------------------------------------
2439 etiss_uint8 rd = 0;
2440 static BitArrayRange R_rd_0(11, 7);
2441 rd += R_rd_0.read(ba) << 0;
2442 etiss_uint8 rs1 = 0;
2443 static BitArrayRange R_rs1_0(19, 15);
2444 rs1 += R_rs1_0.read(ba) << 0;
2445 etiss_uint16 imm = 0;
2446 static BitArrayRange R_imm_0(31, 20);
2447 imm += R_imm_0.read(ba) << 0;
2448 
2449 // -----------------------------------------------------------------------------
2450 
2451  {
2452  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2453 
2454  cp.code() = std::string("//ANDI\n");
2455 
2456 // -----------------------------------------------------------------------------
2457 cp.code() += "etiss_coverage_count(1, 23);\n";
2458 { // block
2459 cp.code() += "etiss_coverage_count(1, 1169);\n";
2460 cp.code() += "{ // block\n";
2461 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2462 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2463 cp.code() += "} // block\n";
2464 } // block
2465 cp.code() += "etiss_coverage_count(1, 1824);\n";
2466 if ((rd % 32ULL) != 0LL) { // conditional
2467 cp.code() += "etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";
2468 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2469 cp.code() += "etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";
2470 } // conditional
2471 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2472 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2473 // -----------------------------------------------------------------------------
2474  cp.getAffectedRegisters().add("instructionPointer", 32);
2475  }
2476 
2477  return true;
2478  },
2479  0,
2480  [] (BitArray & ba, Instruction & instr)
2481  {
2482 // -----------------------------------------------------------------------------
2483 etiss_uint8 rd = 0;
2484 static BitArrayRange R_rd_0(11, 7);
2485 rd += R_rd_0.read(ba) << 0;
2486 etiss_uint8 rs1 = 0;
2487 static BitArrayRange R_rs1_0(19, 15);
2488 rs1 += R_rs1_0.read(ba) << 0;
2489 etiss_uint16 imm = 0;
2490 static BitArrayRange R_imm_0(31, 20);
2491 imm += R_imm_0.read(ba) << 0;
2492 
2493 // -----------------------------------------------------------------------------
2494 
2495  std::stringstream ss;
2496 // -----------------------------------------------------------------------------
2497 ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2498 // -----------------------------------------------------------------------------
2499  return ss.str();
2500  }
2501 );
2502 
2503 // SLLI ------------------------------------------------------------------------
2504 static InstructionDefinition slli_rd_rs1_shamt (
2505  ISA32_RV64IMACFD,
2506  "slli",
2507  (uint32_t) 0x001013,
2508  (uint32_t) 0xfe00707f,
2509  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2510  {
2511 
2512 // -----------------------------------------------------------------------------
2513 
2514 // -----------------------------------------------------------------------------
2515 
2516 // -----------------------------------------------------------------------------
2517 etiss_uint8 rd = 0;
2518 static BitArrayRange R_rd_0(11, 7);
2519 rd += R_rd_0.read(ba) << 0;
2520 etiss_uint8 rs1 = 0;
2521 static BitArrayRange R_rs1_0(19, 15);
2522 rs1 += R_rs1_0.read(ba) << 0;
2523 etiss_uint8 shamt = 0;
2524 static BitArrayRange R_shamt_0(24, 20);
2525 shamt += R_shamt_0.read(ba) << 0;
2526 
2527 // -----------------------------------------------------------------------------
2528 
2529  {
2530  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2531 
2532  cp.code() = std::string("//SLLI\n");
2533 
2534 // -----------------------------------------------------------------------------
2535 cp.code() += "etiss_coverage_count(1, 24);\n";
2536 { // block
2537 cp.code() += "etiss_coverage_count(1, 1169);\n";
2538 cp.code() += "{ // block\n";
2539 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2540 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2541 cp.code() += "} // block\n";
2542 } // block
2543 cp.code() += "etiss_coverage_count(1, 1848);\n";
2544 if ((rd % 32ULL) != 0LL) { // conditional
2545 cp.code() += "etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";
2546 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
2547 cp.code() += "etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";
2548 } // conditional
2549 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2550 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2551 // -----------------------------------------------------------------------------
2552  cp.getAffectedRegisters().add("instructionPointer", 32);
2553  }
2554 
2555  return true;
2556  },
2557  0,
2558  [] (BitArray & ba, Instruction & instr)
2559  {
2560 // -----------------------------------------------------------------------------
2561 etiss_uint8 rd = 0;
2562 static BitArrayRange R_rd_0(11, 7);
2563 rd += R_rd_0.read(ba) << 0;
2564 etiss_uint8 rs1 = 0;
2565 static BitArrayRange R_rs1_0(19, 15);
2566 rs1 += R_rs1_0.read(ba) << 0;
2567 etiss_uint8 shamt = 0;
2568 static BitArrayRange R_shamt_0(24, 20);
2569 shamt += R_shamt_0.read(ba) << 0;
2570 
2571 // -----------------------------------------------------------------------------
2572 
2573  std::stringstream ss;
2574 // -----------------------------------------------------------------------------
2575 ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2576 // -----------------------------------------------------------------------------
2577  return ss.str();
2578  }
2579 );
2580 
2581 // SRLI ------------------------------------------------------------------------
2582 static InstructionDefinition srli_rd_rs1_shamt (
2583  ISA32_RV64IMACFD,
2584  "srli",
2585  (uint32_t) 0x005013,
2586  (uint32_t) 0xfe00707f,
2587  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2588  {
2589 
2590 // -----------------------------------------------------------------------------
2591 
2592 // -----------------------------------------------------------------------------
2593 
2594 // -----------------------------------------------------------------------------
2595 etiss_uint8 rd = 0;
2596 static BitArrayRange R_rd_0(11, 7);
2597 rd += R_rd_0.read(ba) << 0;
2598 etiss_uint8 rs1 = 0;
2599 static BitArrayRange R_rs1_0(19, 15);
2600 rs1 += R_rs1_0.read(ba) << 0;
2601 etiss_uint8 shamt = 0;
2602 static BitArrayRange R_shamt_0(24, 20);
2603 shamt += R_shamt_0.read(ba) << 0;
2604 
2605 // -----------------------------------------------------------------------------
2606 
2607  {
2608  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2609 
2610  cp.code() = std::string("//SRLI\n");
2611 
2612 // -----------------------------------------------------------------------------
2613 cp.code() += "etiss_coverage_count(1, 25);\n";
2614 { // block
2615 cp.code() += "etiss_coverage_count(1, 1169);\n";
2616 cp.code() += "{ // block\n";
2617 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2618 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2619 cp.code() += "} // block\n";
2620 } // block
2621 cp.code() += "etiss_coverage_count(1, 1868);\n";
2622 if ((rd % 32ULL) != 0LL) { // conditional
2623 cp.code() += "etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";
2624 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
2625 cp.code() += "etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";
2626 } // conditional
2627 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2628 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2629 // -----------------------------------------------------------------------------
2630  cp.getAffectedRegisters().add("instructionPointer", 32);
2631  }
2632 
2633  return true;
2634  },
2635  0,
2636  [] (BitArray & ba, Instruction & instr)
2637  {
2638 // -----------------------------------------------------------------------------
2639 etiss_uint8 rd = 0;
2640 static BitArrayRange R_rd_0(11, 7);
2641 rd += R_rd_0.read(ba) << 0;
2642 etiss_uint8 rs1 = 0;
2643 static BitArrayRange R_rs1_0(19, 15);
2644 rs1 += R_rs1_0.read(ba) << 0;
2645 etiss_uint8 shamt = 0;
2646 static BitArrayRange R_shamt_0(24, 20);
2647 shamt += R_shamt_0.read(ba) << 0;
2648 
2649 // -----------------------------------------------------------------------------
2650 
2651  std::stringstream ss;
2652 // -----------------------------------------------------------------------------
2653 ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2654 // -----------------------------------------------------------------------------
2655  return ss.str();
2656  }
2657 );
2658 
2659 // SRAI ------------------------------------------------------------------------
2660 static InstructionDefinition srai_rd_rs1_shamt (
2661  ISA32_RV64IMACFD,
2662  "srai",
2663  (uint32_t) 0x40005013,
2664  (uint32_t) 0xfe00707f,
2665  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2666  {
2667 
2668 // -----------------------------------------------------------------------------
2669 
2670 // -----------------------------------------------------------------------------
2671 
2672 // -----------------------------------------------------------------------------
2673 etiss_uint8 rd = 0;
2674 static BitArrayRange R_rd_0(11, 7);
2675 rd += R_rd_0.read(ba) << 0;
2676 etiss_uint8 rs1 = 0;
2677 static BitArrayRange R_rs1_0(19, 15);
2678 rs1 += R_rs1_0.read(ba) << 0;
2679 etiss_uint8 shamt = 0;
2680 static BitArrayRange R_shamt_0(24, 20);
2681 shamt += R_shamt_0.read(ba) << 0;
2682 
2683 // -----------------------------------------------------------------------------
2684 
2685  {
2686  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2687 
2688  cp.code() = std::string("//SRAI\n");
2689 
2690 // -----------------------------------------------------------------------------
2691 cp.code() += "etiss_coverage_count(1, 26);\n";
2692 { // block
2693 cp.code() += "etiss_coverage_count(1, 1169);\n";
2694 cp.code() += "{ // block\n";
2695 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2696 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2697 cp.code() += "} // block\n";
2698 } // block
2699 cp.code() += "etiss_coverage_count(1, 1888);\n";
2700 if ((rd % 32ULL) != 0LL) { // conditional
2701 cp.code() += "etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";
2702 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
2703 cp.code() += "etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";
2704 } // conditional
2705 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2706 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2707 // -----------------------------------------------------------------------------
2708  cp.getAffectedRegisters().add("instructionPointer", 32);
2709  }
2710 
2711  return true;
2712  },
2713  0,
2714  [] (BitArray & ba, Instruction & instr)
2715  {
2716 // -----------------------------------------------------------------------------
2717 etiss_uint8 rd = 0;
2718 static BitArrayRange R_rd_0(11, 7);
2719 rd += R_rd_0.read(ba) << 0;
2720 etiss_uint8 rs1 = 0;
2721 static BitArrayRange R_rs1_0(19, 15);
2722 rs1 += R_rs1_0.read(ba) << 0;
2723 etiss_uint8 shamt = 0;
2724 static BitArrayRange R_shamt_0(24, 20);
2725 shamt += R_shamt_0.read(ba) << 0;
2726 
2727 // -----------------------------------------------------------------------------
2728 
2729  std::stringstream ss;
2730 // -----------------------------------------------------------------------------
2731 ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2732 // -----------------------------------------------------------------------------
2733  return ss.str();
2734  }
2735 );
2736 
2737 // ADD -------------------------------------------------------------------------
2738 static InstructionDefinition add_rd_rs1_rs2 (
2739  ISA32_RV64IMACFD,
2740  "add",
2741  (uint32_t) 0x000033,
2742  (uint32_t) 0xfe00707f,
2743  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2744  {
2745 
2746 // -----------------------------------------------------------------------------
2747 
2748 // -----------------------------------------------------------------------------
2749 
2750 // -----------------------------------------------------------------------------
2751 etiss_uint8 rd = 0;
2752 static BitArrayRange R_rd_0(11, 7);
2753 rd += R_rd_0.read(ba) << 0;
2754 etiss_uint8 rs1 = 0;
2755 static BitArrayRange R_rs1_0(19, 15);
2756 rs1 += R_rs1_0.read(ba) << 0;
2757 etiss_uint8 rs2 = 0;
2758 static BitArrayRange R_rs2_0(24, 20);
2759 rs2 += R_rs2_0.read(ba) << 0;
2760 
2761 // -----------------------------------------------------------------------------
2762 
2763  {
2764  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2765 
2766  cp.code() = std::string("//ADD\n");
2767 
2768 // -----------------------------------------------------------------------------
2769 cp.code() += "etiss_coverage_count(1, 27);\n";
2770 { // block
2771 cp.code() += "etiss_coverage_count(1, 1169);\n";
2772 cp.code() += "{ // block\n";
2773 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2774 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2775 cp.code() += "} // block\n";
2776 } // block
2777 cp.code() += "etiss_coverage_count(1, 1910);\n";
2778 if ((rd % 32ULL) != 0LL) { // conditional
2779 cp.code() += "etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";
2780 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2781 cp.code() += "etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";
2782 } // conditional
2783 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2784 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2785 // -----------------------------------------------------------------------------
2786  cp.getAffectedRegisters().add("instructionPointer", 32);
2787  }
2788 
2789  return true;
2790  },
2791  0,
2792  [] (BitArray & ba, Instruction & instr)
2793  {
2794 // -----------------------------------------------------------------------------
2795 etiss_uint8 rd = 0;
2796 static BitArrayRange R_rd_0(11, 7);
2797 rd += R_rd_0.read(ba) << 0;
2798 etiss_uint8 rs1 = 0;
2799 static BitArrayRange R_rs1_0(19, 15);
2800 rs1 += R_rs1_0.read(ba) << 0;
2801 etiss_uint8 rs2 = 0;
2802 static BitArrayRange R_rs2_0(24, 20);
2803 rs2 += R_rs2_0.read(ba) << 0;
2804 
2805 // -----------------------------------------------------------------------------
2806 
2807  std::stringstream ss;
2808 // -----------------------------------------------------------------------------
2809 ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2810 // -----------------------------------------------------------------------------
2811  return ss.str();
2812  }
2813 );
2814 
2815 // SUB -------------------------------------------------------------------------
2816 static InstructionDefinition sub_rd_rs1_rs2 (
2817  ISA32_RV64IMACFD,
2818  "sub",
2819  (uint32_t) 0x40000033,
2820  (uint32_t) 0xfe00707f,
2821  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2822  {
2823 
2824 // -----------------------------------------------------------------------------
2825 
2826 // -----------------------------------------------------------------------------
2827 
2828 // -----------------------------------------------------------------------------
2829 etiss_uint8 rd = 0;
2830 static BitArrayRange R_rd_0(11, 7);
2831 rd += R_rd_0.read(ba) << 0;
2832 etiss_uint8 rs1 = 0;
2833 static BitArrayRange R_rs1_0(19, 15);
2834 rs1 += R_rs1_0.read(ba) << 0;
2835 etiss_uint8 rs2 = 0;
2836 static BitArrayRange R_rs2_0(24, 20);
2837 rs2 += R_rs2_0.read(ba) << 0;
2838 
2839 // -----------------------------------------------------------------------------
2840 
2841  {
2842  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2843 
2844  cp.code() = std::string("//SUB\n");
2845 
2846 // -----------------------------------------------------------------------------
2847 cp.code() += "etiss_coverage_count(1, 28);\n";
2848 { // block
2849 cp.code() += "etiss_coverage_count(1, 1169);\n";
2850 cp.code() += "{ // block\n";
2851 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2852 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2853 cp.code() += "} // block\n";
2854 } // block
2855 cp.code() += "etiss_coverage_count(1, 1934);\n";
2856 if ((rd % 32ULL) != 0LL) { // conditional
2857 cp.code() += "etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";
2858 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2859 cp.code() += "etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";
2860 } // conditional
2861 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2862 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2863 // -----------------------------------------------------------------------------
2864  cp.getAffectedRegisters().add("instructionPointer", 32);
2865  }
2866 
2867  return true;
2868  },
2869  0,
2870  [] (BitArray & ba, Instruction & instr)
2871  {
2872 // -----------------------------------------------------------------------------
2873 etiss_uint8 rd = 0;
2874 static BitArrayRange R_rd_0(11, 7);
2875 rd += R_rd_0.read(ba) << 0;
2876 etiss_uint8 rs1 = 0;
2877 static BitArrayRange R_rs1_0(19, 15);
2878 rs1 += R_rs1_0.read(ba) << 0;
2879 etiss_uint8 rs2 = 0;
2880 static BitArrayRange R_rs2_0(24, 20);
2881 rs2 += R_rs2_0.read(ba) << 0;
2882 
2883 // -----------------------------------------------------------------------------
2884 
2885  std::stringstream ss;
2886 // -----------------------------------------------------------------------------
2887 ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2888 // -----------------------------------------------------------------------------
2889  return ss.str();
2890  }
2891 );
2892 
2893 // SLL -------------------------------------------------------------------------
2894 static InstructionDefinition sll_rd_rs1_rs2 (
2895  ISA32_RV64IMACFD,
2896  "sll",
2897  (uint32_t) 0x001033,
2898  (uint32_t) 0xfe00707f,
2899  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2900  {
2901 
2902 // -----------------------------------------------------------------------------
2903 
2904 // -----------------------------------------------------------------------------
2905 
2906 // -----------------------------------------------------------------------------
2907 etiss_uint8 rd = 0;
2908 static BitArrayRange R_rd_0(11, 7);
2909 rd += R_rd_0.read(ba) << 0;
2910 etiss_uint8 rs1 = 0;
2911 static BitArrayRange R_rs1_0(19, 15);
2912 rs1 += R_rs1_0.read(ba) << 0;
2913 etiss_uint8 rs2 = 0;
2914 static BitArrayRange R_rs2_0(24, 20);
2915 rs2 += R_rs2_0.read(ba) << 0;
2916 
2917 // -----------------------------------------------------------------------------
2918 
2919  {
2920  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2921 
2922  cp.code() = std::string("//SLL\n");
2923 
2924 // -----------------------------------------------------------------------------
2925 cp.code() += "etiss_coverage_count(1, 29);\n";
2926 { // block
2927 cp.code() += "etiss_coverage_count(1, 1169);\n";
2928 cp.code() += "{ // block\n";
2929 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2930 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2931 cp.code() += "} // block\n";
2932 } // block
2933 cp.code() += "etiss_coverage_count(1, 1958);\n";
2934 if ((rd % 32ULL) != 0LL) { // conditional
2935 cp.code() += "etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";
2936 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
2937 cp.code() += "etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";
2938 } // conditional
2939 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2940 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2941 // -----------------------------------------------------------------------------
2942  cp.getAffectedRegisters().add("instructionPointer", 32);
2943  }
2944 
2945  return true;
2946  },
2947  0,
2948  [] (BitArray & ba, Instruction & instr)
2949  {
2950 // -----------------------------------------------------------------------------
2951 etiss_uint8 rd = 0;
2952 static BitArrayRange R_rd_0(11, 7);
2953 rd += R_rd_0.read(ba) << 0;
2954 etiss_uint8 rs1 = 0;
2955 static BitArrayRange R_rs1_0(19, 15);
2956 rs1 += R_rs1_0.read(ba) << 0;
2957 etiss_uint8 rs2 = 0;
2958 static BitArrayRange R_rs2_0(24, 20);
2959 rs2 += R_rs2_0.read(ba) << 0;
2960 
2961 // -----------------------------------------------------------------------------
2962 
2963  std::stringstream ss;
2964 // -----------------------------------------------------------------------------
2965 ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2966 // -----------------------------------------------------------------------------
2967  return ss.str();
2968  }
2969 );
2970 
2971 // SLT -------------------------------------------------------------------------
2972 static InstructionDefinition slt_rd_rs1_rs2 (
2973  ISA32_RV64IMACFD,
2974  "slt",
2975  (uint32_t) 0x002033,
2976  (uint32_t) 0xfe00707f,
2977  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2978  {
2979 
2980 // -----------------------------------------------------------------------------
2981 
2982 // -----------------------------------------------------------------------------
2983 
2984 // -----------------------------------------------------------------------------
2985 etiss_uint8 rd = 0;
2986 static BitArrayRange R_rd_0(11, 7);
2987 rd += R_rd_0.read(ba) << 0;
2988 etiss_uint8 rs1 = 0;
2989 static BitArrayRange R_rs1_0(19, 15);
2990 rs1 += R_rs1_0.read(ba) << 0;
2991 etiss_uint8 rs2 = 0;
2992 static BitArrayRange R_rs2_0(24, 20);
2993 rs2 += R_rs2_0.read(ba) << 0;
2994 
2995 // -----------------------------------------------------------------------------
2996 
2997  {
2998  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2999 
3000  cp.code() = std::string("//SLT\n");
3001 
3002 // -----------------------------------------------------------------------------
3003 cp.code() += "etiss_coverage_count(1, 30);\n";
3004 { // block
3005 cp.code() += "etiss_coverage_count(1, 1169);\n";
3006 cp.code() += "{ // block\n";
3007 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3008 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3009 cp.code() += "} // block\n";
3010 } // block
3011 cp.code() += "etiss_coverage_count(1, 1988);\n";
3012 if ((rd % 32ULL) != 0LL) { // conditional
3013 cp.code() += "etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";
3014 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0LL);\n";
3015 cp.code() += "etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";
3016 } // conditional
3017 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3018 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3019 // -----------------------------------------------------------------------------
3020  cp.getAffectedRegisters().add("instructionPointer", 32);
3021  }
3022 
3023  return true;
3024  },
3025  0,
3026  [] (BitArray & ba, Instruction & instr)
3027  {
3028 // -----------------------------------------------------------------------------
3029 etiss_uint8 rd = 0;
3030 static BitArrayRange R_rd_0(11, 7);
3031 rd += R_rd_0.read(ba) << 0;
3032 etiss_uint8 rs1 = 0;
3033 static BitArrayRange R_rs1_0(19, 15);
3034 rs1 += R_rs1_0.read(ba) << 0;
3035 etiss_uint8 rs2 = 0;
3036 static BitArrayRange R_rs2_0(24, 20);
3037 rs2 += R_rs2_0.read(ba) << 0;
3038 
3039 // -----------------------------------------------------------------------------
3040 
3041  std::stringstream ss;
3042 // -----------------------------------------------------------------------------
3043 ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3044 // -----------------------------------------------------------------------------
3045  return ss.str();
3046  }
3047 );
3048 
3049 // SLTU ------------------------------------------------------------------------
3050 static InstructionDefinition sltu_rd_rs1_rs2 (
3051  ISA32_RV64IMACFD,
3052  "sltu",
3053  (uint32_t) 0x003033,
3054  (uint32_t) 0xfe00707f,
3055  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3056  {
3057 
3058 // -----------------------------------------------------------------------------
3059 
3060 // -----------------------------------------------------------------------------
3061 
3062 // -----------------------------------------------------------------------------
3063 etiss_uint8 rd = 0;
3064 static BitArrayRange R_rd_0(11, 7);
3065 rd += R_rd_0.read(ba) << 0;
3066 etiss_uint8 rs1 = 0;
3067 static BitArrayRange R_rs1_0(19, 15);
3068 rs1 += R_rs1_0.read(ba) << 0;
3069 etiss_uint8 rs2 = 0;
3070 static BitArrayRange R_rs2_0(24, 20);
3071 rs2 += R_rs2_0.read(ba) << 0;
3072 
3073 // -----------------------------------------------------------------------------
3074 
3075  {
3076  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3077 
3078  cp.code() = std::string("//SLTU\n");
3079 
3080 // -----------------------------------------------------------------------------
3081 cp.code() += "etiss_coverage_count(1, 31);\n";
3082 { // block
3083 cp.code() += "etiss_coverage_count(1, 1169);\n";
3084 cp.code() += "{ // block\n";
3085 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3086 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3087 cp.code() += "} // block\n";
3088 } // block
3089 cp.code() += "etiss_coverage_count(1, 2017);\n";
3090 if ((rd % 32ULL) != 0LL) { // conditional
3091 cp.code() += "etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";
3092 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0LL);\n";
3093 cp.code() += "etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";
3094 } // conditional
3095 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3096 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3097 // -----------------------------------------------------------------------------
3098  cp.getAffectedRegisters().add("instructionPointer", 32);
3099  }
3100 
3101  return true;
3102  },
3103  0,
3104  [] (BitArray & ba, Instruction & instr)
3105  {
3106 // -----------------------------------------------------------------------------
3107 etiss_uint8 rd = 0;
3108 static BitArrayRange R_rd_0(11, 7);
3109 rd += R_rd_0.read(ba) << 0;
3110 etiss_uint8 rs1 = 0;
3111 static BitArrayRange R_rs1_0(19, 15);
3112 rs1 += R_rs1_0.read(ba) << 0;
3113 etiss_uint8 rs2 = 0;
3114 static BitArrayRange R_rs2_0(24, 20);
3115 rs2 += R_rs2_0.read(ba) << 0;
3116 
3117 // -----------------------------------------------------------------------------
3118 
3119  std::stringstream ss;
3120 // -----------------------------------------------------------------------------
3121 ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3122 // -----------------------------------------------------------------------------
3123  return ss.str();
3124  }
3125 );
3126 
3127 // XOR -------------------------------------------------------------------------
3128 static InstructionDefinition xor_rd_rs1_rs2 (
3129  ISA32_RV64IMACFD,
3130  "xor",
3131  (uint32_t) 0x004033,
3132  (uint32_t) 0xfe00707f,
3133  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3134  {
3135 
3136 // -----------------------------------------------------------------------------
3137 
3138 // -----------------------------------------------------------------------------
3139 
3140 // -----------------------------------------------------------------------------
3141 etiss_uint8 rd = 0;
3142 static BitArrayRange R_rd_0(11, 7);
3143 rd += R_rd_0.read(ba) << 0;
3144 etiss_uint8 rs1 = 0;
3145 static BitArrayRange R_rs1_0(19, 15);
3146 rs1 += R_rs1_0.read(ba) << 0;
3147 etiss_uint8 rs2 = 0;
3148 static BitArrayRange R_rs2_0(24, 20);
3149 rs2 += R_rs2_0.read(ba) << 0;
3150 
3151 // -----------------------------------------------------------------------------
3152 
3153  {
3154  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3155 
3156  cp.code() = std::string("//XOR\n");
3157 
3158 // -----------------------------------------------------------------------------
3159 cp.code() += "etiss_coverage_count(1, 32);\n";
3160 { // block
3161 cp.code() += "etiss_coverage_count(1, 1169);\n";
3162 cp.code() += "{ // block\n";
3163 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3164 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3165 cp.code() += "} // block\n";
3166 } // block
3167 cp.code() += "etiss_coverage_count(1, 2044);\n";
3168 if ((rd % 32ULL) != 0LL) { // conditional
3169 cp.code() += "etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";
3170 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3171 cp.code() += "etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";
3172 } // conditional
3173 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3174 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3175 // -----------------------------------------------------------------------------
3176  cp.getAffectedRegisters().add("instructionPointer", 32);
3177  }
3178 
3179  return true;
3180  },
3181  0,
3182  [] (BitArray & ba, Instruction & instr)
3183  {
3184 // -----------------------------------------------------------------------------
3185 etiss_uint8 rd = 0;
3186 static BitArrayRange R_rd_0(11, 7);
3187 rd += R_rd_0.read(ba) << 0;
3188 etiss_uint8 rs1 = 0;
3189 static BitArrayRange R_rs1_0(19, 15);
3190 rs1 += R_rs1_0.read(ba) << 0;
3191 etiss_uint8 rs2 = 0;
3192 static BitArrayRange R_rs2_0(24, 20);
3193 rs2 += R_rs2_0.read(ba) << 0;
3194 
3195 // -----------------------------------------------------------------------------
3196 
3197  std::stringstream ss;
3198 // -----------------------------------------------------------------------------
3199 ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3200 // -----------------------------------------------------------------------------
3201  return ss.str();
3202  }
3203 );
3204 
3205 // SRL -------------------------------------------------------------------------
3206 static InstructionDefinition srl_rd_rs1_rs2 (
3207  ISA32_RV64IMACFD,
3208  "srl",
3209  (uint32_t) 0x005033,
3210  (uint32_t) 0xfe00707f,
3211  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3212  {
3213 
3214 // -----------------------------------------------------------------------------
3215 
3216 // -----------------------------------------------------------------------------
3217 
3218 // -----------------------------------------------------------------------------
3219 etiss_uint8 rd = 0;
3220 static BitArrayRange R_rd_0(11, 7);
3221 rd += R_rd_0.read(ba) << 0;
3222 etiss_uint8 rs1 = 0;
3223 static BitArrayRange R_rs1_0(19, 15);
3224 rs1 += R_rs1_0.read(ba) << 0;
3225 etiss_uint8 rs2 = 0;
3226 static BitArrayRange R_rs2_0(24, 20);
3227 rs2 += R_rs2_0.read(ba) << 0;
3228 
3229 // -----------------------------------------------------------------------------
3230 
3231  {
3232  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3233 
3234  cp.code() = std::string("//SRL\n");
3235 
3236 // -----------------------------------------------------------------------------
3237 cp.code() += "etiss_coverage_count(1, 33);\n";
3238 { // block
3239 cp.code() += "etiss_coverage_count(1, 1169);\n";
3240 cp.code() += "{ // block\n";
3241 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3242 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3243 cp.code() += "} // block\n";
3244 } // block
3245 cp.code() += "etiss_coverage_count(1, 2068);\n";
3246 if ((rd % 32ULL) != 0LL) { // conditional
3247 cp.code() += "etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";
3248 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
3249 cp.code() += "etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";
3250 } // conditional
3251 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3252 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3253 // -----------------------------------------------------------------------------
3254  cp.getAffectedRegisters().add("instructionPointer", 32);
3255  }
3256 
3257  return true;
3258  },
3259  0,
3260  [] (BitArray & ba, Instruction & instr)
3261  {
3262 // -----------------------------------------------------------------------------
3263 etiss_uint8 rd = 0;
3264 static BitArrayRange R_rd_0(11, 7);
3265 rd += R_rd_0.read(ba) << 0;
3266 etiss_uint8 rs1 = 0;
3267 static BitArrayRange R_rs1_0(19, 15);
3268 rs1 += R_rs1_0.read(ba) << 0;
3269 etiss_uint8 rs2 = 0;
3270 static BitArrayRange R_rs2_0(24, 20);
3271 rs2 += R_rs2_0.read(ba) << 0;
3272 
3273 // -----------------------------------------------------------------------------
3274 
3275  std::stringstream ss;
3276 // -----------------------------------------------------------------------------
3277 ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3278 // -----------------------------------------------------------------------------
3279  return ss.str();
3280  }
3281 );
3282 
3283 // SRA -------------------------------------------------------------------------
3284 static InstructionDefinition sra_rd_rs1_rs2 (
3285  ISA32_RV64IMACFD,
3286  "sra",
3287  (uint32_t) 0x40005033,
3288  (uint32_t) 0xfe00707f,
3289  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3290  {
3291 
3292 // -----------------------------------------------------------------------------
3293 
3294 // -----------------------------------------------------------------------------
3295 
3296 // -----------------------------------------------------------------------------
3297 etiss_uint8 rd = 0;
3298 static BitArrayRange R_rd_0(11, 7);
3299 rd += R_rd_0.read(ba) << 0;
3300 etiss_uint8 rs1 = 0;
3301 static BitArrayRange R_rs1_0(19, 15);
3302 rs1 += R_rs1_0.read(ba) << 0;
3303 etiss_uint8 rs2 = 0;
3304 static BitArrayRange R_rs2_0(24, 20);
3305 rs2 += R_rs2_0.read(ba) << 0;
3306 
3307 // -----------------------------------------------------------------------------
3308 
3309  {
3310  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3311 
3312  cp.code() = std::string("//SRA\n");
3313 
3314 // -----------------------------------------------------------------------------
3315 cp.code() += "etiss_coverage_count(1, 34);\n";
3316 { // block
3317 cp.code() += "etiss_coverage_count(1, 1169);\n";
3318 cp.code() += "{ // block\n";
3319 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3320 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3321 cp.code() += "} // block\n";
3322 } // block
3323 cp.code() += "etiss_coverage_count(1, 2098);\n";
3324 if ((rd % 32ULL) != 0LL) { // conditional
3325 cp.code() += "etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";
3326 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
3327 cp.code() += "etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";
3328 } // conditional
3329 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3330 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3331 // -----------------------------------------------------------------------------
3332  cp.getAffectedRegisters().add("instructionPointer", 32);
3333  }
3334 
3335  return true;
3336  },
3337  0,
3338  [] (BitArray & ba, Instruction & instr)
3339  {
3340 // -----------------------------------------------------------------------------
3341 etiss_uint8 rd = 0;
3342 static BitArrayRange R_rd_0(11, 7);
3343 rd += R_rd_0.read(ba) << 0;
3344 etiss_uint8 rs1 = 0;
3345 static BitArrayRange R_rs1_0(19, 15);
3346 rs1 += R_rs1_0.read(ba) << 0;
3347 etiss_uint8 rs2 = 0;
3348 static BitArrayRange R_rs2_0(24, 20);
3349 rs2 += R_rs2_0.read(ba) << 0;
3350 
3351 // -----------------------------------------------------------------------------
3352 
3353  std::stringstream ss;
3354 // -----------------------------------------------------------------------------
3355 ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3356 // -----------------------------------------------------------------------------
3357  return ss.str();
3358  }
3359 );
3360 
3361 // OR --------------------------------------------------------------------------
3362 static InstructionDefinition or_rd_rs1_rs2 (
3363  ISA32_RV64IMACFD,
3364  "or",
3365  (uint32_t) 0x006033,
3366  (uint32_t) 0xfe00707f,
3367  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3368  {
3369 
3370 // -----------------------------------------------------------------------------
3371 
3372 // -----------------------------------------------------------------------------
3373 
3374 // -----------------------------------------------------------------------------
3375 etiss_uint8 rd = 0;
3376 static BitArrayRange R_rd_0(11, 7);
3377 rd += R_rd_0.read(ba) << 0;
3378 etiss_uint8 rs1 = 0;
3379 static BitArrayRange R_rs1_0(19, 15);
3380 rs1 += R_rs1_0.read(ba) << 0;
3381 etiss_uint8 rs2 = 0;
3382 static BitArrayRange R_rs2_0(24, 20);
3383 rs2 += R_rs2_0.read(ba) << 0;
3384 
3385 // -----------------------------------------------------------------------------
3386 
3387  {
3388  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3389 
3390  cp.code() = std::string("//OR\n");
3391 
3392 // -----------------------------------------------------------------------------
3393 cp.code() += "etiss_coverage_count(1, 35);\n";
3394 { // block
3395 cp.code() += "etiss_coverage_count(1, 1169);\n";
3396 cp.code() += "{ // block\n";
3397 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3398 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3399 cp.code() += "} // block\n";
3400 } // block
3401 cp.code() += "etiss_coverage_count(1, 2129);\n";
3402 if ((rd % 32ULL) != 0LL) { // conditional
3403 cp.code() += "etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";
3404 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3405 cp.code() += "etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";
3406 } // conditional
3407 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3408 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3409 // -----------------------------------------------------------------------------
3410  cp.getAffectedRegisters().add("instructionPointer", 32);
3411  }
3412 
3413  return true;
3414  },
3415  0,
3416  [] (BitArray & ba, Instruction & instr)
3417  {
3418 // -----------------------------------------------------------------------------
3419 etiss_uint8 rd = 0;
3420 static BitArrayRange R_rd_0(11, 7);
3421 rd += R_rd_0.read(ba) << 0;
3422 etiss_uint8 rs1 = 0;
3423 static BitArrayRange R_rs1_0(19, 15);
3424 rs1 += R_rs1_0.read(ba) << 0;
3425 etiss_uint8 rs2 = 0;
3426 static BitArrayRange R_rs2_0(24, 20);
3427 rs2 += R_rs2_0.read(ba) << 0;
3428 
3429 // -----------------------------------------------------------------------------
3430 
3431  std::stringstream ss;
3432 // -----------------------------------------------------------------------------
3433 ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3434 // -----------------------------------------------------------------------------
3435  return ss.str();
3436  }
3437 );
3438 
3439 // AND -------------------------------------------------------------------------
3440 static InstructionDefinition and_rd_rs1_rs2 (
3441  ISA32_RV64IMACFD,
3442  "and",
3443  (uint32_t) 0x007033,
3444  (uint32_t) 0xfe00707f,
3445  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3446  {
3447 
3448 // -----------------------------------------------------------------------------
3449 
3450 // -----------------------------------------------------------------------------
3451 
3452 // -----------------------------------------------------------------------------
3453 etiss_uint8 rd = 0;
3454 static BitArrayRange R_rd_0(11, 7);
3455 rd += R_rd_0.read(ba) << 0;
3456 etiss_uint8 rs1 = 0;
3457 static BitArrayRange R_rs1_0(19, 15);
3458 rs1 += R_rs1_0.read(ba) << 0;
3459 etiss_uint8 rs2 = 0;
3460 static BitArrayRange R_rs2_0(24, 20);
3461 rs2 += R_rs2_0.read(ba) << 0;
3462 
3463 // -----------------------------------------------------------------------------
3464 
3465  {
3466  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3467 
3468  cp.code() = std::string("//AND\n");
3469 
3470 // -----------------------------------------------------------------------------
3471 cp.code() += "etiss_coverage_count(1, 36);\n";
3472 { // block
3473 cp.code() += "etiss_coverage_count(1, 1169);\n";
3474 cp.code() += "{ // block\n";
3475 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3476 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3477 cp.code() += "} // block\n";
3478 } // block
3479 cp.code() += "etiss_coverage_count(1, 2153);\n";
3480 if ((rd % 32ULL) != 0LL) { // conditional
3481 cp.code() += "etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";
3482 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3483 cp.code() += "etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";
3484 } // conditional
3485 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3486 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3487 // -----------------------------------------------------------------------------
3488  cp.getAffectedRegisters().add("instructionPointer", 32);
3489  }
3490 
3491  return true;
3492  },
3493  0,
3494  [] (BitArray & ba, Instruction & instr)
3495  {
3496 // -----------------------------------------------------------------------------
3497 etiss_uint8 rd = 0;
3498 static BitArrayRange R_rd_0(11, 7);
3499 rd += R_rd_0.read(ba) << 0;
3500 etiss_uint8 rs1 = 0;
3501 static BitArrayRange R_rs1_0(19, 15);
3502 rs1 += R_rs1_0.read(ba) << 0;
3503 etiss_uint8 rs2 = 0;
3504 static BitArrayRange R_rs2_0(24, 20);
3505 rs2 += R_rs2_0.read(ba) << 0;
3506 
3507 // -----------------------------------------------------------------------------
3508 
3509  std::stringstream ss;
3510 // -----------------------------------------------------------------------------
3511 ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3512 // -----------------------------------------------------------------------------
3513  return ss.str();
3514  }
3515 );
3516 
3517 // FENCE -----------------------------------------------------------------------
3518 static InstructionDefinition fence_rd_rs1_succ_pred_fm (
3519  ISA32_RV64IMACFD,
3520  "fence",
3521  (uint32_t) 0x00000f,
3522  (uint32_t) 0x00707f,
3523  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3524  {
3525 
3526 // -----------------------------------------------------------------------------
3527 
3528 // -----------------------------------------------------------------------------
3529 
3530 // -----------------------------------------------------------------------------
3531 etiss_uint8 rd = 0;
3532 static BitArrayRange R_rd_0(11, 7);
3533 rd += R_rd_0.read(ba) << 0;
3534 etiss_uint8 rs1 = 0;
3535 static BitArrayRange R_rs1_0(19, 15);
3536 rs1 += R_rs1_0.read(ba) << 0;
3537 etiss_uint8 succ = 0;
3538 static BitArrayRange R_succ_0(23, 20);
3539 succ += R_succ_0.read(ba) << 0;
3540 etiss_uint8 pred = 0;
3541 static BitArrayRange R_pred_0(27, 24);
3542 pred += R_pred_0.read(ba) << 0;
3543 etiss_uint8 fm = 0;
3544 static BitArrayRange R_fm_0(31, 28);
3545 fm += R_fm_0.read(ba) << 0;
3546 
3547 // -----------------------------------------------------------------------------
3548 
3549  {
3550  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3551 
3552  cp.code() = std::string("//FENCE\n");
3553 
3554 // -----------------------------------------------------------------------------
3555 cp.code() += "etiss_coverage_count(1, 37);\n";
3556 { // block
3557 cp.code() += "etiss_coverage_count(1, 1169);\n";
3558 cp.code() += "{ // block\n";
3559 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3560 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3561 cp.code() += "} // block\n";
3562 } // block
3563 cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
3564 cp.code() += "etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";
3565 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3566 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3567 // -----------------------------------------------------------------------------
3568  cp.getAffectedRegisters().add("instructionPointer", 32);
3569  }
3570 
3571  return true;
3572  },
3573  0,
3574  [] (BitArray & ba, Instruction & instr)
3575  {
3576 // -----------------------------------------------------------------------------
3577 etiss_uint8 rd = 0;
3578 static BitArrayRange R_rd_0(11, 7);
3579 rd += R_rd_0.read(ba) << 0;
3580 etiss_uint8 rs1 = 0;
3581 static BitArrayRange R_rs1_0(19, 15);
3582 rs1 += R_rs1_0.read(ba) << 0;
3583 etiss_uint8 succ = 0;
3584 static BitArrayRange R_succ_0(23, 20);
3585 succ += R_succ_0.read(ba) << 0;
3586 etiss_uint8 pred = 0;
3587 static BitArrayRange R_pred_0(27, 24);
3588 pred += R_pred_0.read(ba) << 0;
3589 etiss_uint8 fm = 0;
3590 static BitArrayRange R_fm_0(31, 28);
3591 fm += R_fm_0.read(ba) << 0;
3592 
3593 // -----------------------------------------------------------------------------
3594 
3595  std::stringstream ss;
3596 // -----------------------------------------------------------------------------
3597 ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
3598 // -----------------------------------------------------------------------------
3599  return ss.str();
3600  }
3601 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
lb_rd_rs1_imm
static InstructionDefinition lb_rd_rs1_imm(ISA32_RV64IMACFD, "lb",(uint32_t) 0x000003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="etiss_coverage_count(1, 10);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1498);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int8 res = (etiss_int8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";cp.code()+="etiss_coverage_count(1, 1482);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lb"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV64IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");cp.code()+="etiss_coverage_count(1, 25);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1868);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
beq_imm_rs1_rs2
static InstructionDefinition beq_imm_rs1_rs2(ISA32_RV64IMACFD, "beq",(uint32_t) 0x000063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="etiss_coverage_count(1, 4);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1311);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1283);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";{ cp.code()+="etiss_coverage_count(1, 1310);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1295);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1298, 1296);\n";{ cp.code()+="etiss_coverage_count(1, 1302);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1301, 1299);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1309);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "beq"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RV64IMACFD, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUB\n");cp.code()+="etiss_coverage_count(1, 28);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1934);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] - *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sub"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lhu_rd_rs1_imm
static InstructionDefinition lhu_rd_rs1_imm(ISA32_RV64IMACFD, "lhu",(uint32_t) 0x005003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="etiss_coverage_count(1, 14);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1634);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";cp.code()+="etiss_coverage_count(1, 1618);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bgeu_imm_rs1_rs2
static InstructionDefinition bgeu_imm_rs1_rs2(ISA32_RV64IMACFD, "bgeu",(uint32_t) 0x007063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="etiss_coverage_count(1, 9);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1464);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1436);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >= *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";{ cp.code()+="etiss_coverage_count(1, 1463);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1448);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1451, 1449);\n";{ cp.code()+="etiss_coverage_count(1, 1455);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1454, 1452);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1462);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bgeu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RV64IMACFD, "jalr",(uint32_t) 0x000067,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="etiss_coverage_count(1, 3);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1282);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL) & -2LL;\n";cp.code()+="etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";cp.code()+="etiss_coverage_count(1, 1251);\n";cp.code()+="if (new_pc % 2ULL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 1254, 1252);\n";{ cp.code()+="etiss_coverage_count(1, 1258);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1257, 1255);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 1281);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1259);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";} cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "jalr"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RV64IMACFD, "slt",(uint32_t) 0x002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLT\n");cp.code()+="etiss_coverage_count(1, 30);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1988);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "slt"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RV64IMACFD, "andi",(uint32_t) 0x007013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ANDI\n");cp.code()+="etiss_coverage_count(1, 23);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1824);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "andi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sb_imm_rs1_rs2
static InstructionDefinition sb_imm_rs1_rs2(ISA32_RV64IMACFD, "sb",(uint32_t) 0x000023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="etiss_coverage_count(1, 15);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1656);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sb"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
blt_imm_rs1_rs2
static InstructionDefinition blt_imm_rs1_rs2(ISA32_RV64IMACFD, "blt",(uint32_t) 0x004063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="etiss_coverage_count(1, 6);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1373);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1341);\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";{ cp.code()+="etiss_coverage_count(1, 1372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1357);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1360, 1358);\n";{ cp.code()+="etiss_coverage_count(1, 1364);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1363, 1361);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1371);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "blt"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sh_imm_rs1_rs2
static InstructionDefinition sh_imm_rs1_rs2(ISA32_RV64IMACFD, "sh",(uint32_t) 0x001023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="etiss_coverage_count(1, 16);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1678);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sh"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bge_imm_rs1_rs2
static InstructionDefinition bge_imm_rs1_rs2(ISA32_RV64IMACFD, "bge",(uint32_t) 0x005063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="etiss_coverage_count(1, 7);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1374);\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";{ cp.code()+="etiss_coverage_count(1, 1405);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1390);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1393, 1391);\n";{ cp.code()+="etiss_coverage_count(1, 1397);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1396, 1394);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1404);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bge"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RV64IMACFD, "lui",(uint32_t) 0x000037,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LUI\n");cp.code()+="etiss_coverage_count(1, 0);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1170);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string((etiss_uint64)(((etiss_int32)(imm))))+"ULL;\n";cp.code()+="etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "lui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sw_imm_rs1_rs2
static InstructionDefinition sw_imm_rs1_rs2(ISA32_RV64IMACFD, "sw",(uint32_t) 0x002023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="etiss_coverage_count(1, 17);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1700);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fence_rd_rs1_succ_pred_fm
static InstructionDefinition fence_rd_rs1_succ_pred_fm(ISA32_RV64IMACFD, "fence",(uint32_t) 0x00000f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE\n");cp.code()+="etiss_coverage_count(1, 37);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="((RV64IMACFD*)cpu)->FENCE[0ULL] = "+std::to_string(pred<< 4ULL|succ)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | succ="+std::to_string(succ)+" | pred="+std::to_string(pred)+" | fm="+std::to_string(fm)+"]");return ss.str();})
lbu_rd_rs1_imm
static InstructionDefinition lbu_rd_rs1_imm(ISA32_RV64IMACFD, "lbu",(uint32_t) 0x004003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="etiss_coverage_count(1, 13);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1600);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";cp.code()+="etiss_coverage_count(1, 1584);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lbu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RV64IMACFD, "srl",(uint32_t) 0x005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRL\n");cp.code()+="etiss_coverage_count(1, 33);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2068);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srl"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RV64IMACFD, "ori",(uint32_t) 0x006013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ORI\n");cp.code()+="etiss_coverage_count(1, 22);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1800);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lh_rd_rs1_imm
static InstructionDefinition lh_rd_rs1_imm(ISA32_RV64IMACFD, "lh",(uint32_t) 0x001003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="etiss_coverage_count(1, 11);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1532);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int16 res = (etiss_int16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";cp.code()+="etiss_coverage_count(1, 1516);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RV64IMACFD, "sltiu",(uint32_t) 0x003013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTIU\n");cp.code()+="etiss_coverage_count(1, 20);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1748);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "sltiu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bltu_imm_rs1_rs2
static InstructionDefinition bltu_imm_rs1_rs2(ISA32_RV64IMACFD, "bltu",(uint32_t) 0x006063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="etiss_coverage_count(1, 8);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1435);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1407);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";{ cp.code()+="etiss_coverage_count(1, 1434);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1419);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1422, 1420);\n";{ cp.code()+="etiss_coverage_count(1, 1426);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1425, 1423);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1433);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bltu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bne_imm_rs1_rs2
static InstructionDefinition bne_imm_rs1_rs2(ISA32_RV64IMACFD, "bne",(uint32_t) 0x001063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="etiss_coverage_count(1, 5);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1340);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1312);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] != *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";{ cp.code()+="etiss_coverage_count(1, 1339);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1324);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1327, 1325);\n";{ cp.code()+="etiss_coverage_count(1, 1331);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1330, 1328);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1338);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bne"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RV64IMACFD, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRA\n");cp.code()+="etiss_coverage_count(1, 34);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2098);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sra"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RV64IMACFD, "xor",(uint32_t) 0x004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XOR\n");cp.code()+="etiss_coverage_count(1, 32);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2044);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "xor"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RV64IMACFD, "addi",(uint32_t) 0x000013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDI\n");cp.code()+="etiss_coverage_count(1, 18);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1701);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV64IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");cp.code()+="etiss_coverage_count(1, 24);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1848);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RV64IMACFD, "sltu",(uint32_t) 0x003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTU\n");cp.code()+="etiss_coverage_count(1, 31);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2017);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sltu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RV64IMACFD, "jal",(uint32_t) 0x00006f,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="etiss_coverage_count(1, 2);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1236);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1205);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1208, 1206);\n";{ cp.code()+="etiss_coverage_count(1, 1212);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1211, 1209);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1235);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1213);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int32)(((etiss_int32) imm)<<(11)) >>(11)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;std::stringstream ss;ss<< "jal"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RV64IMACFD, "or",(uint32_t) 0x006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//OR\n");cp.code()+="etiss_coverage_count(1, 35);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2129);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "or"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RV64IMACFD, "add",(uint32_t) 0x000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADD\n");cp.code()+="etiss_coverage_count(1, 27);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1910);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "add"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RV64IMACFD, "xori",(uint32_t) 0x004013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XORI\n");cp.code()+="etiss_coverage_count(1, 21);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1776);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "xori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RV64IMACFD, "slti",(uint32_t) 0x002013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTI\n");cp.code()+="etiss_coverage_count(1, 19);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1722);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "slti"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RV64IMACFD, "and",(uint32_t) 0x007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AND\n");cp.code()+="etiss_coverage_count(1, 36);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2153);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "and"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RV64IMACFD, "auipc",(uint32_t) 0x000017,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AUIPC\n");cp.code()+="etiss_coverage_count(1, 1);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1188);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+(etiss_int32)(imm))+"LL;\n";cp.code()+="etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "auipc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lw_rd_rs1_imm
static InstructionDefinition lw_rd_rs1_imm(ISA32_RV64IMACFD, "lw",(uint32_t) 0x002003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="etiss_coverage_count(1, 12);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1566);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";cp.code()+="etiss_coverage_count(1, 1550);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RV64IMACFD, "sll",(uint32_t) 0x001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLL\n");cp.code()+="etiss_coverage_count(1, 29);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1958);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";cp.code()+="etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sll"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV64IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");cp.code()+="etiss_coverage_count(1, 26);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1888);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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