ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32IInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LUI -------------------------------------------------------------------------
16 static InstructionDefinition lui_rd_imm (
17  ISA32_RV64IMACFD,
18  "lui",
19  (uint32_t) 0x000037,
20  (uint32_t) 0x00007f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint32 imm = 0;
33 static BitArrayRange R_imm_12(31, 12);
34 imm += R_imm_12.read(ba) << 12;
35 
36 // -----------------------------------------------------------------------------
37 
38  {
39  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
40 
41  cp.code() = std::string("//LUI\n");
42 
43 // -----------------------------------------------------------------------------
44 { // block
45 cp.code() += "{ // block\n";
46 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
47 cp.code() += "} // block\n";
48 } // block
49 if ((rd % 32ULL) != 0LL) { // conditional
50 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n";
51 } // conditional
52 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
53 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
54 // -----------------------------------------------------------------------------
55  cp.getAffectedRegisters().add("instructionPointer", 32);
56  }
57 
58  return true;
59  },
60  0,
61  [] (BitArray & ba, Instruction & instr)
62  {
63 // -----------------------------------------------------------------------------
64 etiss_uint8 rd = 0;
65 static BitArrayRange R_rd_0(11, 7);
66 rd += R_rd_0.read(ba) << 0;
67 etiss_uint32 imm = 0;
68 static BitArrayRange R_imm_12(31, 12);
69 imm += R_imm_12.read(ba) << 12;
70 
71 // -----------------------------------------------------------------------------
72 
73  std::stringstream ss;
74 // -----------------------------------------------------------------------------
75 ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
76 // -----------------------------------------------------------------------------
77  return ss.str();
78  }
79 );
80 
81 // AUIPC -----------------------------------------------------------------------
82 static InstructionDefinition auipc_rd_imm (
83  ISA32_RV64IMACFD,
84  "auipc",
85  (uint32_t) 0x000017,
86  (uint32_t) 0x00007f,
87  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
88  {
89 
90 // -----------------------------------------------------------------------------
91 
92 // -----------------------------------------------------------------------------
93 
94 // -----------------------------------------------------------------------------
95 etiss_uint8 rd = 0;
96 static BitArrayRange R_rd_0(11, 7);
97 rd += R_rd_0.read(ba) << 0;
98 etiss_uint32 imm = 0;
99 static BitArrayRange R_imm_12(31, 12);
100 imm += R_imm_12.read(ba) << 12;
101 
102 // -----------------------------------------------------------------------------
103 
104  {
105  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
106 
107  cp.code() = std::string("//AUIPC\n");
108 
109 // -----------------------------------------------------------------------------
110 { // block
111 cp.code() += "{ // block\n";
112 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
113 cp.code() += "} // block\n";
114 } // block
115 if ((rd % 32ULL) != 0LL) { // conditional
116 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
117 } // conditional
118 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
119 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
120 // -----------------------------------------------------------------------------
121  cp.getAffectedRegisters().add("instructionPointer", 32);
122  }
123 
124  return true;
125  },
126  0,
127  [] (BitArray & ba, Instruction & instr)
128  {
129 // -----------------------------------------------------------------------------
130 etiss_uint8 rd = 0;
131 static BitArrayRange R_rd_0(11, 7);
132 rd += R_rd_0.read(ba) << 0;
133 etiss_uint32 imm = 0;
134 static BitArrayRange R_imm_12(31, 12);
135 imm += R_imm_12.read(ba) << 12;
136 
137 // -----------------------------------------------------------------------------
138 
139  std::stringstream ss;
140 // -----------------------------------------------------------------------------
141 ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
142 // -----------------------------------------------------------------------------
143  return ss.str();
144  }
145 );
146 
147 // JAL -------------------------------------------------------------------------
148 static InstructionDefinition jal_rd_imm (
149  ISA32_RV64IMACFD,
150  "jal",
151  (uint32_t) 0x00006f,
152  (uint32_t) 0x00007f,
153  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
154  {
155 
156 // -----------------------------------------------------------------------------
157 
158 // -----------------------------------------------------------------------------
159 
160 // -----------------------------------------------------------------------------
161 etiss_uint8 rd = 0;
162 static BitArrayRange R_rd_0(11, 7);
163 rd += R_rd_0.read(ba) << 0;
164 etiss_uint32 imm = 0;
165 static BitArrayRange R_imm_12(19, 12);
166 imm += R_imm_12.read(ba) << 12;
167 static BitArrayRange R_imm_11(20, 20);
168 imm += R_imm_11.read(ba) << 11;
169 static BitArrayRange R_imm_1(30, 21);
170 imm += R_imm_1.read(ba) << 1;
171 static BitArrayRange R_imm_20(31, 31);
172 imm += R_imm_20.read(ba) << 20;
173 
174 // -----------------------------------------------------------------------------
175 
176  {
177  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
178 
179  cp.code() = std::string("//JAL\n");
180 
181 // -----------------------------------------------------------------------------
182 { // block
183 cp.code() += "{ // block\n";
184 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
185 cp.code() += "} // block\n";
186 } // block
187 { // block
188 cp.code() += "{ // block\n";
189 if (imm % 2ULL) { // conditional
190 { // block
191 cp.code() += "{ // block\n";
192 { // procedure
193 cp.code() += "{ // procedure\n";
194 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
195 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
196 cp.code() += "} // procedure\n";
197 } // procedure
198 cp.code() += "} // block\n";
199 } // block
200 } // conditional
201 else { // conditional
202 { // block
203 cp.code() += "{ // block\n";
204 if ((rd % 32ULL) != 0LL) { // conditional
205 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
206 } // conditional
207 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
208 cp.code() += "} // block\n";
209 } // block
210 } // conditional
211 cp.code() += "} // block\n";
212 } // block
213 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
214 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
215 // -----------------------------------------------------------------------------
216  cp.getAffectedRegisters().add("instructionPointer", 32);
217  }
218  {
219  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
220 
221  cp.code() = std::string("//JAL\n");
222 
223 // -----------------------------------------------------------------------------
224 cp.code() += "return cpu->exception;\n";
225 // -----------------------------------------------------------------------------
226  }
227 
228  return true;
229  },
230  0,
231  [] (BitArray & ba, Instruction & instr)
232  {
233 // -----------------------------------------------------------------------------
234 etiss_uint8 rd = 0;
235 static BitArrayRange R_rd_0(11, 7);
236 rd += R_rd_0.read(ba) << 0;
237 etiss_uint32 imm = 0;
238 static BitArrayRange R_imm_12(19, 12);
239 imm += R_imm_12.read(ba) << 12;
240 static BitArrayRange R_imm_11(20, 20);
241 imm += R_imm_11.read(ba) << 11;
242 static BitArrayRange R_imm_1(30, 21);
243 imm += R_imm_1.read(ba) << 1;
244 static BitArrayRange R_imm_20(31, 31);
245 imm += R_imm_20.read(ba) << 20;
246 
247 // -----------------------------------------------------------------------------
248 
249  std::stringstream ss;
250 // -----------------------------------------------------------------------------
251 ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
252 // -----------------------------------------------------------------------------
253  return ss.str();
254  }
255 );
256 
257 // JALR ------------------------------------------------------------------------
258 static InstructionDefinition jalr_rd_rs1_imm (
259  ISA32_RV64IMACFD,
260  "jalr",
261  (uint32_t) 0x000067,
262  (uint32_t) 0x00707f,
263  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
264  {
265 
266 // -----------------------------------------------------------------------------
267 
268 // -----------------------------------------------------------------------------
269 
270 // -----------------------------------------------------------------------------
271 etiss_uint8 rd = 0;
272 static BitArrayRange R_rd_0(11, 7);
273 rd += R_rd_0.read(ba) << 0;
274 etiss_uint8 rs1 = 0;
275 static BitArrayRange R_rs1_0(19, 15);
276 rs1 += R_rs1_0.read(ba) << 0;
277 etiss_uint16 imm = 0;
278 static BitArrayRange R_imm_0(31, 20);
279 imm += R_imm_0.read(ba) << 0;
280 
281 // -----------------------------------------------------------------------------
282 
283  {
284  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
285 
286  cp.code() = std::string("//JALR\n");
287 
288 // -----------------------------------------------------------------------------
289 { // block
290 cp.code() += "{ // block\n";
291 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
292 cp.code() += "} // block\n";
293 } // block
294 { // block
295 cp.code() += "{ // block\n";
296 cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
297 cp.code() += "if (new_pc % 2ULL) { // conditional\n";
298 { // block
299 cp.code() += "{ // block\n";
300 { // procedure
301 cp.code() += "{ // procedure\n";
302 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
303 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
304 cp.code() += "} // procedure\n";
305 } // procedure
306 cp.code() += "} // block\n";
307 } // block
308 cp.code() += "} // conditional\n";
309 cp.code() += "else { // conditional\n";
310 { // block
311 cp.code() += "{ // block\n";
312 if ((rd % 32ULL) != 0LL) { // conditional
313 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
314 } // conditional
315 cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
316 cp.code() += "} // block\n";
317 } // block
318 cp.code() += "} // conditional\n";
319 cp.code() += "} // block\n";
320 } // block
321 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
322 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
323 // -----------------------------------------------------------------------------
324  cp.getAffectedRegisters().add("instructionPointer", 32);
325  }
326  {
327  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
328 
329  cp.code() = std::string("//JALR\n");
330 
331 // -----------------------------------------------------------------------------
332 cp.code() += "return cpu->exception;\n";
333 // -----------------------------------------------------------------------------
334  }
335 
336  return true;
337  },
338  0,
339  [] (BitArray & ba, Instruction & instr)
340  {
341 // -----------------------------------------------------------------------------
342 etiss_uint8 rd = 0;
343 static BitArrayRange R_rd_0(11, 7);
344 rd += R_rd_0.read(ba) << 0;
345 etiss_uint8 rs1 = 0;
346 static BitArrayRange R_rs1_0(19, 15);
347 rs1 += R_rs1_0.read(ba) << 0;
348 etiss_uint16 imm = 0;
349 static BitArrayRange R_imm_0(31, 20);
350 imm += R_imm_0.read(ba) << 0;
351 
352 // -----------------------------------------------------------------------------
353 
354  std::stringstream ss;
355 // -----------------------------------------------------------------------------
356 ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
357 // -----------------------------------------------------------------------------
358  return ss.str();
359  }
360 );
361 
362 // BEQ -------------------------------------------------------------------------
363 static InstructionDefinition beq_imm_rs1_rs2 (
364  ISA32_RV64IMACFD,
365  "beq",
366  (uint32_t) 0x000063,
367  (uint32_t) 0x00707f,
368  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
369  {
370 
371 // -----------------------------------------------------------------------------
372 
373 // -----------------------------------------------------------------------------
374 
375 // -----------------------------------------------------------------------------
376 etiss_uint16 imm = 0;
377 static BitArrayRange R_imm_11(7, 7);
378 imm += R_imm_11.read(ba) << 11;
379 static BitArrayRange R_imm_1(11, 8);
380 imm += R_imm_1.read(ba) << 1;
381 etiss_uint8 rs1 = 0;
382 static BitArrayRange R_rs1_0(19, 15);
383 rs1 += R_rs1_0.read(ba) << 0;
384 etiss_uint8 rs2 = 0;
385 static BitArrayRange R_rs2_0(24, 20);
386 rs2 += R_rs2_0.read(ba) << 0;
387 static BitArrayRange R_imm_5(30, 25);
388 imm += R_imm_5.read(ba) << 5;
389 static BitArrayRange R_imm_12(31, 31);
390 imm += R_imm_12.read(ba) << 12;
391 
392 // -----------------------------------------------------------------------------
393 
394  {
395  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
396 
397  cp.code() = std::string("//BEQ\n");
398 
399 // -----------------------------------------------------------------------------
400 { // block
401 cp.code() += "{ // block\n";
402 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
403 cp.code() += "} // block\n";
404 } // block
405 { // block
406 cp.code() += "{ // block\n";
407 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
408 { // block
409 cp.code() += "{ // block\n";
410 if (imm % 2ULL) { // conditional
411 { // block
412 cp.code() += "{ // block\n";
413 { // procedure
414 cp.code() += "{ // procedure\n";
415 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
416 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
417 cp.code() += "} // procedure\n";
418 } // procedure
419 cp.code() += "} // block\n";
420 } // block
421 } // conditional
422 else { // conditional
423 { // block
424 cp.code() += "{ // block\n";
425 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
426 cp.code() += "} // block\n";
427 } // block
428 } // conditional
429 cp.code() += "} // block\n";
430 } // block
431 cp.code() += "} // conditional\n";
432 cp.code() += "} // block\n";
433 } // block
434 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
435 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
436 // -----------------------------------------------------------------------------
437  cp.getAffectedRegisters().add("instructionPointer", 32);
438  }
439  {
440  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
441 
442  cp.code() = std::string("//BEQ\n");
443 
444 // -----------------------------------------------------------------------------
445 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
446 // -----------------------------------------------------------------------------
447  }
448 
449  return true;
450  },
451  0,
452  [] (BitArray & ba, Instruction & instr)
453  {
454 // -----------------------------------------------------------------------------
455 etiss_uint16 imm = 0;
456 static BitArrayRange R_imm_11(7, 7);
457 imm += R_imm_11.read(ba) << 11;
458 static BitArrayRange R_imm_1(11, 8);
459 imm += R_imm_1.read(ba) << 1;
460 etiss_uint8 rs1 = 0;
461 static BitArrayRange R_rs1_0(19, 15);
462 rs1 += R_rs1_0.read(ba) << 0;
463 etiss_uint8 rs2 = 0;
464 static BitArrayRange R_rs2_0(24, 20);
465 rs2 += R_rs2_0.read(ba) << 0;
466 static BitArrayRange R_imm_5(30, 25);
467 imm += R_imm_5.read(ba) << 5;
468 static BitArrayRange R_imm_12(31, 31);
469 imm += R_imm_12.read(ba) << 12;
470 
471 // -----------------------------------------------------------------------------
472 
473  std::stringstream ss;
474 // -----------------------------------------------------------------------------
475 ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
476 // -----------------------------------------------------------------------------
477  return ss.str();
478  }
479 );
480 
481 // BNE -------------------------------------------------------------------------
482 static InstructionDefinition bne_imm_rs1_rs2 (
483  ISA32_RV64IMACFD,
484  "bne",
485  (uint32_t) 0x001063,
486  (uint32_t) 0x00707f,
487  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
488  {
489 
490 // -----------------------------------------------------------------------------
491 
492 // -----------------------------------------------------------------------------
493 
494 // -----------------------------------------------------------------------------
495 etiss_uint16 imm = 0;
496 static BitArrayRange R_imm_11(7, 7);
497 imm += R_imm_11.read(ba) << 11;
498 static BitArrayRange R_imm_1(11, 8);
499 imm += R_imm_1.read(ba) << 1;
500 etiss_uint8 rs1 = 0;
501 static BitArrayRange R_rs1_0(19, 15);
502 rs1 += R_rs1_0.read(ba) << 0;
503 etiss_uint8 rs2 = 0;
504 static BitArrayRange R_rs2_0(24, 20);
505 rs2 += R_rs2_0.read(ba) << 0;
506 static BitArrayRange R_imm_5(30, 25);
507 imm += R_imm_5.read(ba) << 5;
508 static BitArrayRange R_imm_12(31, 31);
509 imm += R_imm_12.read(ba) << 12;
510 
511 // -----------------------------------------------------------------------------
512 
513  {
514  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
515 
516  cp.code() = std::string("//BNE\n");
517 
518 // -----------------------------------------------------------------------------
519 { // block
520 cp.code() += "{ // block\n";
521 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
522 cp.code() += "} // block\n";
523 } // block
524 { // block
525 cp.code() += "{ // block\n";
526 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
527 { // block
528 cp.code() += "{ // block\n";
529 if (imm % 2ULL) { // conditional
530 { // block
531 cp.code() += "{ // block\n";
532 { // procedure
533 cp.code() += "{ // procedure\n";
534 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
535 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
536 cp.code() += "} // procedure\n";
537 } // procedure
538 cp.code() += "} // block\n";
539 } // block
540 } // conditional
541 else { // conditional
542 { // block
543 cp.code() += "{ // block\n";
544 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
545 cp.code() += "} // block\n";
546 } // block
547 } // conditional
548 cp.code() += "} // block\n";
549 } // block
550 cp.code() += "} // conditional\n";
551 cp.code() += "} // block\n";
552 } // block
553 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
554 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
555 // -----------------------------------------------------------------------------
556  cp.getAffectedRegisters().add("instructionPointer", 32);
557  }
558  {
559  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
560 
561  cp.code() = std::string("//BNE\n");
562 
563 // -----------------------------------------------------------------------------
564 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
565 // -----------------------------------------------------------------------------
566  }
567 
568  return true;
569  },
570  0,
571  [] (BitArray & ba, Instruction & instr)
572  {
573 // -----------------------------------------------------------------------------
574 etiss_uint16 imm = 0;
575 static BitArrayRange R_imm_11(7, 7);
576 imm += R_imm_11.read(ba) << 11;
577 static BitArrayRange R_imm_1(11, 8);
578 imm += R_imm_1.read(ba) << 1;
579 etiss_uint8 rs1 = 0;
580 static BitArrayRange R_rs1_0(19, 15);
581 rs1 += R_rs1_0.read(ba) << 0;
582 etiss_uint8 rs2 = 0;
583 static BitArrayRange R_rs2_0(24, 20);
584 rs2 += R_rs2_0.read(ba) << 0;
585 static BitArrayRange R_imm_5(30, 25);
586 imm += R_imm_5.read(ba) << 5;
587 static BitArrayRange R_imm_12(31, 31);
588 imm += R_imm_12.read(ba) << 12;
589 
590 // -----------------------------------------------------------------------------
591 
592  std::stringstream ss;
593 // -----------------------------------------------------------------------------
594 ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
595 // -----------------------------------------------------------------------------
596  return ss.str();
597  }
598 );
599 
600 // BLT -------------------------------------------------------------------------
601 static InstructionDefinition blt_imm_rs1_rs2 (
602  ISA32_RV64IMACFD,
603  "blt",
604  (uint32_t) 0x004063,
605  (uint32_t) 0x00707f,
606  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
607  {
608 
609 // -----------------------------------------------------------------------------
610 
611 // -----------------------------------------------------------------------------
612 
613 // -----------------------------------------------------------------------------
614 etiss_uint16 imm = 0;
615 static BitArrayRange R_imm_11(7, 7);
616 imm += R_imm_11.read(ba) << 11;
617 static BitArrayRange R_imm_1(11, 8);
618 imm += R_imm_1.read(ba) << 1;
619 etiss_uint8 rs1 = 0;
620 static BitArrayRange R_rs1_0(19, 15);
621 rs1 += R_rs1_0.read(ba) << 0;
622 etiss_uint8 rs2 = 0;
623 static BitArrayRange R_rs2_0(24, 20);
624 rs2 += R_rs2_0.read(ba) << 0;
625 static BitArrayRange R_imm_5(30, 25);
626 imm += R_imm_5.read(ba) << 5;
627 static BitArrayRange R_imm_12(31, 31);
628 imm += R_imm_12.read(ba) << 12;
629 
630 // -----------------------------------------------------------------------------
631 
632  {
633  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
634 
635  cp.code() = std::string("//BLT\n");
636 
637 // -----------------------------------------------------------------------------
638 { // block
639 cp.code() += "{ // block\n";
640 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
641 cp.code() += "} // block\n";
642 } // block
643 { // block
644 cp.code() += "{ // block\n";
645 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
646 { // block
647 cp.code() += "{ // block\n";
648 if (imm % 2ULL) { // conditional
649 { // block
650 cp.code() += "{ // block\n";
651 { // procedure
652 cp.code() += "{ // procedure\n";
653 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
654 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
655 cp.code() += "} // procedure\n";
656 } // procedure
657 cp.code() += "} // block\n";
658 } // block
659 } // conditional
660 else { // conditional
661 { // block
662 cp.code() += "{ // block\n";
663 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
664 cp.code() += "} // block\n";
665 } // block
666 } // conditional
667 cp.code() += "} // block\n";
668 } // block
669 cp.code() += "} // conditional\n";
670 cp.code() += "} // block\n";
671 } // block
672 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
673 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
674 // -----------------------------------------------------------------------------
675  cp.getAffectedRegisters().add("instructionPointer", 32);
676  }
677  {
678  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
679 
680  cp.code() = std::string("//BLT\n");
681 
682 // -----------------------------------------------------------------------------
683 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
684 // -----------------------------------------------------------------------------
685  }
686 
687  return true;
688  },
689  0,
690  [] (BitArray & ba, Instruction & instr)
691  {
692 // -----------------------------------------------------------------------------
693 etiss_uint16 imm = 0;
694 static BitArrayRange R_imm_11(7, 7);
695 imm += R_imm_11.read(ba) << 11;
696 static BitArrayRange R_imm_1(11, 8);
697 imm += R_imm_1.read(ba) << 1;
698 etiss_uint8 rs1 = 0;
699 static BitArrayRange R_rs1_0(19, 15);
700 rs1 += R_rs1_0.read(ba) << 0;
701 etiss_uint8 rs2 = 0;
702 static BitArrayRange R_rs2_0(24, 20);
703 rs2 += R_rs2_0.read(ba) << 0;
704 static BitArrayRange R_imm_5(30, 25);
705 imm += R_imm_5.read(ba) << 5;
706 static BitArrayRange R_imm_12(31, 31);
707 imm += R_imm_12.read(ba) << 12;
708 
709 // -----------------------------------------------------------------------------
710 
711  std::stringstream ss;
712 // -----------------------------------------------------------------------------
713 ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
714 // -----------------------------------------------------------------------------
715  return ss.str();
716  }
717 );
718 
719 // BGE -------------------------------------------------------------------------
720 static InstructionDefinition bge_imm_rs1_rs2 (
721  ISA32_RV64IMACFD,
722  "bge",
723  (uint32_t) 0x005063,
724  (uint32_t) 0x00707f,
725  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
726  {
727 
728 // -----------------------------------------------------------------------------
729 
730 // -----------------------------------------------------------------------------
731 
732 // -----------------------------------------------------------------------------
733 etiss_uint16 imm = 0;
734 static BitArrayRange R_imm_11(7, 7);
735 imm += R_imm_11.read(ba) << 11;
736 static BitArrayRange R_imm_1(11, 8);
737 imm += R_imm_1.read(ba) << 1;
738 etiss_uint8 rs1 = 0;
739 static BitArrayRange R_rs1_0(19, 15);
740 rs1 += R_rs1_0.read(ba) << 0;
741 etiss_uint8 rs2 = 0;
742 static BitArrayRange R_rs2_0(24, 20);
743 rs2 += R_rs2_0.read(ba) << 0;
744 static BitArrayRange R_imm_5(30, 25);
745 imm += R_imm_5.read(ba) << 5;
746 static BitArrayRange R_imm_12(31, 31);
747 imm += R_imm_12.read(ba) << 12;
748 
749 // -----------------------------------------------------------------------------
750 
751  {
752  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
753 
754  cp.code() = std::string("//BGE\n");
755 
756 // -----------------------------------------------------------------------------
757 { // block
758 cp.code() += "{ // block\n";
759 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
760 cp.code() += "} // block\n";
761 } // block
762 { // block
763 cp.code() += "{ // block\n";
764 cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
765 { // block
766 cp.code() += "{ // block\n";
767 if (imm % 2ULL) { // conditional
768 { // block
769 cp.code() += "{ // block\n";
770 { // procedure
771 cp.code() += "{ // procedure\n";
772 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
773 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
774 cp.code() += "} // procedure\n";
775 } // procedure
776 cp.code() += "} // block\n";
777 } // block
778 } // conditional
779 else { // conditional
780 { // block
781 cp.code() += "{ // block\n";
782 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
783 cp.code() += "} // block\n";
784 } // block
785 } // conditional
786 cp.code() += "} // block\n";
787 } // block
788 cp.code() += "} // conditional\n";
789 cp.code() += "} // block\n";
790 } // block
791 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
792 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
793 // -----------------------------------------------------------------------------
794  cp.getAffectedRegisters().add("instructionPointer", 32);
795  }
796  {
797  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
798 
799  cp.code() = std::string("//BGE\n");
800 
801 // -----------------------------------------------------------------------------
802 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
803 // -----------------------------------------------------------------------------
804  }
805 
806  return true;
807  },
808  0,
809  [] (BitArray & ba, Instruction & instr)
810  {
811 // -----------------------------------------------------------------------------
812 etiss_uint16 imm = 0;
813 static BitArrayRange R_imm_11(7, 7);
814 imm += R_imm_11.read(ba) << 11;
815 static BitArrayRange R_imm_1(11, 8);
816 imm += R_imm_1.read(ba) << 1;
817 etiss_uint8 rs1 = 0;
818 static BitArrayRange R_rs1_0(19, 15);
819 rs1 += R_rs1_0.read(ba) << 0;
820 etiss_uint8 rs2 = 0;
821 static BitArrayRange R_rs2_0(24, 20);
822 rs2 += R_rs2_0.read(ba) << 0;
823 static BitArrayRange R_imm_5(30, 25);
824 imm += R_imm_5.read(ba) << 5;
825 static BitArrayRange R_imm_12(31, 31);
826 imm += R_imm_12.read(ba) << 12;
827 
828 // -----------------------------------------------------------------------------
829 
830  std::stringstream ss;
831 // -----------------------------------------------------------------------------
832 ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
833 // -----------------------------------------------------------------------------
834  return ss.str();
835  }
836 );
837 
838 // BLTU ------------------------------------------------------------------------
839 static InstructionDefinition bltu_imm_rs1_rs2 (
840  ISA32_RV64IMACFD,
841  "bltu",
842  (uint32_t) 0x006063,
843  (uint32_t) 0x00707f,
844  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
845  {
846 
847 // -----------------------------------------------------------------------------
848 
849 // -----------------------------------------------------------------------------
850 
851 // -----------------------------------------------------------------------------
852 etiss_uint16 imm = 0;
853 static BitArrayRange R_imm_11(7, 7);
854 imm += R_imm_11.read(ba) << 11;
855 static BitArrayRange R_imm_1(11, 8);
856 imm += R_imm_1.read(ba) << 1;
857 etiss_uint8 rs1 = 0;
858 static BitArrayRange R_rs1_0(19, 15);
859 rs1 += R_rs1_0.read(ba) << 0;
860 etiss_uint8 rs2 = 0;
861 static BitArrayRange R_rs2_0(24, 20);
862 rs2 += R_rs2_0.read(ba) << 0;
863 static BitArrayRange R_imm_5(30, 25);
864 imm += R_imm_5.read(ba) << 5;
865 static BitArrayRange R_imm_12(31, 31);
866 imm += R_imm_12.read(ba) << 12;
867 
868 // -----------------------------------------------------------------------------
869 
870  {
871  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
872 
873  cp.code() = std::string("//BLTU\n");
874 
875 // -----------------------------------------------------------------------------
876 { // block
877 cp.code() += "{ // block\n";
878 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
879 cp.code() += "} // block\n";
880 } // block
881 { // block
882 cp.code() += "{ // block\n";
883 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
884 { // block
885 cp.code() += "{ // block\n";
886 if (imm % 2ULL) { // conditional
887 { // block
888 cp.code() += "{ // block\n";
889 { // procedure
890 cp.code() += "{ // procedure\n";
891 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
892 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
893 cp.code() += "} // procedure\n";
894 } // procedure
895 cp.code() += "} // block\n";
896 } // block
897 } // conditional
898 else { // conditional
899 { // block
900 cp.code() += "{ // block\n";
901 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
902 cp.code() += "} // block\n";
903 } // block
904 } // conditional
905 cp.code() += "} // block\n";
906 } // block
907 cp.code() += "} // conditional\n";
908 cp.code() += "} // block\n";
909 } // block
910 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
911 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
912 // -----------------------------------------------------------------------------
913  cp.getAffectedRegisters().add("instructionPointer", 32);
914  }
915  {
916  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
917 
918  cp.code() = std::string("//BLTU\n");
919 
920 // -----------------------------------------------------------------------------
921 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
922 // -----------------------------------------------------------------------------
923  }
924 
925  return true;
926  },
927  0,
928  [] (BitArray & ba, Instruction & instr)
929  {
930 // -----------------------------------------------------------------------------
931 etiss_uint16 imm = 0;
932 static BitArrayRange R_imm_11(7, 7);
933 imm += R_imm_11.read(ba) << 11;
934 static BitArrayRange R_imm_1(11, 8);
935 imm += R_imm_1.read(ba) << 1;
936 etiss_uint8 rs1 = 0;
937 static BitArrayRange R_rs1_0(19, 15);
938 rs1 += R_rs1_0.read(ba) << 0;
939 etiss_uint8 rs2 = 0;
940 static BitArrayRange R_rs2_0(24, 20);
941 rs2 += R_rs2_0.read(ba) << 0;
942 static BitArrayRange R_imm_5(30, 25);
943 imm += R_imm_5.read(ba) << 5;
944 static BitArrayRange R_imm_12(31, 31);
945 imm += R_imm_12.read(ba) << 12;
946 
947 // -----------------------------------------------------------------------------
948 
949  std::stringstream ss;
950 // -----------------------------------------------------------------------------
951 ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
952 // -----------------------------------------------------------------------------
953  return ss.str();
954  }
955 );
956 
957 // BGEU ------------------------------------------------------------------------
958 static InstructionDefinition bgeu_imm_rs1_rs2 (
959  ISA32_RV64IMACFD,
960  "bgeu",
961  (uint32_t) 0x007063,
962  (uint32_t) 0x00707f,
963  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
964  {
965 
966 // -----------------------------------------------------------------------------
967 
968 // -----------------------------------------------------------------------------
969 
970 // -----------------------------------------------------------------------------
971 etiss_uint16 imm = 0;
972 static BitArrayRange R_imm_11(7, 7);
973 imm += R_imm_11.read(ba) << 11;
974 static BitArrayRange R_imm_1(11, 8);
975 imm += R_imm_1.read(ba) << 1;
976 etiss_uint8 rs1 = 0;
977 static BitArrayRange R_rs1_0(19, 15);
978 rs1 += R_rs1_0.read(ba) << 0;
979 etiss_uint8 rs2 = 0;
980 static BitArrayRange R_rs2_0(24, 20);
981 rs2 += R_rs2_0.read(ba) << 0;
982 static BitArrayRange R_imm_5(30, 25);
983 imm += R_imm_5.read(ba) << 5;
984 static BitArrayRange R_imm_12(31, 31);
985 imm += R_imm_12.read(ba) << 12;
986 
987 // -----------------------------------------------------------------------------
988 
989  {
990  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
991 
992  cp.code() = std::string("//BGEU\n");
993 
994 // -----------------------------------------------------------------------------
995 { // block
996 cp.code() += "{ // block\n";
997 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
998 cp.code() += "} // block\n";
999 } // block
1000 { // block
1001 cp.code() += "{ // block\n";
1002 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
1003 { // block
1004 cp.code() += "{ // block\n";
1005 if (imm % 2ULL) { // conditional
1006 { // block
1007 cp.code() += "{ // block\n";
1008 { // procedure
1009 cp.code() += "{ // procedure\n";
1010 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
1011 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1012 cp.code() += "} // procedure\n";
1013 } // procedure
1014 cp.code() += "} // block\n";
1015 } // block
1016 } // conditional
1017 else { // conditional
1018 { // block
1019 cp.code() += "{ // block\n";
1020 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1021 cp.code() += "} // block\n";
1022 } // block
1023 } // conditional
1024 cp.code() += "} // block\n";
1025 } // block
1026 cp.code() += "} // conditional\n";
1027 cp.code() += "} // block\n";
1028 } // block
1029 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1030 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1031 // -----------------------------------------------------------------------------
1032  cp.getAffectedRegisters().add("instructionPointer", 32);
1033  }
1034  {
1035  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1036 
1037  cp.code() = std::string("//BGEU\n");
1038 
1039 // -----------------------------------------------------------------------------
1040 cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1041 // -----------------------------------------------------------------------------
1042  }
1043 
1044  return true;
1045  },
1046  0,
1047  [] (BitArray & ba, Instruction & instr)
1048  {
1049 // -----------------------------------------------------------------------------
1050 etiss_uint16 imm = 0;
1051 static BitArrayRange R_imm_11(7, 7);
1052 imm += R_imm_11.read(ba) << 11;
1053 static BitArrayRange R_imm_1(11, 8);
1054 imm += R_imm_1.read(ba) << 1;
1055 etiss_uint8 rs1 = 0;
1056 static BitArrayRange R_rs1_0(19, 15);
1057 rs1 += R_rs1_0.read(ba) << 0;
1058 etiss_uint8 rs2 = 0;
1059 static BitArrayRange R_rs2_0(24, 20);
1060 rs2 += R_rs2_0.read(ba) << 0;
1061 static BitArrayRange R_imm_5(30, 25);
1062 imm += R_imm_5.read(ba) << 5;
1063 static BitArrayRange R_imm_12(31, 31);
1064 imm += R_imm_12.read(ba) << 12;
1065 
1066 // -----------------------------------------------------------------------------
1067 
1068  std::stringstream ss;
1069 // -----------------------------------------------------------------------------
1070 ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1071 // -----------------------------------------------------------------------------
1072  return ss.str();
1073  }
1074 );
1075 
1076 // LB --------------------------------------------------------------------------
1077 static InstructionDefinition lb_rd_rs1_imm (
1078  ISA32_RV64IMACFD,
1079  "lb",
1080  (uint32_t) 0x000003,
1081  (uint32_t) 0x00707f,
1082  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1083  {
1084 
1085 // -----------------------------------------------------------------------------
1086 
1087 // -----------------------------------------------------------------------------
1088 
1089 // -----------------------------------------------------------------------------
1090 etiss_uint8 rd = 0;
1091 static BitArrayRange R_rd_0(11, 7);
1092 rd += R_rd_0.read(ba) << 0;
1093 etiss_uint8 rs1 = 0;
1094 static BitArrayRange R_rs1_0(19, 15);
1095 rs1 += R_rs1_0.read(ba) << 0;
1096 etiss_uint16 imm = 0;
1097 static BitArrayRange R_imm_0(31, 20);
1098 imm += R_imm_0.read(ba) << 0;
1099 
1100 // -----------------------------------------------------------------------------
1101 
1102  {
1103  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1104 
1105  cp.code() = std::string("//LB\n");
1106 
1107 // -----------------------------------------------------------------------------
1108 { // block
1109 cp.code() += "{ // block\n";
1110 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1111 cp.code() += "} // block\n";
1112 } // block
1113 { // block
1114 cp.code() += "{ // block\n";
1115 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1116 cp.code() += "etiss_uint8 mem_val_0;\n";
1117 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1118 cp.code() += "if (cpu->exception) { // conditional\n";
1119 { // procedure
1120 cp.code() += "{ // procedure\n";
1121 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1122 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1123 cp.code() += "} // procedure\n";
1124 } // procedure
1125 cp.code() += "} // conditional\n";
1126 cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
1127 if ((rd % 32ULL) != 0LL) { // conditional
1128 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1129 } // conditional
1130 cp.code() += "} // block\n";
1131 } // block
1132 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1133 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1134 // -----------------------------------------------------------------------------
1135  cp.getAffectedRegisters().add("instructionPointer", 32);
1136  }
1137  {
1138  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1139 
1140  cp.code() = std::string("//LB\n");
1141 
1142 // -----------------------------------------------------------------------------
1143 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1144 // -----------------------------------------------------------------------------
1145  }
1146 
1147  return true;
1148  },
1149  0,
1150  [] (BitArray & ba, Instruction & instr)
1151  {
1152 // -----------------------------------------------------------------------------
1153 etiss_uint8 rd = 0;
1154 static BitArrayRange R_rd_0(11, 7);
1155 rd += R_rd_0.read(ba) << 0;
1156 etiss_uint8 rs1 = 0;
1157 static BitArrayRange R_rs1_0(19, 15);
1158 rs1 += R_rs1_0.read(ba) << 0;
1159 etiss_uint16 imm = 0;
1160 static BitArrayRange R_imm_0(31, 20);
1161 imm += R_imm_0.read(ba) << 0;
1162 
1163 // -----------------------------------------------------------------------------
1164 
1165  std::stringstream ss;
1166 // -----------------------------------------------------------------------------
1167 ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1168 // -----------------------------------------------------------------------------
1169  return ss.str();
1170  }
1171 );
1172 
1173 // LH --------------------------------------------------------------------------
1174 static InstructionDefinition lh_rd_rs1_imm (
1175  ISA32_RV64IMACFD,
1176  "lh",
1177  (uint32_t) 0x001003,
1178  (uint32_t) 0x00707f,
1179  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1180  {
1181 
1182 // -----------------------------------------------------------------------------
1183 
1184 // -----------------------------------------------------------------------------
1185 
1186 // -----------------------------------------------------------------------------
1187 etiss_uint8 rd = 0;
1188 static BitArrayRange R_rd_0(11, 7);
1189 rd += R_rd_0.read(ba) << 0;
1190 etiss_uint8 rs1 = 0;
1191 static BitArrayRange R_rs1_0(19, 15);
1192 rs1 += R_rs1_0.read(ba) << 0;
1193 etiss_uint16 imm = 0;
1194 static BitArrayRange R_imm_0(31, 20);
1195 imm += R_imm_0.read(ba) << 0;
1196 
1197 // -----------------------------------------------------------------------------
1198 
1199  {
1200  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1201 
1202  cp.code() = std::string("//LH\n");
1203 
1204 // -----------------------------------------------------------------------------
1205 { // block
1206 cp.code() += "{ // block\n";
1207 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1208 cp.code() += "} // block\n";
1209 } // block
1210 { // block
1211 cp.code() += "{ // block\n";
1212 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1213 cp.code() += "etiss_uint16 mem_val_0;\n";
1214 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1215 cp.code() += "if (cpu->exception) { // conditional\n";
1216 { // procedure
1217 cp.code() += "{ // procedure\n";
1218 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1219 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1220 cp.code() += "} // procedure\n";
1221 } // procedure
1222 cp.code() += "} // conditional\n";
1223 cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
1224 if ((rd % 32ULL) != 0LL) { // conditional
1225 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1226 } // conditional
1227 cp.code() += "} // block\n";
1228 } // block
1229 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1230 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1231 // -----------------------------------------------------------------------------
1232  cp.getAffectedRegisters().add("instructionPointer", 32);
1233  }
1234  {
1235  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1236 
1237  cp.code() = std::string("//LH\n");
1238 
1239 // -----------------------------------------------------------------------------
1240 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1241 // -----------------------------------------------------------------------------
1242  }
1243 
1244  return true;
1245  },
1246  0,
1247  [] (BitArray & ba, Instruction & instr)
1248  {
1249 // -----------------------------------------------------------------------------
1250 etiss_uint8 rd = 0;
1251 static BitArrayRange R_rd_0(11, 7);
1252 rd += R_rd_0.read(ba) << 0;
1253 etiss_uint8 rs1 = 0;
1254 static BitArrayRange R_rs1_0(19, 15);
1255 rs1 += R_rs1_0.read(ba) << 0;
1256 etiss_uint16 imm = 0;
1257 static BitArrayRange R_imm_0(31, 20);
1258 imm += R_imm_0.read(ba) << 0;
1259 
1260 // -----------------------------------------------------------------------------
1261 
1262  std::stringstream ss;
1263 // -----------------------------------------------------------------------------
1264 ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1265 // -----------------------------------------------------------------------------
1266  return ss.str();
1267  }
1268 );
1269 
1270 // LW --------------------------------------------------------------------------
1271 static InstructionDefinition lw_rd_rs1_imm (
1272  ISA32_RV64IMACFD,
1273  "lw",
1274  (uint32_t) 0x002003,
1275  (uint32_t) 0x00707f,
1276  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1277  {
1278 
1279 // -----------------------------------------------------------------------------
1280 
1281 // -----------------------------------------------------------------------------
1282 
1283 // -----------------------------------------------------------------------------
1284 etiss_uint8 rd = 0;
1285 static BitArrayRange R_rd_0(11, 7);
1286 rd += R_rd_0.read(ba) << 0;
1287 etiss_uint8 rs1 = 0;
1288 static BitArrayRange R_rs1_0(19, 15);
1289 rs1 += R_rs1_0.read(ba) << 0;
1290 etiss_uint16 imm = 0;
1291 static BitArrayRange R_imm_0(31, 20);
1292 imm += R_imm_0.read(ba) << 0;
1293 
1294 // -----------------------------------------------------------------------------
1295 
1296  {
1297  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1298 
1299  cp.code() = std::string("//LW\n");
1300 
1301 // -----------------------------------------------------------------------------
1302 { // block
1303 cp.code() += "{ // block\n";
1304 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1305 cp.code() += "} // block\n";
1306 } // block
1307 { // block
1308 cp.code() += "{ // block\n";
1309 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1310 cp.code() += "etiss_uint32 mem_val_0;\n";
1311 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
1312 cp.code() += "if (cpu->exception) { // conditional\n";
1313 { // procedure
1314 cp.code() += "{ // procedure\n";
1315 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1316 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1317 cp.code() += "} // procedure\n";
1318 } // procedure
1319 cp.code() += "} // conditional\n";
1320 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
1321 if ((rd % 32ULL) != 0LL) { // conditional
1322 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1323 } // conditional
1324 cp.code() += "} // block\n";
1325 } // block
1326 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1327 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1328 // -----------------------------------------------------------------------------
1329  cp.getAffectedRegisters().add("instructionPointer", 32);
1330  }
1331  {
1332  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1333 
1334  cp.code() = std::string("//LW\n");
1335 
1336 // -----------------------------------------------------------------------------
1337 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1338 // -----------------------------------------------------------------------------
1339  }
1340 
1341  return true;
1342  },
1343  0,
1344  [] (BitArray & ba, Instruction & instr)
1345  {
1346 // -----------------------------------------------------------------------------
1347 etiss_uint8 rd = 0;
1348 static BitArrayRange R_rd_0(11, 7);
1349 rd += R_rd_0.read(ba) << 0;
1350 etiss_uint8 rs1 = 0;
1351 static BitArrayRange R_rs1_0(19, 15);
1352 rs1 += R_rs1_0.read(ba) << 0;
1353 etiss_uint16 imm = 0;
1354 static BitArrayRange R_imm_0(31, 20);
1355 imm += R_imm_0.read(ba) << 0;
1356 
1357 // -----------------------------------------------------------------------------
1358 
1359  std::stringstream ss;
1360 // -----------------------------------------------------------------------------
1361 ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1362 // -----------------------------------------------------------------------------
1363  return ss.str();
1364  }
1365 );
1366 
1367 // LBU -------------------------------------------------------------------------
1368 static InstructionDefinition lbu_rd_rs1_imm (
1369  ISA32_RV64IMACFD,
1370  "lbu",
1371  (uint32_t) 0x004003,
1372  (uint32_t) 0x00707f,
1373  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1374  {
1375 
1376 // -----------------------------------------------------------------------------
1377 
1378 // -----------------------------------------------------------------------------
1379 
1380 // -----------------------------------------------------------------------------
1381 etiss_uint8 rd = 0;
1382 static BitArrayRange R_rd_0(11, 7);
1383 rd += R_rd_0.read(ba) << 0;
1384 etiss_uint8 rs1 = 0;
1385 static BitArrayRange R_rs1_0(19, 15);
1386 rs1 += R_rs1_0.read(ba) << 0;
1387 etiss_uint16 imm = 0;
1388 static BitArrayRange R_imm_0(31, 20);
1389 imm += R_imm_0.read(ba) << 0;
1390 
1391 // -----------------------------------------------------------------------------
1392 
1393  {
1394  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1395 
1396  cp.code() = std::string("//LBU\n");
1397 
1398 // -----------------------------------------------------------------------------
1399 { // block
1400 cp.code() += "{ // block\n";
1401 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1402 cp.code() += "} // block\n";
1403 } // block
1404 { // block
1405 cp.code() += "{ // block\n";
1406 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1407 cp.code() += "etiss_uint8 mem_val_0;\n";
1408 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1409 cp.code() += "if (cpu->exception) { // conditional\n";
1410 { // procedure
1411 cp.code() += "{ // procedure\n";
1412 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1413 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1414 cp.code() += "} // procedure\n";
1415 } // procedure
1416 cp.code() += "} // conditional\n";
1417 cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
1418 if ((rd % 32ULL) != 0LL) { // conditional
1419 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1420 } // conditional
1421 cp.code() += "} // block\n";
1422 } // block
1423 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1424 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1425 // -----------------------------------------------------------------------------
1426  cp.getAffectedRegisters().add("instructionPointer", 32);
1427  }
1428  {
1429  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1430 
1431  cp.code() = std::string("//LBU\n");
1432 
1433 // -----------------------------------------------------------------------------
1434 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1435 // -----------------------------------------------------------------------------
1436  }
1437 
1438  return true;
1439  },
1440  0,
1441  [] (BitArray & ba, Instruction & instr)
1442  {
1443 // -----------------------------------------------------------------------------
1444 etiss_uint8 rd = 0;
1445 static BitArrayRange R_rd_0(11, 7);
1446 rd += R_rd_0.read(ba) << 0;
1447 etiss_uint8 rs1 = 0;
1448 static BitArrayRange R_rs1_0(19, 15);
1449 rs1 += R_rs1_0.read(ba) << 0;
1450 etiss_uint16 imm = 0;
1451 static BitArrayRange R_imm_0(31, 20);
1452 imm += R_imm_0.read(ba) << 0;
1453 
1454 // -----------------------------------------------------------------------------
1455 
1456  std::stringstream ss;
1457 // -----------------------------------------------------------------------------
1458 ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1459 // -----------------------------------------------------------------------------
1460  return ss.str();
1461  }
1462 );
1463 
1464 // LHU -------------------------------------------------------------------------
1465 static InstructionDefinition lhu_rd_rs1_imm (
1466  ISA32_RV64IMACFD,
1467  "lhu",
1468  (uint32_t) 0x005003,
1469  (uint32_t) 0x00707f,
1470  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1471  {
1472 
1473 // -----------------------------------------------------------------------------
1474 
1475 // -----------------------------------------------------------------------------
1476 
1477 // -----------------------------------------------------------------------------
1478 etiss_uint8 rd = 0;
1479 static BitArrayRange R_rd_0(11, 7);
1480 rd += R_rd_0.read(ba) << 0;
1481 etiss_uint8 rs1 = 0;
1482 static BitArrayRange R_rs1_0(19, 15);
1483 rs1 += R_rs1_0.read(ba) << 0;
1484 etiss_uint16 imm = 0;
1485 static BitArrayRange R_imm_0(31, 20);
1486 imm += R_imm_0.read(ba) << 0;
1487 
1488 // -----------------------------------------------------------------------------
1489 
1490  {
1491  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1492 
1493  cp.code() = std::string("//LHU\n");
1494 
1495 // -----------------------------------------------------------------------------
1496 { // block
1497 cp.code() += "{ // block\n";
1498 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1499 cp.code() += "} // block\n";
1500 } // block
1501 { // block
1502 cp.code() += "{ // block\n";
1503 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1504 cp.code() += "etiss_uint16 mem_val_0;\n";
1505 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1506 cp.code() += "if (cpu->exception) { // conditional\n";
1507 { // procedure
1508 cp.code() += "{ // procedure\n";
1509 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1510 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1511 cp.code() += "} // procedure\n";
1512 } // procedure
1513 cp.code() += "} // conditional\n";
1514 cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
1515 if ((rd % 32ULL) != 0LL) { // conditional
1516 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
1517 } // conditional
1518 cp.code() += "} // block\n";
1519 } // block
1520 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1521 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1522 // -----------------------------------------------------------------------------
1523  cp.getAffectedRegisters().add("instructionPointer", 32);
1524  }
1525  {
1526  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1527 
1528  cp.code() = std::string("//LHU\n");
1529 
1530 // -----------------------------------------------------------------------------
1531 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1532 // -----------------------------------------------------------------------------
1533  }
1534 
1535  return true;
1536  },
1537  0,
1538  [] (BitArray & ba, Instruction & instr)
1539  {
1540 // -----------------------------------------------------------------------------
1541 etiss_uint8 rd = 0;
1542 static BitArrayRange R_rd_0(11, 7);
1543 rd += R_rd_0.read(ba) << 0;
1544 etiss_uint8 rs1 = 0;
1545 static BitArrayRange R_rs1_0(19, 15);
1546 rs1 += R_rs1_0.read(ba) << 0;
1547 etiss_uint16 imm = 0;
1548 static BitArrayRange R_imm_0(31, 20);
1549 imm += R_imm_0.read(ba) << 0;
1550 
1551 // -----------------------------------------------------------------------------
1552 
1553  std::stringstream ss;
1554 // -----------------------------------------------------------------------------
1555 ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1556 // -----------------------------------------------------------------------------
1557  return ss.str();
1558  }
1559 );
1560 
1561 // SB --------------------------------------------------------------------------
1562 static InstructionDefinition sb_imm_rs1_rs2 (
1563  ISA32_RV64IMACFD,
1564  "sb",
1565  (uint32_t) 0x000023,
1566  (uint32_t) 0x00707f,
1567  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1568  {
1569 
1570 // -----------------------------------------------------------------------------
1571 
1572 // -----------------------------------------------------------------------------
1573 
1574 // -----------------------------------------------------------------------------
1575 etiss_uint16 imm = 0;
1576 static BitArrayRange R_imm_0(11, 7);
1577 imm += R_imm_0.read(ba) << 0;
1578 etiss_uint8 rs1 = 0;
1579 static BitArrayRange R_rs1_0(19, 15);
1580 rs1 += R_rs1_0.read(ba) << 0;
1581 etiss_uint8 rs2 = 0;
1582 static BitArrayRange R_rs2_0(24, 20);
1583 rs2 += R_rs2_0.read(ba) << 0;
1584 static BitArrayRange R_imm_5(31, 25);
1585 imm += R_imm_5.read(ba) << 5;
1586 
1587 // -----------------------------------------------------------------------------
1588 
1589  {
1590  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1591 
1592  cp.code() = std::string("//SB\n");
1593 
1594 // -----------------------------------------------------------------------------
1595 { // block
1596 cp.code() += "{ // block\n";
1597 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1598 cp.code() += "} // block\n";
1599 } // block
1600 { // block
1601 cp.code() += "{ // block\n";
1602 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1603 cp.code() += "etiss_uint8 mem_val_0;\n";
1604 cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1605 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
1606 cp.code() += "if (cpu->exception) { // conditional\n";
1607 { // procedure
1608 cp.code() += "{ // procedure\n";
1609 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1610 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1611 cp.code() += "} // procedure\n";
1612 } // procedure
1613 cp.code() += "} // conditional\n";
1614 cp.code() += "} // block\n";
1615 } // block
1616 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1617 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1618 // -----------------------------------------------------------------------------
1619  cp.getAffectedRegisters().add("instructionPointer", 32);
1620  }
1621  {
1622  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1623 
1624  cp.code() = std::string("//SB\n");
1625 
1626 // -----------------------------------------------------------------------------
1627 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1628 // -----------------------------------------------------------------------------
1629  }
1630 
1631  return true;
1632  },
1633  0,
1634  [] (BitArray & ba, Instruction & instr)
1635  {
1636 // -----------------------------------------------------------------------------
1637 etiss_uint16 imm = 0;
1638 static BitArrayRange R_imm_0(11, 7);
1639 imm += R_imm_0.read(ba) << 0;
1640 etiss_uint8 rs1 = 0;
1641 static BitArrayRange R_rs1_0(19, 15);
1642 rs1 += R_rs1_0.read(ba) << 0;
1643 etiss_uint8 rs2 = 0;
1644 static BitArrayRange R_rs2_0(24, 20);
1645 rs2 += R_rs2_0.read(ba) << 0;
1646 static BitArrayRange R_imm_5(31, 25);
1647 imm += R_imm_5.read(ba) << 5;
1648 
1649 // -----------------------------------------------------------------------------
1650 
1651  std::stringstream ss;
1652 // -----------------------------------------------------------------------------
1653 ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1654 // -----------------------------------------------------------------------------
1655  return ss.str();
1656  }
1657 );
1658 
1659 // SH --------------------------------------------------------------------------
1660 static InstructionDefinition sh_imm_rs1_rs2 (
1661  ISA32_RV64IMACFD,
1662  "sh",
1663  (uint32_t) 0x001023,
1664  (uint32_t) 0x00707f,
1665  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1666  {
1667 
1668 // -----------------------------------------------------------------------------
1669 
1670 // -----------------------------------------------------------------------------
1671 
1672 // -----------------------------------------------------------------------------
1673 etiss_uint16 imm = 0;
1674 static BitArrayRange R_imm_0(11, 7);
1675 imm += R_imm_0.read(ba) << 0;
1676 etiss_uint8 rs1 = 0;
1677 static BitArrayRange R_rs1_0(19, 15);
1678 rs1 += R_rs1_0.read(ba) << 0;
1679 etiss_uint8 rs2 = 0;
1680 static BitArrayRange R_rs2_0(24, 20);
1681 rs2 += R_rs2_0.read(ba) << 0;
1682 static BitArrayRange R_imm_5(31, 25);
1683 imm += R_imm_5.read(ba) << 5;
1684 
1685 // -----------------------------------------------------------------------------
1686 
1687  {
1688  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1689 
1690  cp.code() = std::string("//SH\n");
1691 
1692 // -----------------------------------------------------------------------------
1693 { // block
1694 cp.code() += "{ // block\n";
1695 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1696 cp.code() += "} // block\n";
1697 } // block
1698 { // block
1699 cp.code() += "{ // block\n";
1700 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1701 cp.code() += "etiss_uint16 mem_val_0;\n";
1702 cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1703 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
1704 cp.code() += "if (cpu->exception) { // conditional\n";
1705 { // procedure
1706 cp.code() += "{ // procedure\n";
1707 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1708 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1709 cp.code() += "} // procedure\n";
1710 } // procedure
1711 cp.code() += "} // conditional\n";
1712 cp.code() += "} // block\n";
1713 } // block
1714 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1715 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1716 // -----------------------------------------------------------------------------
1717  cp.getAffectedRegisters().add("instructionPointer", 32);
1718  }
1719  {
1720  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1721 
1722  cp.code() = std::string("//SH\n");
1723 
1724 // -----------------------------------------------------------------------------
1725 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1726 // -----------------------------------------------------------------------------
1727  }
1728 
1729  return true;
1730  },
1731  0,
1732  [] (BitArray & ba, Instruction & instr)
1733  {
1734 // -----------------------------------------------------------------------------
1735 etiss_uint16 imm = 0;
1736 static BitArrayRange R_imm_0(11, 7);
1737 imm += R_imm_0.read(ba) << 0;
1738 etiss_uint8 rs1 = 0;
1739 static BitArrayRange R_rs1_0(19, 15);
1740 rs1 += R_rs1_0.read(ba) << 0;
1741 etiss_uint8 rs2 = 0;
1742 static BitArrayRange R_rs2_0(24, 20);
1743 rs2 += R_rs2_0.read(ba) << 0;
1744 static BitArrayRange R_imm_5(31, 25);
1745 imm += R_imm_5.read(ba) << 5;
1746 
1747 // -----------------------------------------------------------------------------
1748 
1749  std::stringstream ss;
1750 // -----------------------------------------------------------------------------
1751 ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1752 // -----------------------------------------------------------------------------
1753  return ss.str();
1754  }
1755 );
1756 
1757 // SW --------------------------------------------------------------------------
1758 static InstructionDefinition sw_imm_rs1_rs2 (
1759  ISA32_RV64IMACFD,
1760  "sw",
1761  (uint32_t) 0x002023,
1762  (uint32_t) 0x00707f,
1763  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1764  {
1765 
1766 // -----------------------------------------------------------------------------
1767 
1768 // -----------------------------------------------------------------------------
1769 
1770 // -----------------------------------------------------------------------------
1771 etiss_uint16 imm = 0;
1772 static BitArrayRange R_imm_0(11, 7);
1773 imm += R_imm_0.read(ba) << 0;
1774 etiss_uint8 rs1 = 0;
1775 static BitArrayRange R_rs1_0(19, 15);
1776 rs1 += R_rs1_0.read(ba) << 0;
1777 etiss_uint8 rs2 = 0;
1778 static BitArrayRange R_rs2_0(24, 20);
1779 rs2 += R_rs2_0.read(ba) << 0;
1780 static BitArrayRange R_imm_5(31, 25);
1781 imm += R_imm_5.read(ba) << 5;
1782 
1783 // -----------------------------------------------------------------------------
1784 
1785  {
1786  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1787 
1788  cp.code() = std::string("//SW\n");
1789 
1790 // -----------------------------------------------------------------------------
1791 { // block
1792 cp.code() += "{ // block\n";
1793 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1794 cp.code() += "} // block\n";
1795 } // block
1796 { // block
1797 cp.code() += "{ // block\n";
1798 cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1799 cp.code() += "etiss_uint32 mem_val_0;\n";
1800 cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1801 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
1802 cp.code() += "if (cpu->exception) { // conditional\n";
1803 { // procedure
1804 cp.code() += "{ // procedure\n";
1805 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1806 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1807 cp.code() += "} // procedure\n";
1808 } // procedure
1809 cp.code() += "} // conditional\n";
1810 cp.code() += "} // block\n";
1811 } // block
1812 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1813 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1814 // -----------------------------------------------------------------------------
1815  cp.getAffectedRegisters().add("instructionPointer", 32);
1816  }
1817  {
1818  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1819 
1820  cp.code() = std::string("//SW\n");
1821 
1822 // -----------------------------------------------------------------------------
1823 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1824 // -----------------------------------------------------------------------------
1825  }
1826 
1827  return true;
1828  },
1829  0,
1830  [] (BitArray & ba, Instruction & instr)
1831  {
1832 // -----------------------------------------------------------------------------
1833 etiss_uint16 imm = 0;
1834 static BitArrayRange R_imm_0(11, 7);
1835 imm += R_imm_0.read(ba) << 0;
1836 etiss_uint8 rs1 = 0;
1837 static BitArrayRange R_rs1_0(19, 15);
1838 rs1 += R_rs1_0.read(ba) << 0;
1839 etiss_uint8 rs2 = 0;
1840 static BitArrayRange R_rs2_0(24, 20);
1841 rs2 += R_rs2_0.read(ba) << 0;
1842 static BitArrayRange R_imm_5(31, 25);
1843 imm += R_imm_5.read(ba) << 5;
1844 
1845 // -----------------------------------------------------------------------------
1846 
1847  std::stringstream ss;
1848 // -----------------------------------------------------------------------------
1849 ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1850 // -----------------------------------------------------------------------------
1851  return ss.str();
1852  }
1853 );
1854 
1855 // ADDI ------------------------------------------------------------------------
1856 static InstructionDefinition addi_rd_rs1_imm (
1857  ISA32_RV64IMACFD,
1858  "addi",
1859  (uint32_t) 0x000013,
1860  (uint32_t) 0x00707f,
1861  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1862  {
1863 
1864 // -----------------------------------------------------------------------------
1865 
1866 // -----------------------------------------------------------------------------
1867 
1868 // -----------------------------------------------------------------------------
1869 etiss_uint8 rd = 0;
1870 static BitArrayRange R_rd_0(11, 7);
1871 rd += R_rd_0.read(ba) << 0;
1872 etiss_uint8 rs1 = 0;
1873 static BitArrayRange R_rs1_0(19, 15);
1874 rs1 += R_rs1_0.read(ba) << 0;
1875 etiss_uint16 imm = 0;
1876 static BitArrayRange R_imm_0(31, 20);
1877 imm += R_imm_0.read(ba) << 0;
1878 
1879 // -----------------------------------------------------------------------------
1880 
1881  {
1882  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1883 
1884  cp.code() = std::string("//ADDI\n");
1885 
1886 // -----------------------------------------------------------------------------
1887 { // block
1888 cp.code() += "{ // block\n";
1889 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1890 cp.code() += "} // block\n";
1891 } // block
1892 if ((rd % 32ULL) != 0LL) { // conditional
1893 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1894 } // conditional
1895 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1896 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1897 // -----------------------------------------------------------------------------
1898  cp.getAffectedRegisters().add("instructionPointer", 32);
1899  }
1900 
1901  return true;
1902  },
1903  0,
1904  [] (BitArray & ba, Instruction & instr)
1905  {
1906 // -----------------------------------------------------------------------------
1907 etiss_uint8 rd = 0;
1908 static BitArrayRange R_rd_0(11, 7);
1909 rd += R_rd_0.read(ba) << 0;
1910 etiss_uint8 rs1 = 0;
1911 static BitArrayRange R_rs1_0(19, 15);
1912 rs1 += R_rs1_0.read(ba) << 0;
1913 etiss_uint16 imm = 0;
1914 static BitArrayRange R_imm_0(31, 20);
1915 imm += R_imm_0.read(ba) << 0;
1916 
1917 // -----------------------------------------------------------------------------
1918 
1919  std::stringstream ss;
1920 // -----------------------------------------------------------------------------
1921 ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1922 // -----------------------------------------------------------------------------
1923  return ss.str();
1924  }
1925 );
1926 
1927 // SLTI ------------------------------------------------------------------------
1928 static InstructionDefinition slti_rd_rs1_imm (
1929  ISA32_RV64IMACFD,
1930  "slti",
1931  (uint32_t) 0x002013,
1932  (uint32_t) 0x00707f,
1933  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1934  {
1935 
1936 // -----------------------------------------------------------------------------
1937 
1938 // -----------------------------------------------------------------------------
1939 
1940 // -----------------------------------------------------------------------------
1941 etiss_uint8 rd = 0;
1942 static BitArrayRange R_rd_0(11, 7);
1943 rd += R_rd_0.read(ba) << 0;
1944 etiss_uint8 rs1 = 0;
1945 static BitArrayRange R_rs1_0(19, 15);
1946 rs1 += R_rs1_0.read(ba) << 0;
1947 etiss_uint16 imm = 0;
1948 static BitArrayRange R_imm_0(31, 20);
1949 imm += R_imm_0.read(ba) << 0;
1950 
1951 // -----------------------------------------------------------------------------
1952 
1953  {
1954  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1955 
1956  cp.code() = std::string("//SLTI\n");
1957 
1958 // -----------------------------------------------------------------------------
1959 { // block
1960 cp.code() += "{ // block\n";
1961 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1962 cp.code() += "} // block\n";
1963 } // block
1964 if ((rd % 32ULL) != 0LL) { // conditional
1965 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0LL);\n";
1966 } // conditional
1967 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1968 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1969 // -----------------------------------------------------------------------------
1970  cp.getAffectedRegisters().add("instructionPointer", 32);
1971  }
1972 
1973  return true;
1974  },
1975  0,
1976  [] (BitArray & ba, Instruction & instr)
1977  {
1978 // -----------------------------------------------------------------------------
1979 etiss_uint8 rd = 0;
1980 static BitArrayRange R_rd_0(11, 7);
1981 rd += R_rd_0.read(ba) << 0;
1982 etiss_uint8 rs1 = 0;
1983 static BitArrayRange R_rs1_0(19, 15);
1984 rs1 += R_rs1_0.read(ba) << 0;
1985 etiss_uint16 imm = 0;
1986 static BitArrayRange R_imm_0(31, 20);
1987 imm += R_imm_0.read(ba) << 0;
1988 
1989 // -----------------------------------------------------------------------------
1990 
1991  std::stringstream ss;
1992 // -----------------------------------------------------------------------------
1993 ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1994 // -----------------------------------------------------------------------------
1995  return ss.str();
1996  }
1997 );
1998 
1999 // SLTIU -----------------------------------------------------------------------
2000 static InstructionDefinition sltiu_rd_rs1_imm (
2001  ISA32_RV64IMACFD,
2002  "sltiu",
2003  (uint32_t) 0x003013,
2004  (uint32_t) 0x00707f,
2005  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2006  {
2007 
2008 // -----------------------------------------------------------------------------
2009 
2010 // -----------------------------------------------------------------------------
2011 
2012 // -----------------------------------------------------------------------------
2013 etiss_uint8 rd = 0;
2014 static BitArrayRange R_rd_0(11, 7);
2015 rd += R_rd_0.read(ba) << 0;
2016 etiss_uint8 rs1 = 0;
2017 static BitArrayRange R_rs1_0(19, 15);
2018 rs1 += R_rs1_0.read(ba) << 0;
2019 etiss_uint16 imm = 0;
2020 static BitArrayRange R_imm_0(31, 20);
2021 imm += R_imm_0.read(ba) << 0;
2022 
2023 // -----------------------------------------------------------------------------
2024 
2025  {
2026  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2027 
2028  cp.code() = std::string("//SLTIU\n");
2029 
2030 // -----------------------------------------------------------------------------
2031 { // block
2032 cp.code() += "{ // block\n";
2033 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2034 cp.code() += "} // block\n";
2035 } // block
2036 if ((rd % 32ULL) != 0LL) { // conditional
2037 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0LL);\n";
2038 } // conditional
2039 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2040 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2041 // -----------------------------------------------------------------------------
2042  cp.getAffectedRegisters().add("instructionPointer", 32);
2043  }
2044 
2045  return true;
2046  },
2047  0,
2048  [] (BitArray & ba, Instruction & instr)
2049  {
2050 // -----------------------------------------------------------------------------
2051 etiss_uint8 rd = 0;
2052 static BitArrayRange R_rd_0(11, 7);
2053 rd += R_rd_0.read(ba) << 0;
2054 etiss_uint8 rs1 = 0;
2055 static BitArrayRange R_rs1_0(19, 15);
2056 rs1 += R_rs1_0.read(ba) << 0;
2057 etiss_uint16 imm = 0;
2058 static BitArrayRange R_imm_0(31, 20);
2059 imm += R_imm_0.read(ba) << 0;
2060 
2061 // -----------------------------------------------------------------------------
2062 
2063  std::stringstream ss;
2064 // -----------------------------------------------------------------------------
2065 ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2066 // -----------------------------------------------------------------------------
2067  return ss.str();
2068  }
2069 );
2070 
2071 // XORI ------------------------------------------------------------------------
2072 static InstructionDefinition xori_rd_rs1_imm (
2073  ISA32_RV64IMACFD,
2074  "xori",
2075  (uint32_t) 0x004013,
2076  (uint32_t) 0x00707f,
2077  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2078  {
2079 
2080 // -----------------------------------------------------------------------------
2081 
2082 // -----------------------------------------------------------------------------
2083 
2084 // -----------------------------------------------------------------------------
2085 etiss_uint8 rd = 0;
2086 static BitArrayRange R_rd_0(11, 7);
2087 rd += R_rd_0.read(ba) << 0;
2088 etiss_uint8 rs1 = 0;
2089 static BitArrayRange R_rs1_0(19, 15);
2090 rs1 += R_rs1_0.read(ba) << 0;
2091 etiss_uint16 imm = 0;
2092 static BitArrayRange R_imm_0(31, 20);
2093 imm += R_imm_0.read(ba) << 0;
2094 
2095 // -----------------------------------------------------------------------------
2096 
2097  {
2098  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2099 
2100  cp.code() = std::string("//XORI\n");
2101 
2102 // -----------------------------------------------------------------------------
2103 { // block
2104 cp.code() += "{ // block\n";
2105 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2106 cp.code() += "} // block\n";
2107 } // block
2108 if ((rd % 32ULL) != 0LL) { // conditional
2109 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2110 } // conditional
2111 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2112 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2113 // -----------------------------------------------------------------------------
2114  cp.getAffectedRegisters().add("instructionPointer", 32);
2115  }
2116 
2117  return true;
2118  },
2119  0,
2120  [] (BitArray & ba, Instruction & instr)
2121  {
2122 // -----------------------------------------------------------------------------
2123 etiss_uint8 rd = 0;
2124 static BitArrayRange R_rd_0(11, 7);
2125 rd += R_rd_0.read(ba) << 0;
2126 etiss_uint8 rs1 = 0;
2127 static BitArrayRange R_rs1_0(19, 15);
2128 rs1 += R_rs1_0.read(ba) << 0;
2129 etiss_uint16 imm = 0;
2130 static BitArrayRange R_imm_0(31, 20);
2131 imm += R_imm_0.read(ba) << 0;
2132 
2133 // -----------------------------------------------------------------------------
2134 
2135  std::stringstream ss;
2136 // -----------------------------------------------------------------------------
2137 ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2138 // -----------------------------------------------------------------------------
2139  return ss.str();
2140  }
2141 );
2142 
2143 // ORI -------------------------------------------------------------------------
2144 static InstructionDefinition ori_rd_rs1_imm (
2145  ISA32_RV64IMACFD,
2146  "ori",
2147  (uint32_t) 0x006013,
2148  (uint32_t) 0x00707f,
2149  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2150  {
2151 
2152 // -----------------------------------------------------------------------------
2153 
2154 // -----------------------------------------------------------------------------
2155 
2156 // -----------------------------------------------------------------------------
2157 etiss_uint8 rd = 0;
2158 static BitArrayRange R_rd_0(11, 7);
2159 rd += R_rd_0.read(ba) << 0;
2160 etiss_uint8 rs1 = 0;
2161 static BitArrayRange R_rs1_0(19, 15);
2162 rs1 += R_rs1_0.read(ba) << 0;
2163 etiss_uint16 imm = 0;
2164 static BitArrayRange R_imm_0(31, 20);
2165 imm += R_imm_0.read(ba) << 0;
2166 
2167 // -----------------------------------------------------------------------------
2168 
2169  {
2170  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2171 
2172  cp.code() = std::string("//ORI\n");
2173 
2174 // -----------------------------------------------------------------------------
2175 { // block
2176 cp.code() += "{ // block\n";
2177 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2178 cp.code() += "} // block\n";
2179 } // block
2180 if ((rd % 32ULL) != 0LL) { // conditional
2181 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2182 } // conditional
2183 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2184 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2185 // -----------------------------------------------------------------------------
2186  cp.getAffectedRegisters().add("instructionPointer", 32);
2187  }
2188 
2189  return true;
2190  },
2191  0,
2192  [] (BitArray & ba, Instruction & instr)
2193  {
2194 // -----------------------------------------------------------------------------
2195 etiss_uint8 rd = 0;
2196 static BitArrayRange R_rd_0(11, 7);
2197 rd += R_rd_0.read(ba) << 0;
2198 etiss_uint8 rs1 = 0;
2199 static BitArrayRange R_rs1_0(19, 15);
2200 rs1 += R_rs1_0.read(ba) << 0;
2201 etiss_uint16 imm = 0;
2202 static BitArrayRange R_imm_0(31, 20);
2203 imm += R_imm_0.read(ba) << 0;
2204 
2205 // -----------------------------------------------------------------------------
2206 
2207  std::stringstream ss;
2208 // -----------------------------------------------------------------------------
2209 ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2210 // -----------------------------------------------------------------------------
2211  return ss.str();
2212  }
2213 );
2214 
2215 // ANDI ------------------------------------------------------------------------
2216 static InstructionDefinition andi_rd_rs1_imm (
2217  ISA32_RV64IMACFD,
2218  "andi",
2219  (uint32_t) 0x007013,
2220  (uint32_t) 0x00707f,
2221  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2222  {
2223 
2224 // -----------------------------------------------------------------------------
2225 
2226 // -----------------------------------------------------------------------------
2227 
2228 // -----------------------------------------------------------------------------
2229 etiss_uint8 rd = 0;
2230 static BitArrayRange R_rd_0(11, 7);
2231 rd += R_rd_0.read(ba) << 0;
2232 etiss_uint8 rs1 = 0;
2233 static BitArrayRange R_rs1_0(19, 15);
2234 rs1 += R_rs1_0.read(ba) << 0;
2235 etiss_uint16 imm = 0;
2236 static BitArrayRange R_imm_0(31, 20);
2237 imm += R_imm_0.read(ba) << 0;
2238 
2239 // -----------------------------------------------------------------------------
2240 
2241  {
2242  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2243 
2244  cp.code() = std::string("//ANDI\n");
2245 
2246 // -----------------------------------------------------------------------------
2247 { // block
2248 cp.code() += "{ // block\n";
2249 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2250 cp.code() += "} // block\n";
2251 } // block
2252 if ((rd % 32ULL) != 0LL) { // conditional
2253 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2254 } // conditional
2255 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2256 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2257 // -----------------------------------------------------------------------------
2258  cp.getAffectedRegisters().add("instructionPointer", 32);
2259  }
2260 
2261  return true;
2262  },
2263  0,
2264  [] (BitArray & ba, Instruction & instr)
2265  {
2266 // -----------------------------------------------------------------------------
2267 etiss_uint8 rd = 0;
2268 static BitArrayRange R_rd_0(11, 7);
2269 rd += R_rd_0.read(ba) << 0;
2270 etiss_uint8 rs1 = 0;
2271 static BitArrayRange R_rs1_0(19, 15);
2272 rs1 += R_rs1_0.read(ba) << 0;
2273 etiss_uint16 imm = 0;
2274 static BitArrayRange R_imm_0(31, 20);
2275 imm += R_imm_0.read(ba) << 0;
2276 
2277 // -----------------------------------------------------------------------------
2278 
2279  std::stringstream ss;
2280 // -----------------------------------------------------------------------------
2281 ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2282 // -----------------------------------------------------------------------------
2283  return ss.str();
2284  }
2285 );
2286 
2287 // SLLI ------------------------------------------------------------------------
2288 static InstructionDefinition slli_rd_rs1_shamt (
2289  ISA32_RV64IMACFD,
2290  "slli",
2291  (uint32_t) 0x001013,
2292  (uint32_t) 0xfe00707f,
2293  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2294  {
2295 
2296 // -----------------------------------------------------------------------------
2297 
2298 // -----------------------------------------------------------------------------
2299 
2300 // -----------------------------------------------------------------------------
2301 etiss_uint8 rd = 0;
2302 static BitArrayRange R_rd_0(11, 7);
2303 rd += R_rd_0.read(ba) << 0;
2304 etiss_uint8 rs1 = 0;
2305 static BitArrayRange R_rs1_0(19, 15);
2306 rs1 += R_rs1_0.read(ba) << 0;
2307 etiss_uint8 shamt = 0;
2308 static BitArrayRange R_shamt_0(24, 20);
2309 shamt += R_shamt_0.read(ba) << 0;
2310 
2311 // -----------------------------------------------------------------------------
2312 
2313  {
2314  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2315 
2316  cp.code() = std::string("//SLLI\n");
2317 
2318 // -----------------------------------------------------------------------------
2319 { // block
2320 cp.code() += "{ // block\n";
2321 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2322 cp.code() += "} // block\n";
2323 } // block
2324 if ((rd % 32ULL) != 0LL) { // conditional
2325 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
2326 } // conditional
2327 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2328 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2329 // -----------------------------------------------------------------------------
2330  cp.getAffectedRegisters().add("instructionPointer", 32);
2331  }
2332 
2333  return true;
2334  },
2335  0,
2336  [] (BitArray & ba, Instruction & instr)
2337  {
2338 // -----------------------------------------------------------------------------
2339 etiss_uint8 rd = 0;
2340 static BitArrayRange R_rd_0(11, 7);
2341 rd += R_rd_0.read(ba) << 0;
2342 etiss_uint8 rs1 = 0;
2343 static BitArrayRange R_rs1_0(19, 15);
2344 rs1 += R_rs1_0.read(ba) << 0;
2345 etiss_uint8 shamt = 0;
2346 static BitArrayRange R_shamt_0(24, 20);
2347 shamt += R_shamt_0.read(ba) << 0;
2348 
2349 // -----------------------------------------------------------------------------
2350 
2351  std::stringstream ss;
2352 // -----------------------------------------------------------------------------
2353 ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2354 // -----------------------------------------------------------------------------
2355  return ss.str();
2356  }
2357 );
2358 
2359 // SRLI ------------------------------------------------------------------------
2360 static InstructionDefinition srli_rd_rs1_shamt (
2361  ISA32_RV64IMACFD,
2362  "srli",
2363  (uint32_t) 0x005013,
2364  (uint32_t) 0xfe00707f,
2365  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2366  {
2367 
2368 // -----------------------------------------------------------------------------
2369 
2370 // -----------------------------------------------------------------------------
2371 
2372 // -----------------------------------------------------------------------------
2373 etiss_uint8 rd = 0;
2374 static BitArrayRange R_rd_0(11, 7);
2375 rd += R_rd_0.read(ba) << 0;
2376 etiss_uint8 rs1 = 0;
2377 static BitArrayRange R_rs1_0(19, 15);
2378 rs1 += R_rs1_0.read(ba) << 0;
2379 etiss_uint8 shamt = 0;
2380 static BitArrayRange R_shamt_0(24, 20);
2381 shamt += R_shamt_0.read(ba) << 0;
2382 
2383 // -----------------------------------------------------------------------------
2384 
2385  {
2386  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2387 
2388  cp.code() = std::string("//SRLI\n");
2389 
2390 // -----------------------------------------------------------------------------
2391 { // block
2392 cp.code() += "{ // block\n";
2393 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2394 cp.code() += "} // block\n";
2395 } // block
2396 if ((rd % 32ULL) != 0LL) { // conditional
2397 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
2398 } // conditional
2399 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2400 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2401 // -----------------------------------------------------------------------------
2402  cp.getAffectedRegisters().add("instructionPointer", 32);
2403  }
2404 
2405  return true;
2406  },
2407  0,
2408  [] (BitArray & ba, Instruction & instr)
2409  {
2410 // -----------------------------------------------------------------------------
2411 etiss_uint8 rd = 0;
2412 static BitArrayRange R_rd_0(11, 7);
2413 rd += R_rd_0.read(ba) << 0;
2414 etiss_uint8 rs1 = 0;
2415 static BitArrayRange R_rs1_0(19, 15);
2416 rs1 += R_rs1_0.read(ba) << 0;
2417 etiss_uint8 shamt = 0;
2418 static BitArrayRange R_shamt_0(24, 20);
2419 shamt += R_shamt_0.read(ba) << 0;
2420 
2421 // -----------------------------------------------------------------------------
2422 
2423  std::stringstream ss;
2424 // -----------------------------------------------------------------------------
2425 ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2426 // -----------------------------------------------------------------------------
2427  return ss.str();
2428  }
2429 );
2430 
2431 // SRAI ------------------------------------------------------------------------
2432 static InstructionDefinition srai_rd_rs1_shamt (
2433  ISA32_RV64IMACFD,
2434  "srai",
2435  (uint32_t) 0x40005013,
2436  (uint32_t) 0xfe00707f,
2437  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2438  {
2439 
2440 // -----------------------------------------------------------------------------
2441 
2442 // -----------------------------------------------------------------------------
2443 
2444 // -----------------------------------------------------------------------------
2445 etiss_uint8 rd = 0;
2446 static BitArrayRange R_rd_0(11, 7);
2447 rd += R_rd_0.read(ba) << 0;
2448 etiss_uint8 rs1 = 0;
2449 static BitArrayRange R_rs1_0(19, 15);
2450 rs1 += R_rs1_0.read(ba) << 0;
2451 etiss_uint8 shamt = 0;
2452 static BitArrayRange R_shamt_0(24, 20);
2453 shamt += R_shamt_0.read(ba) << 0;
2454 
2455 // -----------------------------------------------------------------------------
2456 
2457  {
2458  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2459 
2460  cp.code() = std::string("//SRAI\n");
2461 
2462 // -----------------------------------------------------------------------------
2463 { // block
2464 cp.code() += "{ // block\n";
2465 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2466 cp.code() += "} // block\n";
2467 } // block
2468 if ((rd % 32ULL) != 0LL) { // conditional
2469 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
2470 } // conditional
2471 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2472 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2473 // -----------------------------------------------------------------------------
2474  cp.getAffectedRegisters().add("instructionPointer", 32);
2475  }
2476 
2477  return true;
2478  },
2479  0,
2480  [] (BitArray & ba, Instruction & instr)
2481  {
2482 // -----------------------------------------------------------------------------
2483 etiss_uint8 rd = 0;
2484 static BitArrayRange R_rd_0(11, 7);
2485 rd += R_rd_0.read(ba) << 0;
2486 etiss_uint8 rs1 = 0;
2487 static BitArrayRange R_rs1_0(19, 15);
2488 rs1 += R_rs1_0.read(ba) << 0;
2489 etiss_uint8 shamt = 0;
2490 static BitArrayRange R_shamt_0(24, 20);
2491 shamt += R_shamt_0.read(ba) << 0;
2492 
2493 // -----------------------------------------------------------------------------
2494 
2495  std::stringstream ss;
2496 // -----------------------------------------------------------------------------
2497 ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2498 // -----------------------------------------------------------------------------
2499  return ss.str();
2500  }
2501 );
2502 
2503 // ADD -------------------------------------------------------------------------
2504 static InstructionDefinition add_rd_rs1_rs2 (
2505  ISA32_RV64IMACFD,
2506  "add",
2507  (uint32_t) 0x000033,
2508  (uint32_t) 0xfe00707f,
2509  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2510  {
2511 
2512 // -----------------------------------------------------------------------------
2513 
2514 // -----------------------------------------------------------------------------
2515 
2516 // -----------------------------------------------------------------------------
2517 etiss_uint8 rd = 0;
2518 static BitArrayRange R_rd_0(11, 7);
2519 rd += R_rd_0.read(ba) << 0;
2520 etiss_uint8 rs1 = 0;
2521 static BitArrayRange R_rs1_0(19, 15);
2522 rs1 += R_rs1_0.read(ba) << 0;
2523 etiss_uint8 rs2 = 0;
2524 static BitArrayRange R_rs2_0(24, 20);
2525 rs2 += R_rs2_0.read(ba) << 0;
2526 
2527 // -----------------------------------------------------------------------------
2528 
2529  {
2530  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2531 
2532  cp.code() = std::string("//ADD\n");
2533 
2534 // -----------------------------------------------------------------------------
2535 { // block
2536 cp.code() += "{ // block\n";
2537 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2538 cp.code() += "} // block\n";
2539 } // block
2540 if ((rd % 32ULL) != 0LL) { // conditional
2541 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2542 } // conditional
2543 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2544 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2545 // -----------------------------------------------------------------------------
2546  cp.getAffectedRegisters().add("instructionPointer", 32);
2547  }
2548 
2549  return true;
2550  },
2551  0,
2552  [] (BitArray & ba, Instruction & instr)
2553  {
2554 // -----------------------------------------------------------------------------
2555 etiss_uint8 rd = 0;
2556 static BitArrayRange R_rd_0(11, 7);
2557 rd += R_rd_0.read(ba) << 0;
2558 etiss_uint8 rs1 = 0;
2559 static BitArrayRange R_rs1_0(19, 15);
2560 rs1 += R_rs1_0.read(ba) << 0;
2561 etiss_uint8 rs2 = 0;
2562 static BitArrayRange R_rs2_0(24, 20);
2563 rs2 += R_rs2_0.read(ba) << 0;
2564 
2565 // -----------------------------------------------------------------------------
2566 
2567  std::stringstream ss;
2568 // -----------------------------------------------------------------------------
2569 ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2570 // -----------------------------------------------------------------------------
2571  return ss.str();
2572  }
2573 );
2574 
2575 // SUB -------------------------------------------------------------------------
2576 static InstructionDefinition sub_rd_rs1_rs2 (
2577  ISA32_RV64IMACFD,
2578  "sub",
2579  (uint32_t) 0x40000033,
2580  (uint32_t) 0xfe00707f,
2581  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2582  {
2583 
2584 // -----------------------------------------------------------------------------
2585 
2586 // -----------------------------------------------------------------------------
2587 
2588 // -----------------------------------------------------------------------------
2589 etiss_uint8 rd = 0;
2590 static BitArrayRange R_rd_0(11, 7);
2591 rd += R_rd_0.read(ba) << 0;
2592 etiss_uint8 rs1 = 0;
2593 static BitArrayRange R_rs1_0(19, 15);
2594 rs1 += R_rs1_0.read(ba) << 0;
2595 etiss_uint8 rs2 = 0;
2596 static BitArrayRange R_rs2_0(24, 20);
2597 rs2 += R_rs2_0.read(ba) << 0;
2598 
2599 // -----------------------------------------------------------------------------
2600 
2601  {
2602  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2603 
2604  cp.code() = std::string("//SUB\n");
2605 
2606 // -----------------------------------------------------------------------------
2607 { // block
2608 cp.code() += "{ // block\n";
2609 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2610 cp.code() += "} // block\n";
2611 } // block
2612 if ((rd % 32ULL) != 0LL) { // conditional
2613 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2614 } // conditional
2615 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2616 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2617 // -----------------------------------------------------------------------------
2618  cp.getAffectedRegisters().add("instructionPointer", 32);
2619  }
2620 
2621  return true;
2622  },
2623  0,
2624  [] (BitArray & ba, Instruction & instr)
2625  {
2626 // -----------------------------------------------------------------------------
2627 etiss_uint8 rd = 0;
2628 static BitArrayRange R_rd_0(11, 7);
2629 rd += R_rd_0.read(ba) << 0;
2630 etiss_uint8 rs1 = 0;
2631 static BitArrayRange R_rs1_0(19, 15);
2632 rs1 += R_rs1_0.read(ba) << 0;
2633 etiss_uint8 rs2 = 0;
2634 static BitArrayRange R_rs2_0(24, 20);
2635 rs2 += R_rs2_0.read(ba) << 0;
2636 
2637 // -----------------------------------------------------------------------------
2638 
2639  std::stringstream ss;
2640 // -----------------------------------------------------------------------------
2641 ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2642 // -----------------------------------------------------------------------------
2643  return ss.str();
2644  }
2645 );
2646 
2647 // SLL -------------------------------------------------------------------------
2648 static InstructionDefinition sll_rd_rs1_rs2 (
2649  ISA32_RV64IMACFD,
2650  "sll",
2651  (uint32_t) 0x001033,
2652  (uint32_t) 0xfe00707f,
2653  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2654  {
2655 
2656 // -----------------------------------------------------------------------------
2657 
2658 // -----------------------------------------------------------------------------
2659 
2660 // -----------------------------------------------------------------------------
2661 etiss_uint8 rd = 0;
2662 static BitArrayRange R_rd_0(11, 7);
2663 rd += R_rd_0.read(ba) << 0;
2664 etiss_uint8 rs1 = 0;
2665 static BitArrayRange R_rs1_0(19, 15);
2666 rs1 += R_rs1_0.read(ba) << 0;
2667 etiss_uint8 rs2 = 0;
2668 static BitArrayRange R_rs2_0(24, 20);
2669 rs2 += R_rs2_0.read(ba) << 0;
2670 
2671 // -----------------------------------------------------------------------------
2672 
2673  {
2674  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2675 
2676  cp.code() = std::string("//SLL\n");
2677 
2678 // -----------------------------------------------------------------------------
2679 { // block
2680 cp.code() += "{ // block\n";
2681 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2682 cp.code() += "} // block\n";
2683 } // block
2684 if ((rd % 32ULL) != 0LL) { // conditional
2685 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
2686 } // conditional
2687 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2688 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2689 // -----------------------------------------------------------------------------
2690  cp.getAffectedRegisters().add("instructionPointer", 32);
2691  }
2692 
2693  return true;
2694  },
2695  0,
2696  [] (BitArray & ba, Instruction & instr)
2697  {
2698 // -----------------------------------------------------------------------------
2699 etiss_uint8 rd = 0;
2700 static BitArrayRange R_rd_0(11, 7);
2701 rd += R_rd_0.read(ba) << 0;
2702 etiss_uint8 rs1 = 0;
2703 static BitArrayRange R_rs1_0(19, 15);
2704 rs1 += R_rs1_0.read(ba) << 0;
2705 etiss_uint8 rs2 = 0;
2706 static BitArrayRange R_rs2_0(24, 20);
2707 rs2 += R_rs2_0.read(ba) << 0;
2708 
2709 // -----------------------------------------------------------------------------
2710 
2711  std::stringstream ss;
2712 // -----------------------------------------------------------------------------
2713 ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2714 // -----------------------------------------------------------------------------
2715  return ss.str();
2716  }
2717 );
2718 
2719 // SLT -------------------------------------------------------------------------
2720 static InstructionDefinition slt_rd_rs1_rs2 (
2721  ISA32_RV64IMACFD,
2722  "slt",
2723  (uint32_t) 0x002033,
2724  (uint32_t) 0xfe00707f,
2725  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2726  {
2727 
2728 // -----------------------------------------------------------------------------
2729 
2730 // -----------------------------------------------------------------------------
2731 
2732 // -----------------------------------------------------------------------------
2733 etiss_uint8 rd = 0;
2734 static BitArrayRange R_rd_0(11, 7);
2735 rd += R_rd_0.read(ba) << 0;
2736 etiss_uint8 rs1 = 0;
2737 static BitArrayRange R_rs1_0(19, 15);
2738 rs1 += R_rs1_0.read(ba) << 0;
2739 etiss_uint8 rs2 = 0;
2740 static BitArrayRange R_rs2_0(24, 20);
2741 rs2 += R_rs2_0.read(ba) << 0;
2742 
2743 // -----------------------------------------------------------------------------
2744 
2745  {
2746  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2747 
2748  cp.code() = std::string("//SLT\n");
2749 
2750 // -----------------------------------------------------------------------------
2751 { // block
2752 cp.code() += "{ // block\n";
2753 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2754 cp.code() += "} // block\n";
2755 } // block
2756 if ((rd % 32ULL) != 0LL) { // conditional
2757 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0LL);\n";
2758 } // conditional
2759 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2760 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2761 // -----------------------------------------------------------------------------
2762  cp.getAffectedRegisters().add("instructionPointer", 32);
2763  }
2764 
2765  return true;
2766  },
2767  0,
2768  [] (BitArray & ba, Instruction & instr)
2769  {
2770 // -----------------------------------------------------------------------------
2771 etiss_uint8 rd = 0;
2772 static BitArrayRange R_rd_0(11, 7);
2773 rd += R_rd_0.read(ba) << 0;
2774 etiss_uint8 rs1 = 0;
2775 static BitArrayRange R_rs1_0(19, 15);
2776 rs1 += R_rs1_0.read(ba) << 0;
2777 etiss_uint8 rs2 = 0;
2778 static BitArrayRange R_rs2_0(24, 20);
2779 rs2 += R_rs2_0.read(ba) << 0;
2780 
2781 // -----------------------------------------------------------------------------
2782 
2783  std::stringstream ss;
2784 // -----------------------------------------------------------------------------
2785 ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2786 // -----------------------------------------------------------------------------
2787  return ss.str();
2788  }
2789 );
2790 
2791 // SLTU ------------------------------------------------------------------------
2792 static InstructionDefinition sltu_rd_rs1_rs2 (
2793  ISA32_RV64IMACFD,
2794  "sltu",
2795  (uint32_t) 0x003033,
2796  (uint32_t) 0xfe00707f,
2797  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2798  {
2799 
2800 // -----------------------------------------------------------------------------
2801 
2802 // -----------------------------------------------------------------------------
2803 
2804 // -----------------------------------------------------------------------------
2805 etiss_uint8 rd = 0;
2806 static BitArrayRange R_rd_0(11, 7);
2807 rd += R_rd_0.read(ba) << 0;
2808 etiss_uint8 rs1 = 0;
2809 static BitArrayRange R_rs1_0(19, 15);
2810 rs1 += R_rs1_0.read(ba) << 0;
2811 etiss_uint8 rs2 = 0;
2812 static BitArrayRange R_rs2_0(24, 20);
2813 rs2 += R_rs2_0.read(ba) << 0;
2814 
2815 // -----------------------------------------------------------------------------
2816 
2817  {
2818  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2819 
2820  cp.code() = std::string("//SLTU\n");
2821 
2822 // -----------------------------------------------------------------------------
2823 { // block
2824 cp.code() += "{ // block\n";
2825 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2826 cp.code() += "} // block\n";
2827 } // block
2828 if ((rd % 32ULL) != 0LL) { // conditional
2829 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0LL);\n";
2830 } // conditional
2831 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2832 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2833 // -----------------------------------------------------------------------------
2834  cp.getAffectedRegisters().add("instructionPointer", 32);
2835  }
2836 
2837  return true;
2838  },
2839  0,
2840  [] (BitArray & ba, Instruction & instr)
2841  {
2842 // -----------------------------------------------------------------------------
2843 etiss_uint8 rd = 0;
2844 static BitArrayRange R_rd_0(11, 7);
2845 rd += R_rd_0.read(ba) << 0;
2846 etiss_uint8 rs1 = 0;
2847 static BitArrayRange R_rs1_0(19, 15);
2848 rs1 += R_rs1_0.read(ba) << 0;
2849 etiss_uint8 rs2 = 0;
2850 static BitArrayRange R_rs2_0(24, 20);
2851 rs2 += R_rs2_0.read(ba) << 0;
2852 
2853 // -----------------------------------------------------------------------------
2854 
2855  std::stringstream ss;
2856 // -----------------------------------------------------------------------------
2857 ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2858 // -----------------------------------------------------------------------------
2859  return ss.str();
2860  }
2861 );
2862 
2863 // XOR -------------------------------------------------------------------------
2864 static InstructionDefinition xor_rd_rs1_rs2 (
2865  ISA32_RV64IMACFD,
2866  "xor",
2867  (uint32_t) 0x004033,
2868  (uint32_t) 0xfe00707f,
2869  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2870  {
2871 
2872 // -----------------------------------------------------------------------------
2873 
2874 // -----------------------------------------------------------------------------
2875 
2876 // -----------------------------------------------------------------------------
2877 etiss_uint8 rd = 0;
2878 static BitArrayRange R_rd_0(11, 7);
2879 rd += R_rd_0.read(ba) << 0;
2880 etiss_uint8 rs1 = 0;
2881 static BitArrayRange R_rs1_0(19, 15);
2882 rs1 += R_rs1_0.read(ba) << 0;
2883 etiss_uint8 rs2 = 0;
2884 static BitArrayRange R_rs2_0(24, 20);
2885 rs2 += R_rs2_0.read(ba) << 0;
2886 
2887 // -----------------------------------------------------------------------------
2888 
2889  {
2890  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2891 
2892  cp.code() = std::string("//XOR\n");
2893 
2894 // -----------------------------------------------------------------------------
2895 { // block
2896 cp.code() += "{ // block\n";
2897 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2898 cp.code() += "} // block\n";
2899 } // block
2900 if ((rd % 32ULL) != 0LL) { // conditional
2901 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2902 } // conditional
2903 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2904 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2905 // -----------------------------------------------------------------------------
2906  cp.getAffectedRegisters().add("instructionPointer", 32);
2907  }
2908 
2909  return true;
2910  },
2911  0,
2912  [] (BitArray & ba, Instruction & instr)
2913  {
2914 // -----------------------------------------------------------------------------
2915 etiss_uint8 rd = 0;
2916 static BitArrayRange R_rd_0(11, 7);
2917 rd += R_rd_0.read(ba) << 0;
2918 etiss_uint8 rs1 = 0;
2919 static BitArrayRange R_rs1_0(19, 15);
2920 rs1 += R_rs1_0.read(ba) << 0;
2921 etiss_uint8 rs2 = 0;
2922 static BitArrayRange R_rs2_0(24, 20);
2923 rs2 += R_rs2_0.read(ba) << 0;
2924 
2925 // -----------------------------------------------------------------------------
2926 
2927  std::stringstream ss;
2928 // -----------------------------------------------------------------------------
2929 ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2930 // -----------------------------------------------------------------------------
2931  return ss.str();
2932  }
2933 );
2934 
2935 // SRL -------------------------------------------------------------------------
2936 static InstructionDefinition srl_rd_rs1_rs2 (
2937  ISA32_RV64IMACFD,
2938  "srl",
2939  (uint32_t) 0x005033,
2940  (uint32_t) 0xfe00707f,
2941  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2942  {
2943 
2944 // -----------------------------------------------------------------------------
2945 
2946 // -----------------------------------------------------------------------------
2947 
2948 // -----------------------------------------------------------------------------
2949 etiss_uint8 rd = 0;
2950 static BitArrayRange R_rd_0(11, 7);
2951 rd += R_rd_0.read(ba) << 0;
2952 etiss_uint8 rs1 = 0;
2953 static BitArrayRange R_rs1_0(19, 15);
2954 rs1 += R_rs1_0.read(ba) << 0;
2955 etiss_uint8 rs2 = 0;
2956 static BitArrayRange R_rs2_0(24, 20);
2957 rs2 += R_rs2_0.read(ba) << 0;
2958 
2959 // -----------------------------------------------------------------------------
2960 
2961  {
2962  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2963 
2964  cp.code() = std::string("//SRL\n");
2965 
2966 // -----------------------------------------------------------------------------
2967 { // block
2968 cp.code() += "{ // block\n";
2969 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2970 cp.code() += "} // block\n";
2971 } // block
2972 if ((rd % 32ULL) != 0LL) { // conditional
2973 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
2974 } // conditional
2975 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2976 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2977 // -----------------------------------------------------------------------------
2978  cp.getAffectedRegisters().add("instructionPointer", 32);
2979  }
2980 
2981  return true;
2982  },
2983  0,
2984  [] (BitArray & ba, Instruction & instr)
2985  {
2986 // -----------------------------------------------------------------------------
2987 etiss_uint8 rd = 0;
2988 static BitArrayRange R_rd_0(11, 7);
2989 rd += R_rd_0.read(ba) << 0;
2990 etiss_uint8 rs1 = 0;
2991 static BitArrayRange R_rs1_0(19, 15);
2992 rs1 += R_rs1_0.read(ba) << 0;
2993 etiss_uint8 rs2 = 0;
2994 static BitArrayRange R_rs2_0(24, 20);
2995 rs2 += R_rs2_0.read(ba) << 0;
2996 
2997 // -----------------------------------------------------------------------------
2998 
2999  std::stringstream ss;
3000 // -----------------------------------------------------------------------------
3001 ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3002 // -----------------------------------------------------------------------------
3003  return ss.str();
3004  }
3005 );
3006 
3007 // SRA -------------------------------------------------------------------------
3008 static InstructionDefinition sra_rd_rs1_rs2 (
3009  ISA32_RV64IMACFD,
3010  "sra",
3011  (uint32_t) 0x40005033,
3012  (uint32_t) 0xfe00707f,
3013  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3014  {
3015 
3016 // -----------------------------------------------------------------------------
3017 
3018 // -----------------------------------------------------------------------------
3019 
3020 // -----------------------------------------------------------------------------
3021 etiss_uint8 rd = 0;
3022 static BitArrayRange R_rd_0(11, 7);
3023 rd += R_rd_0.read(ba) << 0;
3024 etiss_uint8 rs1 = 0;
3025 static BitArrayRange R_rs1_0(19, 15);
3026 rs1 += R_rs1_0.read(ba) << 0;
3027 etiss_uint8 rs2 = 0;
3028 static BitArrayRange R_rs2_0(24, 20);
3029 rs2 += R_rs2_0.read(ba) << 0;
3030 
3031 // -----------------------------------------------------------------------------
3032 
3033  {
3034  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3035 
3036  cp.code() = std::string("//SRA\n");
3037 
3038 // -----------------------------------------------------------------------------
3039 { // block
3040 cp.code() += "{ // block\n";
3041 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3042 cp.code() += "} // block\n";
3043 } // block
3044 if ((rd % 32ULL) != 0LL) { // conditional
3045 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n";
3046 } // conditional
3047 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3048 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3049 // -----------------------------------------------------------------------------
3050  cp.getAffectedRegisters().add("instructionPointer", 32);
3051  }
3052 
3053  return true;
3054  },
3055  0,
3056  [] (BitArray & ba, Instruction & instr)
3057  {
3058 // -----------------------------------------------------------------------------
3059 etiss_uint8 rd = 0;
3060 static BitArrayRange R_rd_0(11, 7);
3061 rd += R_rd_0.read(ba) << 0;
3062 etiss_uint8 rs1 = 0;
3063 static BitArrayRange R_rs1_0(19, 15);
3064 rs1 += R_rs1_0.read(ba) << 0;
3065 etiss_uint8 rs2 = 0;
3066 static BitArrayRange R_rs2_0(24, 20);
3067 rs2 += R_rs2_0.read(ba) << 0;
3068 
3069 // -----------------------------------------------------------------------------
3070 
3071  std::stringstream ss;
3072 // -----------------------------------------------------------------------------
3073 ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3074 // -----------------------------------------------------------------------------
3075  return ss.str();
3076  }
3077 );
3078 
3079 // OR --------------------------------------------------------------------------
3080 static InstructionDefinition or_rd_rs1_rs2 (
3081  ISA32_RV64IMACFD,
3082  "or",
3083  (uint32_t) 0x006033,
3084  (uint32_t) 0xfe00707f,
3085  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3086  {
3087 
3088 // -----------------------------------------------------------------------------
3089 
3090 // -----------------------------------------------------------------------------
3091 
3092 // -----------------------------------------------------------------------------
3093 etiss_uint8 rd = 0;
3094 static BitArrayRange R_rd_0(11, 7);
3095 rd += R_rd_0.read(ba) << 0;
3096 etiss_uint8 rs1 = 0;
3097 static BitArrayRange R_rs1_0(19, 15);
3098 rs1 += R_rs1_0.read(ba) << 0;
3099 etiss_uint8 rs2 = 0;
3100 static BitArrayRange R_rs2_0(24, 20);
3101 rs2 += R_rs2_0.read(ba) << 0;
3102 
3103 // -----------------------------------------------------------------------------
3104 
3105  {
3106  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3107 
3108  cp.code() = std::string("//OR\n");
3109 
3110 // -----------------------------------------------------------------------------
3111 { // block
3112 cp.code() += "{ // block\n";
3113 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3114 cp.code() += "} // block\n";
3115 } // block
3116 if ((rd % 32ULL) != 0LL) { // conditional
3117 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3118 } // conditional
3119 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3120 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3121 // -----------------------------------------------------------------------------
3122  cp.getAffectedRegisters().add("instructionPointer", 32);
3123  }
3124 
3125  return true;
3126  },
3127  0,
3128  [] (BitArray & ba, Instruction & instr)
3129  {
3130 // -----------------------------------------------------------------------------
3131 etiss_uint8 rd = 0;
3132 static BitArrayRange R_rd_0(11, 7);
3133 rd += R_rd_0.read(ba) << 0;
3134 etiss_uint8 rs1 = 0;
3135 static BitArrayRange R_rs1_0(19, 15);
3136 rs1 += R_rs1_0.read(ba) << 0;
3137 etiss_uint8 rs2 = 0;
3138 static BitArrayRange R_rs2_0(24, 20);
3139 rs2 += R_rs2_0.read(ba) << 0;
3140 
3141 // -----------------------------------------------------------------------------
3142 
3143  std::stringstream ss;
3144 // -----------------------------------------------------------------------------
3145 ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3146 // -----------------------------------------------------------------------------
3147  return ss.str();
3148  }
3149 );
3150 
3151 // AND -------------------------------------------------------------------------
3152 static InstructionDefinition and_rd_rs1_rs2 (
3153  ISA32_RV64IMACFD,
3154  "and",
3155  (uint32_t) 0x007033,
3156  (uint32_t) 0xfe00707f,
3157  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3158  {
3159 
3160 // -----------------------------------------------------------------------------
3161 
3162 // -----------------------------------------------------------------------------
3163 
3164 // -----------------------------------------------------------------------------
3165 etiss_uint8 rd = 0;
3166 static BitArrayRange R_rd_0(11, 7);
3167 rd += R_rd_0.read(ba) << 0;
3168 etiss_uint8 rs1 = 0;
3169 static BitArrayRange R_rs1_0(19, 15);
3170 rs1 += R_rs1_0.read(ba) << 0;
3171 etiss_uint8 rs2 = 0;
3172 static BitArrayRange R_rs2_0(24, 20);
3173 rs2 += R_rs2_0.read(ba) << 0;
3174 
3175 // -----------------------------------------------------------------------------
3176 
3177  {
3178  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3179 
3180  cp.code() = std::string("//AND\n");
3181 
3182 // -----------------------------------------------------------------------------
3183 { // block
3184 cp.code() += "{ // block\n";
3185 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3186 cp.code() += "} // block\n";
3187 } // block
3188 if ((rd % 32ULL) != 0LL) { // conditional
3189 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3190 } // conditional
3191 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3192 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3193 // -----------------------------------------------------------------------------
3194  cp.getAffectedRegisters().add("instructionPointer", 32);
3195  }
3196 
3197  return true;
3198  },
3199  0,
3200  [] (BitArray & ba, Instruction & instr)
3201  {
3202 // -----------------------------------------------------------------------------
3203 etiss_uint8 rd = 0;
3204 static BitArrayRange R_rd_0(11, 7);
3205 rd += R_rd_0.read(ba) << 0;
3206 etiss_uint8 rs1 = 0;
3207 static BitArrayRange R_rs1_0(19, 15);
3208 rs1 += R_rs1_0.read(ba) << 0;
3209 etiss_uint8 rs2 = 0;
3210 static BitArrayRange R_rs2_0(24, 20);
3211 rs2 += R_rs2_0.read(ba) << 0;
3212 
3213 // -----------------------------------------------------------------------------
3214 
3215  std::stringstream ss;
3216 // -----------------------------------------------------------------------------
3217 ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3218 // -----------------------------------------------------------------------------
3219  return ss.str();
3220  }
3221 );
3222 
3223 // FENCE -----------------------------------------------------------------------
3224 static InstructionDefinition fence_rd_rs1_succ_pred_fm (
3225  ISA32_RV64IMACFD,
3226  "fence",
3227  (uint32_t) 0x00000f,
3228  (uint32_t) 0x00707f,
3229  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3230  {
3231 
3232 // -----------------------------------------------------------------------------
3233 
3234 // -----------------------------------------------------------------------------
3235 
3236 // -----------------------------------------------------------------------------
3237 etiss_uint8 rd = 0;
3238 static BitArrayRange R_rd_0(11, 7);
3239 rd += R_rd_0.read(ba) << 0;
3240 etiss_uint8 rs1 = 0;
3241 static BitArrayRange R_rs1_0(19, 15);
3242 rs1 += R_rs1_0.read(ba) << 0;
3243 etiss_uint8 succ = 0;
3244 static BitArrayRange R_succ_0(23, 20);
3245 succ += R_succ_0.read(ba) << 0;
3246 etiss_uint8 pred = 0;
3247 static BitArrayRange R_pred_0(27, 24);
3248 pred += R_pred_0.read(ba) << 0;
3249 etiss_uint8 fm = 0;
3250 static BitArrayRange R_fm_0(31, 28);
3251 fm += R_fm_0.read(ba) << 0;
3252 
3253 // -----------------------------------------------------------------------------
3254 
3255  {
3256  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3257 
3258  cp.code() = std::string("//FENCE\n");
3259 
3260 // -----------------------------------------------------------------------------
3261 { // block
3262 cp.code() += "{ // block\n";
3263 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3264 cp.code() += "} // block\n";
3265 } // block
3266 cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
3267 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3268 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3269 // -----------------------------------------------------------------------------
3270  cp.getAffectedRegisters().add("instructionPointer", 32);
3271  }
3272 
3273  return true;
3274  },
3275  0,
3276  [] (BitArray & ba, Instruction & instr)
3277  {
3278 // -----------------------------------------------------------------------------
3279 etiss_uint8 rd = 0;
3280 static BitArrayRange R_rd_0(11, 7);
3281 rd += R_rd_0.read(ba) << 0;
3282 etiss_uint8 rs1 = 0;
3283 static BitArrayRange R_rs1_0(19, 15);
3284 rs1 += R_rs1_0.read(ba) << 0;
3285 etiss_uint8 succ = 0;
3286 static BitArrayRange R_succ_0(23, 20);
3287 succ += R_succ_0.read(ba) << 0;
3288 etiss_uint8 pred = 0;
3289 static BitArrayRange R_pred_0(27, 24);
3290 pred += R_pred_0.read(ba) << 0;
3291 etiss_uint8 fm = 0;
3292 static BitArrayRange R_fm_0(31, 28);
3293 fm += R_fm_0.read(ba) << 0;
3294 
3295 // -----------------------------------------------------------------------------
3296 
3297  std::stringstream ss;
3298 // -----------------------------------------------------------------------------
3299 ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
3300 // -----------------------------------------------------------------------------
3301  return ss.str();
3302  }
3303 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
blt_imm_rs1_rs2
static InstructionDefinition blt_imm_rs1_rs2(ISA32_RV64IMACFD, "blt",(uint32_t) 0x004063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLT\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "blt"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RV64IMACFD, "srl",(uint32_t) 0x005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srl"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RV64IMACFD, "auipc",(uint32_t) 0x000017,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AUIPC\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+(etiss_int32)(imm))+"LL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "auipc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RV64IMACFD, "lui",(uint32_t) 0x000037,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LUI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string((etiss_uint64)(((etiss_int32)(imm))))+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "lui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bgeu_imm_rs1_rs2
static InstructionDefinition bgeu_imm_rs1_rs2(ISA32_RV64IMACFD, "bgeu",(uint32_t) 0x007063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGEU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >= *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bgeu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RV64IMACFD, "xor",(uint32_t) 0x004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XOR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "xor"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RV64IMACFD, "slti",(uint32_t) 0x002013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL)) ? (1ULL) : (0LL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "slti"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sh_imm_rs1_rs2
static InstructionDefinition sh_imm_rs1_rs2(ISA32_RV64IMACFD, "sh",(uint32_t) 0x001023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SH\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sh"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RV64IMACFD, "addi",(uint32_t) 0x000013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV64IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RV64IMACFD, "ori",(uint32_t) 0x006013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ORI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RV64IMACFD, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRA\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sra"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RV64IMACFD, "jalr",(uint32_t) 0x000067,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JALR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL) & -2LL;\n";cp.code()+="if (new_pc % 2ULL) { // conditional\n";{ cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";} cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "jalr"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bltu_imm_rs1_rs2
static InstructionDefinition bltu_imm_rs1_rs2(ISA32_RV64IMACFD, "bltu",(uint32_t) 0x006063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLTU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bltu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RV64IMACFD, "jal",(uint32_t) 0x00006f,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JAL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int32)(((etiss_int32) imm)<<(11)) >>(11)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;std::stringstream ss;ss<< "jal"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RV64IMACFD, "add",(uint32_t) 0x000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "add"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RV64IMACFD, "and",(uint32_t) 0x007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AND\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "and"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RV64IMACFD, "sltu",(uint32_t) 0x003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (1ULL) : (0LL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sltu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RV64IMACFD, "or",(uint32_t) 0x006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//OR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "or"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RV64IMACFD, "sltiu",(uint32_t) 0x003013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTIU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL)) ? (1ULL) : (0LL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "sltiu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RV64IMACFD, "sll",(uint32_t) 0x001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 63ULL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sll"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RV64IMACFD, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUB\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] - *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sub"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RV64IMACFD, "slt",(uint32_t) 0x002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLT\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (1ULL) : (0LL);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "slt"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lhu_rd_rs1_imm
static InstructionDefinition lhu_rd_rs1_imm(ISA32_RV64IMACFD, "lhu",(uint32_t) 0x005003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LHU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV64IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
lbu_rd_rs1_imm
static InstructionDefinition lbu_rd_rs1_imm(ISA32_RV64IMACFD, "lbu",(uint32_t) 0x004003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LBU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lbu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sw_imm_rs1_rs2
static InstructionDefinition sw_imm_rs1_rs2(ISA32_RV64IMACFD, "sw",(uint32_t) 0x002023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV64IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RV64IMACFD, "andi",(uint32_t) 0x007013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ANDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "andi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bge_imm_rs1_rs2
static InstructionDefinition bge_imm_rs1_rs2(ISA32_RV64IMACFD, "bge",(uint32_t) 0x005063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGE\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bge"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lw_rd_rs1_imm
static InstructionDefinition lw_rd_rs1_imm(ISA32_RV64IMACFD, "lw",(uint32_t) 0x002003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fence_rd_rs1_succ_pred_fm
static InstructionDefinition fence_rd_rs1_succ_pred_fm(ISA32_RV64IMACFD, "fence",(uint32_t) 0x00000f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="((RV64IMACFD*)cpu)->FENCE[0ULL] = "+std::to_string(pred<< 4ULL|succ)+"ULL;\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | succ="+std::to_string(succ)+" | pred="+std::to_string(pred)+" | fm="+std::to_string(fm)+"]");return ss.str();})
beq_imm_rs1_rs2
static InstructionDefinition beq_imm_rs1_rs2(ISA32_RV64IMACFD, "beq",(uint32_t) 0x000063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BEQ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "beq"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bne_imm_rs1_rs2
static InstructionDefinition bne_imm_rs1_rs2(ISA32_RV64IMACFD, "bne",(uint32_t) 0x001063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BNE\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] != *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";{ cp.code()+="{ // block\n";if(imm % 2ULL) { { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) >>(3)))+"LL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bne"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lh_rd_rs1_imm
static InstructionDefinition lh_rd_rs1_imm(ISA32_RV64IMACFD, "lh",(uint32_t) 0x001003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LH\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int16 res = (etiss_int16)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RV64IMACFD, "xori",(uint32_t) 0x004013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XORI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ "+std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))))+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "xori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lb_rd_rs1_imm
static InstructionDefinition lb_rd_rs1_imm(ISA32_RV64IMACFD, "lb",(uint32_t) 0x000003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LB\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int8 res = (etiss_int8)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lb"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sb_imm_rs1_rs2
static InstructionDefinition sb_imm_rs1_rs2(ISA32_RV64IMACFD, "sb",(uint32_t) 0x000023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SB\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sb"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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