ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_tum_retInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // ECALL -----------------------------------------------------------------------
16 static InstructionDefinition ecall_ (
17  ISA32_RV32IMACFD,
18  "ecall",
19  (uint32_t) 0x000073,
20  (uint32_t) 0xffffffff,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 
30 // -----------------------------------------------------------------------------
31 
32  {
33  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
34 
35  cp.code() = std::string("//ECALL\n");
36 
37 // -----------------------------------------------------------------------------
38 cp.code() += "etiss_coverage_count(1, 168);\n";
39 { // block
40 cp.code() += "etiss_coverage_count(1, 1169);\n";
41 cp.code() += "{ // block\n";
42 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
43 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
44 cp.code() += "} // block\n";
45 } // block
46 { // block
47 cp.code() += "etiss_coverage_count(1, 2191);\n";
48 cp.code() += "{ // block\n";
49 { // procedure
50 cp.code() += "{ // procedure\n";
51 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
52 cp.code() += "etiss_coverage_count(4, 2190, 2186, 2189, 2188);\n";
53 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
54 cp.code() += "} // procedure\n";
55 } // procedure
56 cp.code() += "} // block\n";
57 } // block
58 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
59 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
60 // -----------------------------------------------------------------------------
61  cp.getAffectedRegisters().add("instructionPointer", 32);
62  }
63  {
64  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
65 
66  cp.code() = std::string("//ECALL\n");
67 
68 // -----------------------------------------------------------------------------
69 cp.code() += "return cpu->exception;\n";
70 // -----------------------------------------------------------------------------
71  }
72 
73  return true;
74  },
75  0,
76  [] (BitArray & ba, Instruction & instr)
77  {
78 // -----------------------------------------------------------------------------
79 
80 // -----------------------------------------------------------------------------
81 
82  std::stringstream ss;
83 // -----------------------------------------------------------------------------
84 ss << "ecall" << " # " << ba << (" []");
85 // -----------------------------------------------------------------------------
86  return ss.str();
87  }
88 );
89 
90 // MRET ------------------------------------------------------------------------
91 static InstructionDefinition mret_ (
92  ISA32_RV32IMACFD,
93  "mret",
94  (uint32_t) 0x30200073,
95  (uint32_t) 0xffffffff,
96  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
97  {
98 
99 // -----------------------------------------------------------------------------
100 
101 // -----------------------------------------------------------------------------
102 
103 // -----------------------------------------------------------------------------
104 
105 // -----------------------------------------------------------------------------
106 
107  {
108  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
109 
110  cp.code() = std::string("//MRET\n");
111 
112 // -----------------------------------------------------------------------------
113 cp.code() += "etiss_coverage_count(1, 166);\n";
114 { // block
115 cp.code() += "etiss_coverage_count(1, 1169);\n";
116 cp.code() += "{ // block\n";
117 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
118 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
119 cp.code() += "} // block\n";
120 } // block
121 { // block
122 cp.code() += "etiss_coverage_count(1, 2325);\n";
123 cp.code() += "{ // block\n";
124 cp.code() += "etiss_coverage_count(1, 2264);\n";
125 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
126 cp.code() += "etiss_coverage_count(2, 2267, 2265);\n";
127 { // procedure
128 cp.code() += "{ // procedure\n";
129 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
130 cp.code() += "etiss_coverage_count(2, 2270, 2268);\n";
131 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
132 cp.code() += "} // procedure\n";
133 } // procedure
134 cp.code() += "} // conditional\n";
135 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";
136 cp.code() += "etiss_coverage_count(3, 2275, 2271, 2274);\n";
137 cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
138 cp.code() += "etiss_coverage_count(2, 2279, 2278);\n";
139 cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";
140 cp.code() += "etiss_coverage_count(3, 2284, 2283, 2281);\n";
141 cp.code() += "etiss_coverage_count(1, 2285);\n";
142 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
143 cp.code() += "etiss_coverage_count(2, 2288, 2286);\n";
144 cp.code() += "s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";
145 cp.code() += "etiss_coverage_count(5, 2294, 2289, 2293, 2290, 2292);\n";
146 cp.code() += "} // conditional\n";
147 cp.code() += "s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";
148 cp.code() += "etiss_coverage_count(6, 2302, 2295, 2301, 2296, 2300, 2298);\n";
149 cp.code() += "s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";
150 cp.code() += "etiss_coverage_count(5, 2308, 2303, 2307, 2304, 2306);\n";
151 cp.code() += "s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
152 cp.code() += "etiss_coverage_count(7, 2318, 2309, 2317, 2310, 2316, 2313, 2312);\n";
153 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
154 cp.code() += "etiss_coverage_count(2, 2321, 2320);\n";
155 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
156 cp.code() += "etiss_coverage_count(3, 2324, 2322, 2323);\n";
157 cp.code() += "} // block\n";
158 } // block
159 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
160 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
161 // -----------------------------------------------------------------------------
162  cp.getAffectedRegisters().add("instructionPointer", 32);
163  }
164  {
165  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
166 
167  cp.code() = std::string("//MRET\n");
168 
169 // -----------------------------------------------------------------------------
170 cp.code() += "return cpu->exception;\n";
171 // -----------------------------------------------------------------------------
172  }
173 
174  return true;
175  },
176  0,
177  [] (BitArray & ba, Instruction & instr)
178  {
179 // -----------------------------------------------------------------------------
180 
181 // -----------------------------------------------------------------------------
182 
183  std::stringstream ss;
184 // -----------------------------------------------------------------------------
185 ss << "mret" << " # " << ba << (" []");
186 // -----------------------------------------------------------------------------
187  return ss.str();
188  }
189 );
190 
191 // WFI -------------------------------------------------------------------------
192 static InstructionDefinition wfi_ (
193  ISA32_RV32IMACFD,
194  "wfi",
195  (uint32_t) 0x10500073,
196  (uint32_t) 0xffffffff,
197  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
198  {
199 
200 // -----------------------------------------------------------------------------
201 
202 // -----------------------------------------------------------------------------
203 
204 // -----------------------------------------------------------------------------
205 
206 // -----------------------------------------------------------------------------
207 
208  {
209  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
210 
211  cp.code() = std::string("//WFI\n");
212 
213 // -----------------------------------------------------------------------------
214 cp.code() += "etiss_coverage_count(1, 169);\n";
215 { // block
216 cp.code() += "etiss_coverage_count(1, 1169);\n";
217 cp.code() += "{ // block\n";
218 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
219 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
220 cp.code() += "} // block\n";
221 } // block
222 { // block
223 cp.code() += "etiss_coverage_count(1, 2326);\n";
224 cp.code() += "{ // block\n";
225 cp.code() += "} // block\n";
226 } // block
227 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
228 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
229 // -----------------------------------------------------------------------------
230  cp.getAffectedRegisters().add("instructionPointer", 32);
231  }
232  {
233  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
234 
235  cp.code() = std::string("//WFI\n");
236 
237 // -----------------------------------------------------------------------------
238 cp.code() += "return cpu->exception;\n";
239 // -----------------------------------------------------------------------------
240  }
241 
242  return true;
243  },
244  0,
245  [] (BitArray & ba, Instruction & instr)
246  {
247 // -----------------------------------------------------------------------------
248 
249 // -----------------------------------------------------------------------------
250 
251  std::stringstream ss;
252 // -----------------------------------------------------------------------------
253 ss << "wfi" << " # " << ba << (" []");
254 // -----------------------------------------------------------------------------
255  return ss.str();
256  }
257 );
258 
259 // SRET ------------------------------------------------------------------------
260 static InstructionDefinition sret_ (
261  ISA32_RV32IMACFD,
262  "sret",
263  (uint32_t) 0x10200073,
264  (uint32_t) 0xffffffff,
265  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
266  {
267 
268 // -----------------------------------------------------------------------------
269 
270 // -----------------------------------------------------------------------------
271 
272 // -----------------------------------------------------------------------------
273 
274 // -----------------------------------------------------------------------------
275 
276  {
277  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
278 
279  cp.code() = std::string("//SRET\n");
280 
281 // -----------------------------------------------------------------------------
282 cp.code() += "etiss_coverage_count(1, 167);\n";
283 { // block
284 cp.code() += "etiss_coverage_count(1, 1169);\n";
285 cp.code() += "{ // block\n";
286 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
287 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
288 cp.code() += "} // block\n";
289 } // block
290 { // block
291 cp.code() += "etiss_coverage_count(1, 6415);\n";
292 cp.code() += "{ // block\n";
293 cp.code() += "etiss_coverage_count(1, 6361);\n";
294 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
295 cp.code() += "etiss_coverage_count(6, 6371, 6362, 6369, 6366, 6364, 6370);\n";
296 { // procedure
297 cp.code() += "{ // procedure\n";
298 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
299 cp.code() += "etiss_coverage_count(2, 6374, 6372);\n";
300 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
301 cp.code() += "} // procedure\n";
302 } // procedure
303 cp.code() += "} // conditional\n";
304 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";
305 cp.code() += "etiss_coverage_count(3, 6379, 6375, 6378);\n";
306 cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
307 cp.code() += "etiss_coverage_count(2, 6383, 6382);\n";
308 cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";
309 cp.code() += "etiss_coverage_count(3, 6388, 6387, 6385);\n";
310 cp.code() += "s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";
311 cp.code() += "etiss_coverage_count(6, 6396, 6389, 6395, 6390, 6394, 6392);\n";
312 cp.code() += "s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";
313 cp.code() += "etiss_coverage_count(5, 6402, 6397, 6401, 6398, 6400);\n";
314 cp.code() += "s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";
315 cp.code() += "etiss_coverage_count(4, 6408, 6403, 6407, 6404);\n";
316 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
317 cp.code() += "etiss_coverage_count(2, 6411, 6410);\n";
318 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
319 cp.code() += "etiss_coverage_count(3, 6414, 6412, 6413);\n";
320 cp.code() += "} // block\n";
321 } // block
322 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
323 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
324 // -----------------------------------------------------------------------------
325  cp.getAffectedRegisters().add("instructionPointer", 32);
326  }
327  {
328  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
329 
330  cp.code() = std::string("//SRET\n");
331 
332 // -----------------------------------------------------------------------------
333 cp.code() += "return cpu->exception;\n";
334 // -----------------------------------------------------------------------------
335  }
336 
337  return true;
338  },
339  0,
340  [] (BitArray & ba, Instruction & instr)
341  {
342 // -----------------------------------------------------------------------------
343 
344 // -----------------------------------------------------------------------------
345 
346  std::stringstream ss;
347 // -----------------------------------------------------------------------------
348 ss << "sret" << " # " << ba << (" []");
349 // -----------------------------------------------------------------------------
350  return ss.str();
351  }
352 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
ecall_
static InstructionDefinition ecall_(ISA32_RV32IMACFD, "ecall",(uint32_t) 0x000073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="etiss_coverage_count(1, 168);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2191);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";cp.code()+="etiss_coverage_count(4, 2190, 2186, 2189, 2188);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();})
wfi_
static InstructionDefinition wfi_(ISA32_RV32IMACFD, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="etiss_coverage_count(1, 169);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2326);\n";cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();})
mret_
static InstructionDefinition mret_(ISA32_RV32IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="etiss_coverage_count(1, 166);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2325);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2264);\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 2267, 2265);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2270, 2268);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_coverage_count(3, 2275, 2271, 2274);\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_coverage_count(2, 2279, 2278);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";cp.code()+="etiss_coverage_count(3, 2284, 2283, 2281);\n";cp.code()+="etiss_coverage_count(1, 2285);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 2288, 2286);\n";cp.code()+="s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="etiss_coverage_count(5, 2294, 2289, 2293, 2290, 2292);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";cp.code()+="etiss_coverage_count(6, 2302, 2295, 2301, 2296, 2300, 2298);\n";cp.code()+="s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 2308, 2303, 2307, 2304, 2306);\n";cp.code()+="s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="etiss_coverage_count(7, 2318, 2309, 2317, 2310, 2316, 2313, 2312);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 2321, 2320);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="etiss_coverage_count(3, 2324, 2322, 2323);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();})
sret_
static InstructionDefinition sret_(ISA32_RV32IMACFD, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="etiss_coverage_count(1, 167);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6415);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 6361);\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";cp.code()+="etiss_coverage_count(6, 6371, 6362, 6369, 6366, 6364, 6370);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 6374, 6372);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_coverage_count(3, 6379, 6375, 6378);\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_coverage_count(2, 6383, 6382);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";cp.code()+="etiss_coverage_count(3, 6388, 6387, 6385);\n";cp.code()+="s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";cp.code()+="etiss_coverage_count(6, 6396, 6389, 6395, 6390, 6394, 6392);\n";cp.code()+="s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 6402, 6397, 6401, 6398, 6400);\n";cp.code()+="s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="etiss_coverage_count(4, 6408, 6403, 6407, 6404);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="etiss_coverage_count(2, 6411, 6410);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="etiss_coverage_count(3, 6414, 6412, 6413);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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