ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_tum_retInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // ECALL -----------------------------------------------------------------------
16 static InstructionDefinition ecall_ (
17  ISA32_RV32IMACFD,
18  "ecall",
19  (uint32_t) 0x000073,
20  (uint32_t) 0xffffffff,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 
30 // -----------------------------------------------------------------------------
31 
32  {
33  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
34 
35  cp.code() = std::string("//ECALL\n");
36 
37 // -----------------------------------------------------------------------------
38 { // block
39 cp.code() += "{ // block\n";
40 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
41 cp.code() += "} // block\n";
42 } // block
43 { // block
44 cp.code() += "{ // block\n";
45 { // procedure
46 cp.code() += "{ // procedure\n";
47 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
48 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
49 cp.code() += "} // procedure\n";
50 } // procedure
51 cp.code() += "} // block\n";
52 } // block
53 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
54 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
55 // -----------------------------------------------------------------------------
56  cp.getAffectedRegisters().add("instructionPointer", 32);
57  }
58  {
59  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
60 
61  cp.code() = std::string("//ECALL\n");
62 
63 // -----------------------------------------------------------------------------
64 cp.code() += "return cpu->exception;\n";
65 // -----------------------------------------------------------------------------
66  }
67 
68  return true;
69  },
70  0,
71  [] (BitArray & ba, Instruction & instr)
72  {
73 // -----------------------------------------------------------------------------
74 
75 // -----------------------------------------------------------------------------
76 
77  std::stringstream ss;
78 // -----------------------------------------------------------------------------
79 ss << "ecall" << " # " << ba << (" []");
80 // -----------------------------------------------------------------------------
81  return ss.str();
82  }
83 );
84 
85 // MRET ------------------------------------------------------------------------
86 static InstructionDefinition mret_ (
87  ISA32_RV32IMACFD,
88  "mret",
89  (uint32_t) 0x30200073,
90  (uint32_t) 0xffffffff,
91  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
92  {
93 
94 // -----------------------------------------------------------------------------
95 
96 // -----------------------------------------------------------------------------
97 
98 // -----------------------------------------------------------------------------
99 
100 // -----------------------------------------------------------------------------
101 
102  {
103  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
104 
105  cp.code() = std::string("//MRET\n");
106 
107 // -----------------------------------------------------------------------------
108 { // block
109 cp.code() += "{ // block\n";
110 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
111 cp.code() += "} // block\n";
112 } // block
113 { // block
114 cp.code() += "{ // block\n";
115 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
116 { // procedure
117 cp.code() += "{ // procedure\n";
118 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
119 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
120 cp.code() += "} // procedure\n";
121 } // procedure
122 cp.code() += "} // conditional\n";
123 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";
124 cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
125 cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";
126 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
127 cp.code() += "s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";
128 cp.code() += "} // conditional\n";
129 cp.code() += "s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";
130 cp.code() += "s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";
131 cp.code() += "s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
132 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
133 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
134 cp.code() += "} // block\n";
135 } // block
136 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
137 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
138 // -----------------------------------------------------------------------------
139  cp.getAffectedRegisters().add("instructionPointer", 32);
140  }
141  {
142  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
143 
144  cp.code() = std::string("//MRET\n");
145 
146 // -----------------------------------------------------------------------------
147 cp.code() += "return cpu->exception;\n";
148 // -----------------------------------------------------------------------------
149  }
150 
151  return true;
152  },
153  0,
154  [] (BitArray & ba, Instruction & instr)
155  {
156 // -----------------------------------------------------------------------------
157 
158 // -----------------------------------------------------------------------------
159 
160  std::stringstream ss;
161 // -----------------------------------------------------------------------------
162 ss << "mret" << " # " << ba << (" []");
163 // -----------------------------------------------------------------------------
164  return ss.str();
165  }
166 );
167 
168 // WFI -------------------------------------------------------------------------
169 static InstructionDefinition wfi_ (
170  ISA32_RV32IMACFD,
171  "wfi",
172  (uint32_t) 0x10500073,
173  (uint32_t) 0xffffffff,
174  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
175  {
176 
177 // -----------------------------------------------------------------------------
178 
179 // -----------------------------------------------------------------------------
180 
181 // -----------------------------------------------------------------------------
182 
183 // -----------------------------------------------------------------------------
184 
185  {
186  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
187 
188  cp.code() = std::string("//WFI\n");
189 
190 // -----------------------------------------------------------------------------
191 { // block
192 cp.code() += "{ // block\n";
193 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
194 cp.code() += "} // block\n";
195 } // block
196 { // block
197 cp.code() += "{ // block\n";
198 cp.code() += "} // block\n";
199 } // block
200 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
201 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
202 // -----------------------------------------------------------------------------
203  cp.getAffectedRegisters().add("instructionPointer", 32);
204  }
205  {
206  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
207 
208  cp.code() = std::string("//WFI\n");
209 
210 // -----------------------------------------------------------------------------
211 cp.code() += "return cpu->exception;\n";
212 // -----------------------------------------------------------------------------
213  }
214 
215  return true;
216  },
217  0,
218  [] (BitArray & ba, Instruction & instr)
219  {
220 // -----------------------------------------------------------------------------
221 
222 // -----------------------------------------------------------------------------
223 
224  std::stringstream ss;
225 // -----------------------------------------------------------------------------
226 ss << "wfi" << " # " << ba << (" []");
227 // -----------------------------------------------------------------------------
228  return ss.str();
229  }
230 );
231 
232 // SRET ------------------------------------------------------------------------
233 static InstructionDefinition sret_ (
234  ISA32_RV32IMACFD,
235  "sret",
236  (uint32_t) 0x10200073,
237  (uint32_t) 0xffffffff,
238  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
239  {
240 
241 // -----------------------------------------------------------------------------
242 
243 // -----------------------------------------------------------------------------
244 
245 // -----------------------------------------------------------------------------
246 
247 // -----------------------------------------------------------------------------
248 
249  {
250  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
251 
252  cp.code() = std::string("//SRET\n");
253 
254 // -----------------------------------------------------------------------------
255 { // block
256 cp.code() += "{ // block\n";
257 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
258 cp.code() += "} // block\n";
259 } // block
260 { // block
261 cp.code() += "{ // block\n";
262 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
263 { // procedure
264 cp.code() += "{ // procedure\n";
265 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
266 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
267 cp.code() += "} // procedure\n";
268 } // procedure
269 cp.code() += "} // conditional\n";
270 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";
271 cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
272 cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";
273 cp.code() += "s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";
274 cp.code() += "s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";
275 cp.code() += "s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";
276 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
277 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
278 cp.code() += "} // block\n";
279 } // block
280 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
281 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
282 // -----------------------------------------------------------------------------
283  cp.getAffectedRegisters().add("instructionPointer", 32);
284  }
285  {
286  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
287 
288  cp.code() = std::string("//SRET\n");
289 
290 // -----------------------------------------------------------------------------
291 cp.code() += "return cpu->exception;\n";
292 // -----------------------------------------------------------------------------
293  }
294 
295  return true;
296  },
297  0,
298  [] (BitArray & ba, Instruction & instr)
299  {
300 // -----------------------------------------------------------------------------
301 
302 // -----------------------------------------------------------------------------
303 
304  std::stringstream ss;
305 // -----------------------------------------------------------------------------
306 ss << "sret" << " # " << ba << (" []");
307 // -----------------------------------------------------------------------------
308  return ss.str();
309  }
310 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
wfi_
static InstructionDefinition wfi_(ISA32_RV32IMACFD, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//WFI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//WFI\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "wfi"<< " # "<< ba<<(" []");return ss.str();})
ecall_
static InstructionDefinition ecall_(ISA32_RV32IMACFD, "ecall",(uint32_t) 0x000073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ECALL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//ECALL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "ecall"<< " # "<< ba<<(" []");return ss.str();})
mret_
static InstructionDefinition mret_(ISA32_RV32IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();})
sret_
static InstructionDefinition sret_(ISA32_RV32IMACFD, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";cp.code()+="s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";cp.code()+="s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";cp.code()+="s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SRET\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "sret"<< " # "<< ba<<(" []");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Jul 4 2024 12:41:52 for ETISS 0.8.0 by doxygen 1.9.1