InstructionDefinition mret_(ISA32_RV32IMACFD, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff,[](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n"); { cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n"; cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n"); cp.code()+="return cpu->exception;\n"; } return true;}, 0,[](BitArray &ba, Instruction &instr) { std::stringstream ss; ss<< "mret"<< " # "<< ba<<(" []"); return ss.str();}) |
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ISA32_RV32IMACFD |
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"mret" |
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(uint32_t) |
0x30200073, |
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(uint32_t) |
0xffffffff, |
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[] (BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MRET\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";cp.code()+="etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";cp.code()+="etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";cp.code()+="if (prev_prv != 3LL) { // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 131072LL, 0LL);\n";cp.code()+="} // conditional\n";cp.code()+="s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";cp.code()+="s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";cp.code()+="s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";cp.code()+="((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//MRET\n");cp.code()+="return cpu->exception;\n";} return true;} |
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0 |
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[] (BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "mret"<< " # "<< ba<<(" []");return ss.str();} |
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