RV32IMACFDFuncs.h

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#ifndef __RV32IMACFD_FUNCS_H
#define __RV32IMACFD_FUNCS_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "RV32IMACFD.h"
#include "etiss/jit/CPU.h"
#include "etiss/jit/System.h"
#include "etiss/jit/ReturnCode.h"
 
 
void leave(etiss_int32 priv_lvl);
 
void wait(etiss_int32 flag);
 
etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 
etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 
etiss_uint32 unbox_s(etiss_uint64);
 
etiss_uint32 fclass_s(etiss_uint32);
 
etiss_uint32 fget_flags();
 
etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
 
etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 
etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 
etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 
etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 
etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 
etiss_uint64 unbox_d(etiss_uint64);
 
etiss_uint64 fclass_d(etiss_uint64);
 
etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
etiss_uint64 etiss_get_time();
 
etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
 
void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
 
etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask);
 
etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
 
etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val);
 
void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
 
void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
 
etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
etiss_uint8 etiss_semihost_enabled();
 
etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 
#ifdef __cplusplus
}
#endif
 
#endif