7 #ifndef __RV32IMACFD_FUNCS_H
8 #define __RV32IMACFD_FUNCS_H
15 #include "etiss/jit/CPU.h"
16 #include "etiss/jit/System.h"
17 #include "etiss/jit/ReturnCode.h"
18 #include "etiss/jit/Coverage.h"
etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8)
etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8)
void leave(etiss_int32 priv_lvl)
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8)
void RV32IMACFD_translate_exc_code(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 cause)
etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8)
etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32)
etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32)
etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint32 unbox_s(etiss_uint64)
etiss_uint64 etiss_get_instret(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
void wait(etiss_int32 flag)
void RV32IMACFD_check_irq(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
void RV32IMACFD_csr_write(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8)
etiss_uint64 etiss_get_time()
etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint8 rm)
etiss_uint8 etiss_semihost_enabled()
Checks whether semihosting is enabled in the config.
etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8)
etiss_uint32 fclass_s(etiss_uint32)
etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint64 etiss_get_cycles(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint32 fget_flags()
etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8)
etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32)
etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int8 extension)
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers)
etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8)
void RV32IMACFD_raise(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32)
etiss_int64 etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter)
Executes the semihosting call based on the operation number.
etiss_uint64 fclass_d(etiss_uint64)
etiss_uint64 unbox_d(etiss_uint64)
etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8)
etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8)
etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU *const cpu, ETISS_System *const system, void *const *const plugin_pointers, etiss_uint32 csr)
etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8)
basic cpu state structure needed for execution of any cpu architecture.
memory access and time synchronization functions.