ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_tum_csrInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CSRRW -----------------------------------------------------------------------
16 static InstructionDefinition csrrw_rd_rs1_csr (
17  ISA32_RV32IMACFD,
18  "csrrw",
19  (uint32_t) 0x001073,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 csr = 0;
36 static BitArrayRange R_csr_0(31, 20);
37 csr += R_csr_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//CSRRW\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 153);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 3249);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
59 cp.code() += "etiss_coverage_count(4, 3222, 3221, 3220, 3218);\n";
60 cp.code() += "etiss_coverage_count(1, 3223);\n";
61 if ((rd % 32ULL) != 0LL) { // conditional
62 cp.code() += "etiss_coverage_count(5, 3229, 3226, 3224, 3227, 3228);\n";
63 { // block
64 cp.code() += "etiss_coverage_count(1, 3244);\n";
65 cp.code() += "{ // block\n";
66 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
67 cp.code() += "etiss_coverage_count(3, 3233, 3232, 3231);\n";
68 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
69 cp.code() += "etiss_coverage_count(3, 3236, 3234, 3235);\n";
70 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
71 cp.code() += "etiss_coverage_count(5, 3243, 3241, 3240, 3238, 3242);\n";
72 cp.code() += "} // block\n";
73 } // block
74 } // conditional
75 else { // conditional
76 { // block
77 cp.code() += "etiss_coverage_count(1, 3248);\n";
78 cp.code() += "{ // block\n";
79 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
80 cp.code() += "etiss_coverage_count(3, 3247, 3245, 3246);\n";
81 cp.code() += "} // block\n";
82 } // block
83 } // conditional
84 cp.code() += "} // block\n";
85 } // block
86 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
87 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
88 // -----------------------------------------------------------------------------
89  cp.getAffectedRegisters().add("instructionPointer", 32);
90  }
91 
92  return true;
93  },
94  0,
95  [] (BitArray & ba, Instruction & instr)
96  {
97 // -----------------------------------------------------------------------------
98 etiss_uint8 rd = 0;
99 static BitArrayRange R_rd_0(11, 7);
100 rd += R_rd_0.read(ba) << 0;
101 etiss_uint8 rs1 = 0;
102 static BitArrayRange R_rs1_0(19, 15);
103 rs1 += R_rs1_0.read(ba) << 0;
104 etiss_uint16 csr = 0;
105 static BitArrayRange R_csr_0(31, 20);
106 csr += R_csr_0.read(ba) << 0;
107 
108 // -----------------------------------------------------------------------------
109 
110  std::stringstream ss;
111 // -----------------------------------------------------------------------------
112 ss << "csrrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
113 // -----------------------------------------------------------------------------
114  return ss.str();
115  }
116 );
117 
118 // CSRRS -----------------------------------------------------------------------
119 static InstructionDefinition csrrs_rd_rs1_csr (
120  ISA32_RV32IMACFD,
121  "csrrs",
122  (uint32_t) 0x002073,
123  (uint32_t) 0x00707f,
124  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
125  {
126 
127 // -----------------------------------------------------------------------------
128 
129 // -----------------------------------------------------------------------------
130 
131 // -----------------------------------------------------------------------------
132 etiss_uint8 rd = 0;
133 static BitArrayRange R_rd_0(11, 7);
134 rd += R_rd_0.read(ba) << 0;
135 etiss_uint8 rs1 = 0;
136 static BitArrayRange R_rs1_0(19, 15);
137 rs1 += R_rs1_0.read(ba) << 0;
138 etiss_uint16 csr = 0;
139 static BitArrayRange R_csr_0(31, 20);
140 csr += R_csr_0.read(ba) << 0;
141 
142 // -----------------------------------------------------------------------------
143 
144  {
145  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
146 
147  cp.code() = std::string("//CSRRS\n");
148 
149 // -----------------------------------------------------------------------------
150 cp.code() += "etiss_coverage_count(1, 154);\n";
151 { // block
152 cp.code() += "etiss_coverage_count(1, 1169);\n";
153 cp.code() += "{ // block\n";
154 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
155 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
156 cp.code() += "} // block\n";
157 } // block
158 { // block
159 cp.code() += "etiss_coverage_count(1, 3284);\n";
160 cp.code() += "{ // block\n";
161 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
162 cp.code() += "etiss_coverage_count(3, 3253, 3252, 3251);\n";
163 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
164 cp.code() += "etiss_coverage_count(4, 3260, 3259, 3258, 3256);\n";
165 cp.code() += "etiss_coverage_count(1, 3261);\n";
166 if (rs1 != 0LL) { // conditional
167 cp.code() += "etiss_coverage_count(3, 3264, 3262, 3263);\n";
168 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
169 cp.code() += "etiss_coverage_count(5, 3269, 3265, 3268, 3266, 3267);\n";
170 } // conditional
171 cp.code() += "etiss_coverage_count(1, 3270);\n";
172 if ((rd % 32ULL) != 0LL) { // conditional
173 cp.code() += "etiss_coverage_count(5, 3276, 3273, 3271, 3274, 3275);\n";
174 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
175 cp.code() += "etiss_coverage_count(5, 3283, 3281, 3280, 3278, 3282);\n";
176 } // conditional
177 cp.code() += "} // block\n";
178 } // block
179 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
180 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
181 // -----------------------------------------------------------------------------
182  cp.getAffectedRegisters().add("instructionPointer", 32);
183  }
184 
185  return true;
186  },
187  0,
188  [] (BitArray & ba, Instruction & instr)
189  {
190 // -----------------------------------------------------------------------------
191 etiss_uint8 rd = 0;
192 static BitArrayRange R_rd_0(11, 7);
193 rd += R_rd_0.read(ba) << 0;
194 etiss_uint8 rs1 = 0;
195 static BitArrayRange R_rs1_0(19, 15);
196 rs1 += R_rs1_0.read(ba) << 0;
197 etiss_uint16 csr = 0;
198 static BitArrayRange R_csr_0(31, 20);
199 csr += R_csr_0.read(ba) << 0;
200 
201 // -----------------------------------------------------------------------------
202 
203  std::stringstream ss;
204 // -----------------------------------------------------------------------------
205 ss << "csrrs" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
206 // -----------------------------------------------------------------------------
207  return ss.str();
208  }
209 );
210 
211 // CSRRC -----------------------------------------------------------------------
212 static InstructionDefinition csrrc_rd_rs1_csr (
213  ISA32_RV32IMACFD,
214  "csrrc",
215  (uint32_t) 0x003073,
216  (uint32_t) 0x00707f,
217  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
218  {
219 
220 // -----------------------------------------------------------------------------
221 
222 // -----------------------------------------------------------------------------
223 
224 // -----------------------------------------------------------------------------
225 etiss_uint8 rd = 0;
226 static BitArrayRange R_rd_0(11, 7);
227 rd += R_rd_0.read(ba) << 0;
228 etiss_uint8 rs1 = 0;
229 static BitArrayRange R_rs1_0(19, 15);
230 rs1 += R_rs1_0.read(ba) << 0;
231 etiss_uint16 csr = 0;
232 static BitArrayRange R_csr_0(31, 20);
233 csr += R_csr_0.read(ba) << 0;
234 
235 // -----------------------------------------------------------------------------
236 
237  {
238  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
239 
240  cp.code() = std::string("//CSRRC\n");
241 
242 // -----------------------------------------------------------------------------
243 cp.code() += "etiss_coverage_count(1, 155);\n";
244 { // block
245 cp.code() += "etiss_coverage_count(1, 1169);\n";
246 cp.code() += "{ // block\n";
247 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
248 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
249 cp.code() += "} // block\n";
250 } // block
251 { // block
252 cp.code() += "etiss_coverage_count(1, 3320);\n";
253 cp.code() += "{ // block\n";
254 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
255 cp.code() += "etiss_coverage_count(3, 3288, 3287, 3286);\n";
256 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
257 cp.code() += "etiss_coverage_count(4, 3295, 3294, 3293, 3291);\n";
258 cp.code() += "etiss_coverage_count(1, 3296);\n";
259 if (rs1 != 0LL) { // conditional
260 cp.code() += "etiss_coverage_count(3, 3299, 3297, 3298);\n";
261 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
262 cp.code() += "etiss_coverage_count(6, 3305, 3300, 3304, 3301, 3303, 3302);\n";
263 } // conditional
264 cp.code() += "etiss_coverage_count(1, 3306);\n";
265 if ((rd % 32ULL) != 0LL) { // conditional
266 cp.code() += "etiss_coverage_count(5, 3312, 3309, 3307, 3310, 3311);\n";
267 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
268 cp.code() += "etiss_coverage_count(5, 3319, 3317, 3316, 3314, 3318);\n";
269 } // conditional
270 cp.code() += "} // block\n";
271 } // block
272 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
273 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
274 // -----------------------------------------------------------------------------
275  cp.getAffectedRegisters().add("instructionPointer", 32);
276  }
277 
278  return true;
279  },
280  0,
281  [] (BitArray & ba, Instruction & instr)
282  {
283 // -----------------------------------------------------------------------------
284 etiss_uint8 rd = 0;
285 static BitArrayRange R_rd_0(11, 7);
286 rd += R_rd_0.read(ba) << 0;
287 etiss_uint8 rs1 = 0;
288 static BitArrayRange R_rs1_0(19, 15);
289 rs1 += R_rs1_0.read(ba) << 0;
290 etiss_uint16 csr = 0;
291 static BitArrayRange R_csr_0(31, 20);
292 csr += R_csr_0.read(ba) << 0;
293 
294 // -----------------------------------------------------------------------------
295 
296  std::stringstream ss;
297 // -----------------------------------------------------------------------------
298 ss << "csrrc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]");
299 // -----------------------------------------------------------------------------
300  return ss.str();
301  }
302 );
303 
304 // CSRRWI ----------------------------------------------------------------------
305 static InstructionDefinition csrrwi_rd_zimm_csr (
306  ISA32_RV32IMACFD,
307  "csrrwi",
308  (uint32_t) 0x005073,
309  (uint32_t) 0x00707f,
310  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
311  {
312 
313 // -----------------------------------------------------------------------------
314 
315 // -----------------------------------------------------------------------------
316 
317 // -----------------------------------------------------------------------------
318 etiss_uint8 rd = 0;
319 static BitArrayRange R_rd_0(11, 7);
320 rd += R_rd_0.read(ba) << 0;
321 etiss_uint8 zimm = 0;
322 static BitArrayRange R_zimm_0(19, 15);
323 zimm += R_zimm_0.read(ba) << 0;
324 etiss_uint16 csr = 0;
325 static BitArrayRange R_csr_0(31, 20);
326 csr += R_csr_0.read(ba) << 0;
327 
328 // -----------------------------------------------------------------------------
329 
330  {
331  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
332 
333  cp.code() = std::string("//CSRRWI\n");
334 
335 // -----------------------------------------------------------------------------
336 cp.code() += "etiss_coverage_count(1, 156);\n";
337 { // block
338 cp.code() += "etiss_coverage_count(1, 1169);\n";
339 cp.code() += "{ // block\n";
340 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
341 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
342 cp.code() += "} // block\n";
343 } // block
344 { // block
345 cp.code() += "etiss_coverage_count(1, 3344);\n";
346 cp.code() += "{ // block\n";
347 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
348 cp.code() += "etiss_coverage_count(3, 3324, 3323, 3322);\n";
349 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
350 cp.code() += "etiss_coverage_count(4, 3329, 3325, 3328, 3326);\n";
351 cp.code() += "etiss_coverage_count(1, 3330);\n";
352 if ((rd % 32ULL) != 0LL) { // conditional
353 cp.code() += "etiss_coverage_count(5, 3336, 3333, 3331, 3334, 3335);\n";
354 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
355 cp.code() += "etiss_coverage_count(5, 3343, 3341, 3340, 3338, 3342);\n";
356 } // conditional
357 cp.code() += "} // block\n";
358 } // block
359 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
360 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
361 // -----------------------------------------------------------------------------
362  cp.getAffectedRegisters().add("instructionPointer", 32);
363  }
364 
365  return true;
366  },
367  0,
368  [] (BitArray & ba, Instruction & instr)
369  {
370 // -----------------------------------------------------------------------------
371 etiss_uint8 rd = 0;
372 static BitArrayRange R_rd_0(11, 7);
373 rd += R_rd_0.read(ba) << 0;
374 etiss_uint8 zimm = 0;
375 static BitArrayRange R_zimm_0(19, 15);
376 zimm += R_zimm_0.read(ba) << 0;
377 etiss_uint16 csr = 0;
378 static BitArrayRange R_csr_0(31, 20);
379 csr += R_csr_0.read(ba) << 0;
380 
381 // -----------------------------------------------------------------------------
382 
383  std::stringstream ss;
384 // -----------------------------------------------------------------------------
385 ss << "csrrwi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
386 // -----------------------------------------------------------------------------
387  return ss.str();
388  }
389 );
390 
391 // CSRRSI ----------------------------------------------------------------------
392 static InstructionDefinition csrrsi_rd_zimm_csr (
393  ISA32_RV32IMACFD,
394  "csrrsi",
395  (uint32_t) 0x006073,
396  (uint32_t) 0x00707f,
397  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
398  {
399 
400 // -----------------------------------------------------------------------------
401 
402 // -----------------------------------------------------------------------------
403 
404 // -----------------------------------------------------------------------------
405 etiss_uint8 rd = 0;
406 static BitArrayRange R_rd_0(11, 7);
407 rd += R_rd_0.read(ba) << 0;
408 etiss_uint8 zimm = 0;
409 static BitArrayRange R_zimm_0(19, 15);
410 zimm += R_zimm_0.read(ba) << 0;
411 etiss_uint16 csr = 0;
412 static BitArrayRange R_csr_0(31, 20);
413 csr += R_csr_0.read(ba) << 0;
414 
415 // -----------------------------------------------------------------------------
416 
417  {
418  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
419 
420  cp.code() = std::string("//CSRRSI\n");
421 
422 // -----------------------------------------------------------------------------
423 cp.code() += "etiss_coverage_count(1, 157);\n";
424 { // block
425 cp.code() += "etiss_coverage_count(1, 1169);\n";
426 cp.code() += "{ // block\n";
427 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
428 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
429 cp.code() += "} // block\n";
430 } // block
431 { // block
432 cp.code() += "etiss_coverage_count(1, 3374);\n";
433 cp.code() += "{ // block\n";
434 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
435 cp.code() += "etiss_coverage_count(3, 3348, 3347, 3346);\n";
436 cp.code() += "etiss_coverage_count(1, 3349);\n";
437 if (zimm != 0LL) { // conditional
438 cp.code() += "etiss_coverage_count(3, 3352, 3350, 3351);\n";
439 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
440 cp.code() += "etiss_coverage_count(6, 3359, 3353, 3358, 3354, 3357, 3355);\n";
441 } // conditional
442 cp.code() += "etiss_coverage_count(1, 3360);\n";
443 if ((rd % 32ULL) != 0LL) { // conditional
444 cp.code() += "etiss_coverage_count(5, 3366, 3363, 3361, 3364, 3365);\n";
445 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
446 cp.code() += "etiss_coverage_count(5, 3373, 3371, 3370, 3368, 3372);\n";
447 } // conditional
448 cp.code() += "} // block\n";
449 } // block
450 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
451 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
452 // -----------------------------------------------------------------------------
453  cp.getAffectedRegisters().add("instructionPointer", 32);
454  }
455 
456  return true;
457  },
458  0,
459  [] (BitArray & ba, Instruction & instr)
460  {
461 // -----------------------------------------------------------------------------
462 etiss_uint8 rd = 0;
463 static BitArrayRange R_rd_0(11, 7);
464 rd += R_rd_0.read(ba) << 0;
465 etiss_uint8 zimm = 0;
466 static BitArrayRange R_zimm_0(19, 15);
467 zimm += R_zimm_0.read(ba) << 0;
468 etiss_uint16 csr = 0;
469 static BitArrayRange R_csr_0(31, 20);
470 csr += R_csr_0.read(ba) << 0;
471 
472 // -----------------------------------------------------------------------------
473 
474  std::stringstream ss;
475 // -----------------------------------------------------------------------------
476 ss << "csrrsi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
477 // -----------------------------------------------------------------------------
478  return ss.str();
479  }
480 );
481 
482 // CSRRCI ----------------------------------------------------------------------
483 static InstructionDefinition csrrci_rd_zimm_csr (
484  ISA32_RV32IMACFD,
485  "csrrci",
486  (uint32_t) 0x007073,
487  (uint32_t) 0x00707f,
488  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
489  {
490 
491 // -----------------------------------------------------------------------------
492 
493 // -----------------------------------------------------------------------------
494 
495 // -----------------------------------------------------------------------------
496 etiss_uint8 rd = 0;
497 static BitArrayRange R_rd_0(11, 7);
498 rd += R_rd_0.read(ba) << 0;
499 etiss_uint8 zimm = 0;
500 static BitArrayRange R_zimm_0(19, 15);
501 zimm += R_zimm_0.read(ba) << 0;
502 etiss_uint16 csr = 0;
503 static BitArrayRange R_csr_0(31, 20);
504 csr += R_csr_0.read(ba) << 0;
505 
506 // -----------------------------------------------------------------------------
507 
508  {
509  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
510 
511  cp.code() = std::string("//CSRRCI\n");
512 
513 // -----------------------------------------------------------------------------
514 cp.code() += "etiss_coverage_count(1, 158);\n";
515 { // block
516 cp.code() += "etiss_coverage_count(1, 1169);\n";
517 cp.code() += "{ // block\n";
518 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
519 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
520 cp.code() += "} // block\n";
521 } // block
522 { // block
523 cp.code() += "etiss_coverage_count(1, 3406);\n";
524 cp.code() += "{ // block\n";
525 cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
526 cp.code() += "etiss_coverage_count(3, 3378, 3377, 3376);\n";
527 cp.code() += "etiss_coverage_count(1, 3379);\n";
528 if (zimm != 0LL) { // conditional
529 cp.code() += "etiss_coverage_count(3, 3382, 3380, 3381);\n";
530 cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
531 cp.code() += "etiss_coverage_count(8, 3391, 3383, 3390, 3384, 3389, 3387, 3385, 3388);\n";
532 } // conditional
533 cp.code() += "etiss_coverage_count(1, 3392);\n";
534 if ((rd % 32ULL) != 0LL) { // conditional
535 cp.code() += "etiss_coverage_count(5, 3398, 3395, 3393, 3396, 3397);\n";
536 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
537 cp.code() += "etiss_coverage_count(5, 3405, 3403, 3402, 3400, 3404);\n";
538 } // conditional
539 cp.code() += "} // block\n";
540 } // block
541 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
542 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
543 // -----------------------------------------------------------------------------
544  cp.getAffectedRegisters().add("instructionPointer", 32);
545  }
546 
547  return true;
548  },
549  0,
550  [] (BitArray & ba, Instruction & instr)
551  {
552 // -----------------------------------------------------------------------------
553 etiss_uint8 rd = 0;
554 static BitArrayRange R_rd_0(11, 7);
555 rd += R_rd_0.read(ba) << 0;
556 etiss_uint8 zimm = 0;
557 static BitArrayRange R_zimm_0(19, 15);
558 zimm += R_zimm_0.read(ba) << 0;
559 etiss_uint16 csr = 0;
560 static BitArrayRange R_csr_0(31, 20);
561 csr += R_csr_0.read(ba) << 0;
562 
563 // -----------------------------------------------------------------------------
564 
565  std::stringstream ss;
566 // -----------------------------------------------------------------------------
567 ss << "csrrci" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]");
568 // -----------------------------------------------------------------------------
569  return ss.str();
570  }
571 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
csrrci_rd_zimm_csr
static InstructionDefinition csrrci_rd_zimm_csr(ISA32_RV32IMACFD, "csrrci",(uint32_t) 0x007073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRCI\n");cp.code()+="etiss_coverage_count(1, 158);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3378, 3377, 3376);\n";cp.code()+="etiss_coverage_count(1, 3379);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3382, 3380, 3381);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & "+std::to_string(~(((etiss_uint32)(zimm))))+"ULL);\n";cp.code()+="etiss_coverage_count(8, 3391, 3383, 3390, 3384, 3389, 3387, 3385, 3388);\n";} cp.code()+="etiss_coverage_count(1, 3392);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3398, 3395, 3393, 3396, 3397);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3405, 3403, 3402, 3400, 3404);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrci"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrwi_rd_zimm_csr
static InstructionDefinition csrrwi_rd_zimm_csr(ISA32_RV32IMACFD, "csrrwi",(uint32_t) 0x005073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRWI\n");cp.code()+="etiss_coverage_count(1, 156);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3344);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3324, 3323, 3322);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, "+std::to_string((etiss_uint32)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(4, 3329, 3325, 3328, 3326);\n";cp.code()+="etiss_coverage_count(1, 3330);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3336, 3333, 3331, 3334, 3335);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3343, 3341, 3340, 3338, 3342);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrwi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrsi_rd_zimm_csr
static InstructionDefinition csrrsi_rd_zimm_csr(ISA32_RV32IMACFD, "csrrsi",(uint32_t) 0x006073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRSI\n");cp.code()+="etiss_coverage_count(1, 157);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3374);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3348, 3347, 3346);\n";cp.code()+="etiss_coverage_count(1, 3349);\n";if(zimm !=0LL) { cp.code()+="etiss_coverage_count(3, 3352, 3350, 3351);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | "+std::to_string((etiss_uint32)(zimm))+"ULL);\n";cp.code()+="etiss_coverage_count(6, 3359, 3353, 3358, 3354, 3357, 3355);\n";} cp.code()+="etiss_coverage_count(1, 3360);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3366, 3363, 3361, 3364, 3365);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3373, 3371, 3370, 3368, 3372);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 zimm=0;static BitArrayRange R_zimm_0(19, 15);zimm+=R_zimm_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrsi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | zimm="+std::to_string(zimm)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrc_rd_rs1_csr
static InstructionDefinition csrrc_rd_rs1_csr(ISA32_RV32IMACFD, "csrrc",(uint32_t) 0x003073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRC\n");cp.code()+="etiss_coverage_count(1, 155);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3288, 3287, 3286);\n";cp.code()+="etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3295, 3294, 3293, 3291);\n";cp.code()+="etiss_coverage_count(1, 3296);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3299, 3297, 3298);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd & ~(xrs1));\n";cp.code()+="etiss_coverage_count(6, 3305, 3300, 3304, 3301, 3303, 3302);\n";} cp.code()+="etiss_coverage_count(1, 3306);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3312, 3309, 3307, 3310, 3311);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3319, 3317, 3316, 3314, 3318);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrw_rd_rs1_csr
static InstructionDefinition csrrw_rd_rs1_csr(ISA32_RV32IMACFD, "csrrw",(uint32_t) 0x001073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRW\n");cp.code()+="etiss_coverage_count(1, 153);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3249);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3222, 3221, 3220, 3218);\n";cp.code()+="etiss_coverage_count(1, 3223);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3229, 3226, 3224, 3227, 3228);\n";{ cp.code()+="etiss_coverage_count(1, 3244);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3233, 3232, 3231);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3236, 3234, 3235);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3243, 3241, 3240, 3238, 3242);\n";cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 3248);\n";cp.code()+="{ // block\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrs1);\n";cp.code()+="etiss_coverage_count(3, 3247, 3245, 3246);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
csrrs_rd_rs1_csr
static InstructionDefinition csrrs_rd_rs1_csr(ISA32_RV32IMACFD, "csrrs",(uint32_t) 0x002073,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRRS\n");cp.code()+="etiss_coverage_count(1, 154);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3284);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL);\n";cp.code()+="etiss_coverage_count(3, 3253, 3252, 3251);\n";cp.code()+="etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 3260, 3259, 3258, 3256);\n";cp.code()+="etiss_coverage_count(1, 3261);\n";if(rs1 !=0LL) { cp.code()+="etiss_coverage_count(3, 3264, 3262, 3263);\n";cp.code()+="RV32IMACFD_csr_write(cpu, system, plugin_pointers, "+std::to_string(csr)+"ULL, xrd | xrs1);\n";cp.code()+="etiss_coverage_count(5, 3269, 3265, 3268, 3266, 3267);\n";} cp.code()+="etiss_coverage_count(1, 3270);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3276, 3273, 3271, 3274, 3275);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = xrd;\n";cp.code()+="etiss_coverage_count(5, 3283, 3281, 3280, 3278, 3282);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 csr=0;static BitArrayRange R_csr_0(31, 20);csr+=R_csr_0.read(ba)<< 0;std::stringstream ss;ss<< "csrrs"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | csr="+std::to_string(csr)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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