ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV32IMACFD_RV32IInstr.cpp
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1
8#include "RV32IMACFDArch.h"
9#include "RV32IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// LUI -------------------------------------------------------------------------
16static InstructionDefinition lui_rd_imm (
17 ISA32_RV32IMACFD,
18 "lui",
19 (uint32_t) 0x000037,
20 (uint32_t) 0x00007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint32 imm = 0;
33static BitArrayRange R_imm_12(31, 12);
34imm += R_imm_12.read(ba) << 12;
35
36// -----------------------------------------------------------------------------
37
38 {
39 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
40
41 cp.code() = std::string("//LUI\n");
42
43// -----------------------------------------------------------------------------
44cp.code() += "etiss_coverage_count(1, 0);\n";
45{ // block
46cp.code() += "etiss_coverage_count(1, 1169);\n";
47cp.code() += "{ // block\n";
48cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
49cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
50cp.code() += "} // block\n";
51} // block
52cp.code() += "etiss_coverage_count(1, 1170);\n";
53if ((rd % 32ULL) != 0LL) { // conditional
54cp.code() += "etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";
55cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "ULL;\n";
56cp.code() += "etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";
57} // conditional
58cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
59cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
60// -----------------------------------------------------------------------------
61 cp.getAffectedRegisters().add("instructionPointer", 32);
62 }
63
64 return true;
65 },
66 0,
67 [] (BitArray & ba, Instruction & instr)
68 {
69// -----------------------------------------------------------------------------
70etiss_uint8 rd = 0;
71static BitArrayRange R_rd_0(11, 7);
72rd += R_rd_0.read(ba) << 0;
73etiss_uint32 imm = 0;
74static BitArrayRange R_imm_12(31, 12);
75imm += R_imm_12.read(ba) << 12;
76
77// -----------------------------------------------------------------------------
78
79 std::stringstream ss;
80// -----------------------------------------------------------------------------
81ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
82// -----------------------------------------------------------------------------
83 return ss.str();
84 }
85);
86
87// AUIPC -----------------------------------------------------------------------
88static InstructionDefinition auipc_rd_imm (
89 ISA32_RV32IMACFD,
90 "auipc",
91 (uint32_t) 0x000017,
92 (uint32_t) 0x00007f,
93 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
94 {
95
96// -----------------------------------------------------------------------------
97
98// -----------------------------------------------------------------------------
99
100// -----------------------------------------------------------------------------
101etiss_uint8 rd = 0;
102static BitArrayRange R_rd_0(11, 7);
103rd += R_rd_0.read(ba) << 0;
104etiss_uint32 imm = 0;
105static BitArrayRange R_imm_12(31, 12);
106imm += R_imm_12.read(ba) << 12;
107
108// -----------------------------------------------------------------------------
109
110 {
111 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
112
113 cp.code() = std::string("//AUIPC\n");
114
115// -----------------------------------------------------------------------------
116cp.code() += "etiss_coverage_count(1, 1);\n";
117{ // block
118cp.code() += "etiss_coverage_count(1, 1169);\n";
119cp.code() += "{ // block\n";
120cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
121cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
122cp.code() += "} // block\n";
123} // block
124cp.code() += "etiss_coverage_count(1, 1188);\n";
125if ((rd % 32ULL) != 0LL) { // conditional
126cp.code() += "etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";
127cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n";
128cp.code() += "etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";
129} // conditional
130cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
131cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
132// -----------------------------------------------------------------------------
133 cp.getAffectedRegisters().add("instructionPointer", 32);
134 }
135
136 return true;
137 },
138 0,
139 [] (BitArray & ba, Instruction & instr)
140 {
141// -----------------------------------------------------------------------------
142etiss_uint8 rd = 0;
143static BitArrayRange R_rd_0(11, 7);
144rd += R_rd_0.read(ba) << 0;
145etiss_uint32 imm = 0;
146static BitArrayRange R_imm_12(31, 12);
147imm += R_imm_12.read(ba) << 12;
148
149// -----------------------------------------------------------------------------
150
151 std::stringstream ss;
152// -----------------------------------------------------------------------------
153ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
154// -----------------------------------------------------------------------------
155 return ss.str();
156 }
157);
158
159// JAL -------------------------------------------------------------------------
160static InstructionDefinition jal_rd_imm (
161 ISA32_RV32IMACFD,
162 "jal",
163 (uint32_t) 0x00006f,
164 (uint32_t) 0x00007f,
165 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
166 {
167
168// -----------------------------------------------------------------------------
169
170// -----------------------------------------------------------------------------
171
172// -----------------------------------------------------------------------------
173etiss_uint8 rd = 0;
174static BitArrayRange R_rd_0(11, 7);
175rd += R_rd_0.read(ba) << 0;
176etiss_uint32 imm = 0;
177static BitArrayRange R_imm_12(19, 12);
178imm += R_imm_12.read(ba) << 12;
179static BitArrayRange R_imm_11(20, 20);
180imm += R_imm_11.read(ba) << 11;
181static BitArrayRange R_imm_1(30, 21);
182imm += R_imm_1.read(ba) << 1;
183static BitArrayRange R_imm_20(31, 31);
184imm += R_imm_20.read(ba) << 20;
185
186// -----------------------------------------------------------------------------
187
188 {
189 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
190
191 cp.code() = std::string("//JAL\n");
192
193// -----------------------------------------------------------------------------
194cp.code() += "etiss_coverage_count(1, 2);\n";
195{ // block
196cp.code() += "etiss_coverage_count(1, 1169);\n";
197cp.code() += "{ // block\n";
198cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
199cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
200cp.code() += "} // block\n";
201} // block
202{ // block
203cp.code() += "etiss_coverage_count(1, 1236);\n";
204cp.code() += "{ // block\n";
205cp.code() += "etiss_coverage_count(1, 1205);\n";
206if (imm % 2ULL) { // conditional
207cp.code() += "etiss_coverage_count(2, 1208, 1206);\n";
208{ // block
209cp.code() += "etiss_coverage_count(1, 1212);\n";
210cp.code() += "{ // block\n";
211{ // procedure
212cp.code() += "{ // procedure\n";
213cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
214cp.code() += "etiss_coverage_count(2, 1211, 1209);\n";
215cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
216cp.code() += "} // procedure\n";
217} // procedure
218cp.code() += "} // block\n";
219} // block
220} // conditional
221else { // conditional
222{ // block
223cp.code() += "etiss_coverage_count(1, 1235);\n";
224cp.code() += "{ // block\n";
225cp.code() += "etiss_coverage_count(1, 1213);\n";
226if ((rd % 32ULL) != 0LL) { // conditional
227cp.code() += "etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";
228cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
229cp.code() += "etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";
230} // conditional
231cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n";
232cp.code() += "etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";
233cp.code() += "} // block\n";
234} // block
235} // conditional
236cp.code() += "} // block\n";
237} // block
238cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
239cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
240// -----------------------------------------------------------------------------
241 cp.getAffectedRegisters().add("instructionPointer", 32);
242 }
243 {
244 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
245
246 cp.code() = std::string("//JAL\n");
247
248// -----------------------------------------------------------------------------
249cp.code() += "return cpu->exception;\n";
250// -----------------------------------------------------------------------------
251 }
252
253 return true;
254 },
255 0,
256 [] (BitArray & ba, Instruction & instr)
257 {
258// -----------------------------------------------------------------------------
259etiss_uint8 rd = 0;
260static BitArrayRange R_rd_0(11, 7);
261rd += R_rd_0.read(ba) << 0;
262etiss_uint32 imm = 0;
263static BitArrayRange R_imm_12(19, 12);
264imm += R_imm_12.read(ba) << 12;
265static BitArrayRange R_imm_11(20, 20);
266imm += R_imm_11.read(ba) << 11;
267static BitArrayRange R_imm_1(30, 21);
268imm += R_imm_1.read(ba) << 1;
269static BitArrayRange R_imm_20(31, 31);
270imm += R_imm_20.read(ba) << 20;
271
272// -----------------------------------------------------------------------------
273
274 std::stringstream ss;
275// -----------------------------------------------------------------------------
276ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
277// -----------------------------------------------------------------------------
278 return ss.str();
279 }
280);
281
282// JALR ------------------------------------------------------------------------
283static InstructionDefinition jalr_rd_rs1_imm (
284 ISA32_RV32IMACFD,
285 "jalr",
286 (uint32_t) 0x000067,
287 (uint32_t) 0x00707f,
288 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
289 {
290
291// -----------------------------------------------------------------------------
292
293// -----------------------------------------------------------------------------
294
295// -----------------------------------------------------------------------------
296etiss_uint8 rd = 0;
297static BitArrayRange R_rd_0(11, 7);
298rd += R_rd_0.read(ba) << 0;
299etiss_uint8 rs1 = 0;
300static BitArrayRange R_rs1_0(19, 15);
301rs1 += R_rs1_0.read(ba) << 0;
302etiss_uint16 imm = 0;
303static BitArrayRange R_imm_0(31, 20);
304imm += R_imm_0.read(ba) << 0;
305
306// -----------------------------------------------------------------------------
307
308 {
309 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
310
311 cp.code() = std::string("//JALR\n");
312
313// -----------------------------------------------------------------------------
314cp.code() += "etiss_coverage_count(1, 3);\n";
315{ // block
316cp.code() += "etiss_coverage_count(1, 1169);\n";
317cp.code() += "{ // block\n";
318cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
319cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
320cp.code() += "} // block\n";
321} // block
322{ // block
323cp.code() += "etiss_coverage_count(1, 1282);\n";
324cp.code() += "{ // block\n";
325cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n";
326cp.code() += "etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";
327cp.code() += "etiss_coverage_count(1, 1251);\n";
328cp.code() += "if (new_pc % 2ULL) { // conditional\n";
329cp.code() += "etiss_coverage_count(2, 1254, 1252);\n";
330{ // block
331cp.code() += "etiss_coverage_count(1, 1258);\n";
332cp.code() += "{ // block\n";
333{ // procedure
334cp.code() += "{ // procedure\n";
335cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
336cp.code() += "etiss_coverage_count(2, 1257, 1255);\n";
337cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
338cp.code() += "} // procedure\n";
339} // procedure
340cp.code() += "} // block\n";
341} // block
342cp.code() += "} // conditional\n";
343cp.code() += "else { // conditional\n";
344{ // block
345cp.code() += "etiss_coverage_count(1, 1281);\n";
346cp.code() += "{ // block\n";
347cp.code() += "etiss_coverage_count(1, 1259);\n";
348if ((rd % 32ULL) != 0LL) { // conditional
349cp.code() += "etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";
350cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n";
351cp.code() += "etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";
352} // conditional
353cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
354cp.code() += "etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";
355cp.code() += "} // block\n";
356} // block
357cp.code() += "} // conditional\n";
358cp.code() += "} // block\n";
359} // block
360cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
361cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
362// -----------------------------------------------------------------------------
363 cp.getAffectedRegisters().add("instructionPointer", 32);
364 }
365 {
366 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
367
368 cp.code() = std::string("//JALR\n");
369
370// -----------------------------------------------------------------------------
371cp.code() += "return cpu->exception;\n";
372// -----------------------------------------------------------------------------
373 }
374
375 return true;
376 },
377 0,
378 [] (BitArray & ba, Instruction & instr)
379 {
380// -----------------------------------------------------------------------------
381etiss_uint8 rd = 0;
382static BitArrayRange R_rd_0(11, 7);
383rd += R_rd_0.read(ba) << 0;
384etiss_uint8 rs1 = 0;
385static BitArrayRange R_rs1_0(19, 15);
386rs1 += R_rs1_0.read(ba) << 0;
387etiss_uint16 imm = 0;
388static BitArrayRange R_imm_0(31, 20);
389imm += R_imm_0.read(ba) << 0;
390
391// -----------------------------------------------------------------------------
392
393 std::stringstream ss;
394// -----------------------------------------------------------------------------
395ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
396// -----------------------------------------------------------------------------
397 return ss.str();
398 }
399);
400
401// BEQ -------------------------------------------------------------------------
402static InstructionDefinition beq_imm_rs1_rs2 (
403 ISA32_RV32IMACFD,
404 "beq",
405 (uint32_t) 0x000063,
406 (uint32_t) 0x00707f,
407 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
408 {
409
410// -----------------------------------------------------------------------------
411
412// -----------------------------------------------------------------------------
413
414// -----------------------------------------------------------------------------
415etiss_uint16 imm = 0;
416static BitArrayRange R_imm_11(7, 7);
417imm += R_imm_11.read(ba) << 11;
418static BitArrayRange R_imm_1(11, 8);
419imm += R_imm_1.read(ba) << 1;
420etiss_uint8 rs1 = 0;
421static BitArrayRange R_rs1_0(19, 15);
422rs1 += R_rs1_0.read(ba) << 0;
423etiss_uint8 rs2 = 0;
424static BitArrayRange R_rs2_0(24, 20);
425rs2 += R_rs2_0.read(ba) << 0;
426static BitArrayRange R_imm_5(30, 25);
427imm += R_imm_5.read(ba) << 5;
428static BitArrayRange R_imm_12(31, 31);
429imm += R_imm_12.read(ba) << 12;
430
431// -----------------------------------------------------------------------------
432
433 {
434 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
435
436 cp.code() = std::string("//BEQ\n");
437
438// -----------------------------------------------------------------------------
439cp.code() += "etiss_coverage_count(1, 4);\n";
440{ // block
441cp.code() += "etiss_coverage_count(1, 1169);\n";
442cp.code() += "{ // block\n";
443cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
444cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
445cp.code() += "} // block\n";
446} // block
447{ // block
448cp.code() += "etiss_coverage_count(1, 1311);\n";
449cp.code() += "{ // block\n";
450cp.code() += "etiss_coverage_count(1, 1283);\n";
451cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
452cp.code() += "etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";
453{ // block
454cp.code() += "etiss_coverage_count(1, 1310);\n";
455cp.code() += "{ // block\n";
456cp.code() += "etiss_coverage_count(1, 1295);\n";
457if (imm % 2ULL) { // conditional
458cp.code() += "etiss_coverage_count(2, 1298, 1296);\n";
459{ // block
460cp.code() += "etiss_coverage_count(1, 1302);\n";
461cp.code() += "{ // block\n";
462{ // procedure
463cp.code() += "{ // procedure\n";
464cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
465cp.code() += "etiss_coverage_count(2, 1301, 1299);\n";
466cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
467cp.code() += "} // procedure\n";
468} // procedure
469cp.code() += "} // block\n";
470} // block
471} // conditional
472else { // conditional
473{ // block
474cp.code() += "etiss_coverage_count(1, 1309);\n";
475cp.code() += "{ // block\n";
476cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
477cp.code() += "etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";
478cp.code() += "} // block\n";
479} // block
480} // conditional
481cp.code() += "} // block\n";
482} // block
483cp.code() += "} // conditional\n";
484cp.code() += "} // block\n";
485} // block
486cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
487cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
488// -----------------------------------------------------------------------------
489 cp.getAffectedRegisters().add("instructionPointer", 32);
490 }
491 {
492 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
493
494 cp.code() = std::string("//BEQ\n");
495
496// -----------------------------------------------------------------------------
497cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
498// -----------------------------------------------------------------------------
499 }
500
501 return true;
502 },
503 0,
504 [] (BitArray & ba, Instruction & instr)
505 {
506// -----------------------------------------------------------------------------
507etiss_uint16 imm = 0;
508static BitArrayRange R_imm_11(7, 7);
509imm += R_imm_11.read(ba) << 11;
510static BitArrayRange R_imm_1(11, 8);
511imm += R_imm_1.read(ba) << 1;
512etiss_uint8 rs1 = 0;
513static BitArrayRange R_rs1_0(19, 15);
514rs1 += R_rs1_0.read(ba) << 0;
515etiss_uint8 rs2 = 0;
516static BitArrayRange R_rs2_0(24, 20);
517rs2 += R_rs2_0.read(ba) << 0;
518static BitArrayRange R_imm_5(30, 25);
519imm += R_imm_5.read(ba) << 5;
520static BitArrayRange R_imm_12(31, 31);
521imm += R_imm_12.read(ba) << 12;
522
523// -----------------------------------------------------------------------------
524
525 std::stringstream ss;
526// -----------------------------------------------------------------------------
527ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
528// -----------------------------------------------------------------------------
529 return ss.str();
530 }
531);
532
533// BNE -------------------------------------------------------------------------
534static InstructionDefinition bne_imm_rs1_rs2 (
535 ISA32_RV32IMACFD,
536 "bne",
537 (uint32_t) 0x001063,
538 (uint32_t) 0x00707f,
539 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
540 {
541
542// -----------------------------------------------------------------------------
543
544// -----------------------------------------------------------------------------
545
546// -----------------------------------------------------------------------------
547etiss_uint16 imm = 0;
548static BitArrayRange R_imm_11(7, 7);
549imm += R_imm_11.read(ba) << 11;
550static BitArrayRange R_imm_1(11, 8);
551imm += R_imm_1.read(ba) << 1;
552etiss_uint8 rs1 = 0;
553static BitArrayRange R_rs1_0(19, 15);
554rs1 += R_rs1_0.read(ba) << 0;
555etiss_uint8 rs2 = 0;
556static BitArrayRange R_rs2_0(24, 20);
557rs2 += R_rs2_0.read(ba) << 0;
558static BitArrayRange R_imm_5(30, 25);
559imm += R_imm_5.read(ba) << 5;
560static BitArrayRange R_imm_12(31, 31);
561imm += R_imm_12.read(ba) << 12;
562
563// -----------------------------------------------------------------------------
564
565 {
566 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
567
568 cp.code() = std::string("//BNE\n");
569
570// -----------------------------------------------------------------------------
571cp.code() += "etiss_coverage_count(1, 5);\n";
572{ // block
573cp.code() += "etiss_coverage_count(1, 1169);\n";
574cp.code() += "{ // block\n";
575cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
576cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
577cp.code() += "} // block\n";
578} // block
579{ // block
580cp.code() += "etiss_coverage_count(1, 1340);\n";
581cp.code() += "{ // block\n";
582cp.code() += "etiss_coverage_count(1, 1312);\n";
583cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
584cp.code() += "etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";
585{ // block
586cp.code() += "etiss_coverage_count(1, 1339);\n";
587cp.code() += "{ // block\n";
588cp.code() += "etiss_coverage_count(1, 1324);\n";
589if (imm % 2ULL) { // conditional
590cp.code() += "etiss_coverage_count(2, 1327, 1325);\n";
591{ // block
592cp.code() += "etiss_coverage_count(1, 1331);\n";
593cp.code() += "{ // block\n";
594{ // procedure
595cp.code() += "{ // procedure\n";
596cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
597cp.code() += "etiss_coverage_count(2, 1330, 1328);\n";
598cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
599cp.code() += "} // procedure\n";
600} // procedure
601cp.code() += "} // block\n";
602} // block
603} // conditional
604else { // conditional
605{ // block
606cp.code() += "etiss_coverage_count(1, 1338);\n";
607cp.code() += "{ // block\n";
608cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
609cp.code() += "etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";
610cp.code() += "} // block\n";
611} // block
612} // conditional
613cp.code() += "} // block\n";
614} // block
615cp.code() += "} // conditional\n";
616cp.code() += "} // block\n";
617} // block
618cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
619cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
620// -----------------------------------------------------------------------------
621 cp.getAffectedRegisters().add("instructionPointer", 32);
622 }
623 {
624 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
625
626 cp.code() = std::string("//BNE\n");
627
628// -----------------------------------------------------------------------------
629cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
630// -----------------------------------------------------------------------------
631 }
632
633 return true;
634 },
635 0,
636 [] (BitArray & ba, Instruction & instr)
637 {
638// -----------------------------------------------------------------------------
639etiss_uint16 imm = 0;
640static BitArrayRange R_imm_11(7, 7);
641imm += R_imm_11.read(ba) << 11;
642static BitArrayRange R_imm_1(11, 8);
643imm += R_imm_1.read(ba) << 1;
644etiss_uint8 rs1 = 0;
645static BitArrayRange R_rs1_0(19, 15);
646rs1 += R_rs1_0.read(ba) << 0;
647etiss_uint8 rs2 = 0;
648static BitArrayRange R_rs2_0(24, 20);
649rs2 += R_rs2_0.read(ba) << 0;
650static BitArrayRange R_imm_5(30, 25);
651imm += R_imm_5.read(ba) << 5;
652static BitArrayRange R_imm_12(31, 31);
653imm += R_imm_12.read(ba) << 12;
654
655// -----------------------------------------------------------------------------
656
657 std::stringstream ss;
658// -----------------------------------------------------------------------------
659ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
660// -----------------------------------------------------------------------------
661 return ss.str();
662 }
663);
664
665// BLT -------------------------------------------------------------------------
666static InstructionDefinition blt_imm_rs1_rs2 (
667 ISA32_RV32IMACFD,
668 "blt",
669 (uint32_t) 0x004063,
670 (uint32_t) 0x00707f,
671 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
672 {
673
674// -----------------------------------------------------------------------------
675
676// -----------------------------------------------------------------------------
677
678// -----------------------------------------------------------------------------
679etiss_uint16 imm = 0;
680static BitArrayRange R_imm_11(7, 7);
681imm += R_imm_11.read(ba) << 11;
682static BitArrayRange R_imm_1(11, 8);
683imm += R_imm_1.read(ba) << 1;
684etiss_uint8 rs1 = 0;
685static BitArrayRange R_rs1_0(19, 15);
686rs1 += R_rs1_0.read(ba) << 0;
687etiss_uint8 rs2 = 0;
688static BitArrayRange R_rs2_0(24, 20);
689rs2 += R_rs2_0.read(ba) << 0;
690static BitArrayRange R_imm_5(30, 25);
691imm += R_imm_5.read(ba) << 5;
692static BitArrayRange R_imm_12(31, 31);
693imm += R_imm_12.read(ba) << 12;
694
695// -----------------------------------------------------------------------------
696
697 {
698 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
699
700 cp.code() = std::string("//BLT\n");
701
702// -----------------------------------------------------------------------------
703cp.code() += "etiss_coverage_count(1, 6);\n";
704{ // block
705cp.code() += "etiss_coverage_count(1, 1169);\n";
706cp.code() += "{ // block\n";
707cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
708cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
709cp.code() += "} // block\n";
710} // block
711{ // block
712cp.code() += "etiss_coverage_count(1, 1373);\n";
713cp.code() += "{ // block\n";
714cp.code() += "etiss_coverage_count(1, 1341);\n";
715cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
716cp.code() += "etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";
717{ // block
718cp.code() += "etiss_coverage_count(1, 1372);\n";
719cp.code() += "{ // block\n";
720cp.code() += "etiss_coverage_count(1, 1357);\n";
721if (imm % 2ULL) { // conditional
722cp.code() += "etiss_coverage_count(2, 1360, 1358);\n";
723{ // block
724cp.code() += "etiss_coverage_count(1, 1364);\n";
725cp.code() += "{ // block\n";
726{ // procedure
727cp.code() += "{ // procedure\n";
728cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
729cp.code() += "etiss_coverage_count(2, 1363, 1361);\n";
730cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
731cp.code() += "} // procedure\n";
732} // procedure
733cp.code() += "} // block\n";
734} // block
735} // conditional
736else { // conditional
737{ // block
738cp.code() += "etiss_coverage_count(1, 1371);\n";
739cp.code() += "{ // block\n";
740cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
741cp.code() += "etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";
742cp.code() += "} // block\n";
743} // block
744} // conditional
745cp.code() += "} // block\n";
746} // block
747cp.code() += "} // conditional\n";
748cp.code() += "} // block\n";
749} // block
750cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
751cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
752// -----------------------------------------------------------------------------
753 cp.getAffectedRegisters().add("instructionPointer", 32);
754 }
755 {
756 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
757
758 cp.code() = std::string("//BLT\n");
759
760// -----------------------------------------------------------------------------
761cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
762// -----------------------------------------------------------------------------
763 }
764
765 return true;
766 },
767 0,
768 [] (BitArray & ba, Instruction & instr)
769 {
770// -----------------------------------------------------------------------------
771etiss_uint16 imm = 0;
772static BitArrayRange R_imm_11(7, 7);
773imm += R_imm_11.read(ba) << 11;
774static BitArrayRange R_imm_1(11, 8);
775imm += R_imm_1.read(ba) << 1;
776etiss_uint8 rs1 = 0;
777static BitArrayRange R_rs1_0(19, 15);
778rs1 += R_rs1_0.read(ba) << 0;
779etiss_uint8 rs2 = 0;
780static BitArrayRange R_rs2_0(24, 20);
781rs2 += R_rs2_0.read(ba) << 0;
782static BitArrayRange R_imm_5(30, 25);
783imm += R_imm_5.read(ba) << 5;
784static BitArrayRange R_imm_12(31, 31);
785imm += R_imm_12.read(ba) << 12;
786
787// -----------------------------------------------------------------------------
788
789 std::stringstream ss;
790// -----------------------------------------------------------------------------
791ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
792// -----------------------------------------------------------------------------
793 return ss.str();
794 }
795);
796
797// BGE -------------------------------------------------------------------------
798static InstructionDefinition bge_imm_rs1_rs2 (
799 ISA32_RV32IMACFD,
800 "bge",
801 (uint32_t) 0x005063,
802 (uint32_t) 0x00707f,
803 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
804 {
805
806// -----------------------------------------------------------------------------
807
808// -----------------------------------------------------------------------------
809
810// -----------------------------------------------------------------------------
811etiss_uint16 imm = 0;
812static BitArrayRange R_imm_11(7, 7);
813imm += R_imm_11.read(ba) << 11;
814static BitArrayRange R_imm_1(11, 8);
815imm += R_imm_1.read(ba) << 1;
816etiss_uint8 rs1 = 0;
817static BitArrayRange R_rs1_0(19, 15);
818rs1 += R_rs1_0.read(ba) << 0;
819etiss_uint8 rs2 = 0;
820static BitArrayRange R_rs2_0(24, 20);
821rs2 += R_rs2_0.read(ba) << 0;
822static BitArrayRange R_imm_5(30, 25);
823imm += R_imm_5.read(ba) << 5;
824static BitArrayRange R_imm_12(31, 31);
825imm += R_imm_12.read(ba) << 12;
826
827// -----------------------------------------------------------------------------
828
829 {
830 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
831
832 cp.code() = std::string("//BGE\n");
833
834// -----------------------------------------------------------------------------
835cp.code() += "etiss_coverage_count(1, 7);\n";
836{ // block
837cp.code() += "etiss_coverage_count(1, 1169);\n";
838cp.code() += "{ // block\n";
839cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
840cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
841cp.code() += "} // block\n";
842} // block
843{ // block
844cp.code() += "etiss_coverage_count(1, 1406);\n";
845cp.code() += "{ // block\n";
846cp.code() += "etiss_coverage_count(1, 1374);\n";
847cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n";
848cp.code() += "etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";
849{ // block
850cp.code() += "etiss_coverage_count(1, 1405);\n";
851cp.code() += "{ // block\n";
852cp.code() += "etiss_coverage_count(1, 1390);\n";
853if (imm % 2ULL) { // conditional
854cp.code() += "etiss_coverage_count(2, 1393, 1391);\n";
855{ // block
856cp.code() += "etiss_coverage_count(1, 1397);\n";
857cp.code() += "{ // block\n";
858{ // procedure
859cp.code() += "{ // procedure\n";
860cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
861cp.code() += "etiss_coverage_count(2, 1396, 1394);\n";
862cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
863cp.code() += "} // procedure\n";
864} // procedure
865cp.code() += "} // block\n";
866} // block
867} // conditional
868else { // conditional
869{ // block
870cp.code() += "etiss_coverage_count(1, 1404);\n";
871cp.code() += "{ // block\n";
872cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
873cp.code() += "etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";
874cp.code() += "} // block\n";
875} // block
876} // conditional
877cp.code() += "} // block\n";
878} // block
879cp.code() += "} // conditional\n";
880cp.code() += "} // block\n";
881} // block
882cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
883cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
884// -----------------------------------------------------------------------------
885 cp.getAffectedRegisters().add("instructionPointer", 32);
886 }
887 {
888 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
889
890 cp.code() = std::string("//BGE\n");
891
892// -----------------------------------------------------------------------------
893cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
894// -----------------------------------------------------------------------------
895 }
896
897 return true;
898 },
899 0,
900 [] (BitArray & ba, Instruction & instr)
901 {
902// -----------------------------------------------------------------------------
903etiss_uint16 imm = 0;
904static BitArrayRange R_imm_11(7, 7);
905imm += R_imm_11.read(ba) << 11;
906static BitArrayRange R_imm_1(11, 8);
907imm += R_imm_1.read(ba) << 1;
908etiss_uint8 rs1 = 0;
909static BitArrayRange R_rs1_0(19, 15);
910rs1 += R_rs1_0.read(ba) << 0;
911etiss_uint8 rs2 = 0;
912static BitArrayRange R_rs2_0(24, 20);
913rs2 += R_rs2_0.read(ba) << 0;
914static BitArrayRange R_imm_5(30, 25);
915imm += R_imm_5.read(ba) << 5;
916static BitArrayRange R_imm_12(31, 31);
917imm += R_imm_12.read(ba) << 12;
918
919// -----------------------------------------------------------------------------
920
921 std::stringstream ss;
922// -----------------------------------------------------------------------------
923ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
924// -----------------------------------------------------------------------------
925 return ss.str();
926 }
927);
928
929// BLTU ------------------------------------------------------------------------
930static InstructionDefinition bltu_imm_rs1_rs2 (
931 ISA32_RV32IMACFD,
932 "bltu",
933 (uint32_t) 0x006063,
934 (uint32_t) 0x00707f,
935 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
936 {
937
938// -----------------------------------------------------------------------------
939
940// -----------------------------------------------------------------------------
941
942// -----------------------------------------------------------------------------
943etiss_uint16 imm = 0;
944static BitArrayRange R_imm_11(7, 7);
945imm += R_imm_11.read(ba) << 11;
946static BitArrayRange R_imm_1(11, 8);
947imm += R_imm_1.read(ba) << 1;
948etiss_uint8 rs1 = 0;
949static BitArrayRange R_rs1_0(19, 15);
950rs1 += R_rs1_0.read(ba) << 0;
951etiss_uint8 rs2 = 0;
952static BitArrayRange R_rs2_0(24, 20);
953rs2 += R_rs2_0.read(ba) << 0;
954static BitArrayRange R_imm_5(30, 25);
955imm += R_imm_5.read(ba) << 5;
956static BitArrayRange R_imm_12(31, 31);
957imm += R_imm_12.read(ba) << 12;
958
959// -----------------------------------------------------------------------------
960
961 {
962 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
963
964 cp.code() = std::string("//BLTU\n");
965
966// -----------------------------------------------------------------------------
967cp.code() += "etiss_coverage_count(1, 8);\n";
968{ // block
969cp.code() += "etiss_coverage_count(1, 1169);\n";
970cp.code() += "{ // block\n";
971cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
972cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
973cp.code() += "} // block\n";
974} // block
975{ // block
976cp.code() += "etiss_coverage_count(1, 1435);\n";
977cp.code() += "{ // block\n";
978cp.code() += "etiss_coverage_count(1, 1407);\n";
979cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
980cp.code() += "etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";
981{ // block
982cp.code() += "etiss_coverage_count(1, 1434);\n";
983cp.code() += "{ // block\n";
984cp.code() += "etiss_coverage_count(1, 1419);\n";
985if (imm % 2ULL) { // conditional
986cp.code() += "etiss_coverage_count(2, 1422, 1420);\n";
987{ // block
988cp.code() += "etiss_coverage_count(1, 1426);\n";
989cp.code() += "{ // block\n";
990{ // procedure
991cp.code() += "{ // procedure\n";
992cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
993cp.code() += "etiss_coverage_count(2, 1425, 1423);\n";
994cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
995cp.code() += "} // procedure\n";
996} // procedure
997cp.code() += "} // block\n";
998} // block
999} // conditional
1000else { // conditional
1001{ // block
1002cp.code() += "etiss_coverage_count(1, 1433);\n";
1003cp.code() += "{ // block\n";
1004cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1005cp.code() += "etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";
1006cp.code() += "} // block\n";
1007} // block
1008} // conditional
1009cp.code() += "} // block\n";
1010} // block
1011cp.code() += "} // conditional\n";
1012cp.code() += "} // block\n";
1013} // block
1014cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1015cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1016// -----------------------------------------------------------------------------
1017 cp.getAffectedRegisters().add("instructionPointer", 32);
1018 }
1019 {
1020 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1021
1022 cp.code() = std::string("//BLTU\n");
1023
1024// -----------------------------------------------------------------------------
1025cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1026// -----------------------------------------------------------------------------
1027 }
1028
1029 return true;
1030 },
1031 0,
1032 [] (BitArray & ba, Instruction & instr)
1033 {
1034// -----------------------------------------------------------------------------
1035etiss_uint16 imm = 0;
1036static BitArrayRange R_imm_11(7, 7);
1037imm += R_imm_11.read(ba) << 11;
1038static BitArrayRange R_imm_1(11, 8);
1039imm += R_imm_1.read(ba) << 1;
1040etiss_uint8 rs1 = 0;
1041static BitArrayRange R_rs1_0(19, 15);
1042rs1 += R_rs1_0.read(ba) << 0;
1043etiss_uint8 rs2 = 0;
1044static BitArrayRange R_rs2_0(24, 20);
1045rs2 += R_rs2_0.read(ba) << 0;
1046static BitArrayRange R_imm_5(30, 25);
1047imm += R_imm_5.read(ba) << 5;
1048static BitArrayRange R_imm_12(31, 31);
1049imm += R_imm_12.read(ba) << 12;
1050
1051// -----------------------------------------------------------------------------
1052
1053 std::stringstream ss;
1054// -----------------------------------------------------------------------------
1055ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1056// -----------------------------------------------------------------------------
1057 return ss.str();
1058 }
1059);
1060
1061// BGEU ------------------------------------------------------------------------
1062static InstructionDefinition bgeu_imm_rs1_rs2 (
1063 ISA32_RV32IMACFD,
1064 "bgeu",
1065 (uint32_t) 0x007063,
1066 (uint32_t) 0x00707f,
1067 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1068 {
1069
1070// -----------------------------------------------------------------------------
1071
1072// -----------------------------------------------------------------------------
1073
1074// -----------------------------------------------------------------------------
1075etiss_uint16 imm = 0;
1076static BitArrayRange R_imm_11(7, 7);
1077imm += R_imm_11.read(ba) << 11;
1078static BitArrayRange R_imm_1(11, 8);
1079imm += R_imm_1.read(ba) << 1;
1080etiss_uint8 rs1 = 0;
1081static BitArrayRange R_rs1_0(19, 15);
1082rs1 += R_rs1_0.read(ba) << 0;
1083etiss_uint8 rs2 = 0;
1084static BitArrayRange R_rs2_0(24, 20);
1085rs2 += R_rs2_0.read(ba) << 0;
1086static BitArrayRange R_imm_5(30, 25);
1087imm += R_imm_5.read(ba) << 5;
1088static BitArrayRange R_imm_12(31, 31);
1089imm += R_imm_12.read(ba) << 12;
1090
1091// -----------------------------------------------------------------------------
1092
1093 {
1094 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1095
1096 cp.code() = std::string("//BGEU\n");
1097
1098// -----------------------------------------------------------------------------
1099cp.code() += "etiss_coverage_count(1, 9);\n";
1100{ // block
1101cp.code() += "etiss_coverage_count(1, 1169);\n";
1102cp.code() += "{ // block\n";
1103cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1104cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1105cp.code() += "} // block\n";
1106} // block
1107{ // block
1108cp.code() += "etiss_coverage_count(1, 1464);\n";
1109cp.code() += "{ // block\n";
1110cp.code() += "etiss_coverage_count(1, 1436);\n";
1111cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n";
1112cp.code() += "etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";
1113{ // block
1114cp.code() += "etiss_coverage_count(1, 1463);\n";
1115cp.code() += "{ // block\n";
1116cp.code() += "etiss_coverage_count(1, 1448);\n";
1117if (imm % 2ULL) { // conditional
1118cp.code() += "etiss_coverage_count(2, 1451, 1449);\n";
1119{ // block
1120cp.code() += "etiss_coverage_count(1, 1455);\n";
1121cp.code() += "{ // block\n";
1122{ // procedure
1123cp.code() += "{ // procedure\n";
1124cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";
1125cp.code() += "etiss_coverage_count(2, 1454, 1452);\n";
1126cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1127cp.code() += "} // procedure\n";
1128} // procedure
1129cp.code() += "} // block\n";
1130} // block
1131} // conditional
1132else { // conditional
1133{ // block
1134cp.code() += "etiss_coverage_count(1, 1462);\n";
1135cp.code() += "{ // block\n";
1136cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n";
1137cp.code() += "etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";
1138cp.code() += "} // block\n";
1139} // block
1140} // conditional
1141cp.code() += "} // block\n";
1142} // block
1143cp.code() += "} // conditional\n";
1144cp.code() += "} // block\n";
1145} // block
1146cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1147cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1148// -----------------------------------------------------------------------------
1149 cp.getAffectedRegisters().add("instructionPointer", 32);
1150 }
1151 {
1152 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1153
1154 cp.code() = std::string("//BGEU\n");
1155
1156// -----------------------------------------------------------------------------
1157cp.code() += "if (cpu->return_pending || cpu->exception || cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n";
1158// -----------------------------------------------------------------------------
1159 }
1160
1161 return true;
1162 },
1163 0,
1164 [] (BitArray & ba, Instruction & instr)
1165 {
1166// -----------------------------------------------------------------------------
1167etiss_uint16 imm = 0;
1168static BitArrayRange R_imm_11(7, 7);
1169imm += R_imm_11.read(ba) << 11;
1170static BitArrayRange R_imm_1(11, 8);
1171imm += R_imm_1.read(ba) << 1;
1172etiss_uint8 rs1 = 0;
1173static BitArrayRange R_rs1_0(19, 15);
1174rs1 += R_rs1_0.read(ba) << 0;
1175etiss_uint8 rs2 = 0;
1176static BitArrayRange R_rs2_0(24, 20);
1177rs2 += R_rs2_0.read(ba) << 0;
1178static BitArrayRange R_imm_5(30, 25);
1179imm += R_imm_5.read(ba) << 5;
1180static BitArrayRange R_imm_12(31, 31);
1181imm += R_imm_12.read(ba) << 12;
1182
1183// -----------------------------------------------------------------------------
1184
1185 std::stringstream ss;
1186// -----------------------------------------------------------------------------
1187ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1188// -----------------------------------------------------------------------------
1189 return ss.str();
1190 }
1191);
1192
1193// LB --------------------------------------------------------------------------
1194static InstructionDefinition lb_rd_rs1_imm (
1195 ISA32_RV32IMACFD,
1196 "lb",
1197 (uint32_t) 0x000003,
1198 (uint32_t) 0x00707f,
1199 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1200 {
1201
1202// -----------------------------------------------------------------------------
1203
1204// -----------------------------------------------------------------------------
1205
1206// -----------------------------------------------------------------------------
1207etiss_uint8 rd = 0;
1208static BitArrayRange R_rd_0(11, 7);
1209rd += R_rd_0.read(ba) << 0;
1210etiss_uint8 rs1 = 0;
1211static BitArrayRange R_rs1_0(19, 15);
1212rs1 += R_rs1_0.read(ba) << 0;
1213etiss_uint16 imm = 0;
1214static BitArrayRange R_imm_0(31, 20);
1215imm += R_imm_0.read(ba) << 0;
1216
1217// -----------------------------------------------------------------------------
1218
1219 {
1220 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1221
1222 cp.code() = std::string("//LB\n");
1223
1224// -----------------------------------------------------------------------------
1225cp.code() += "etiss_coverage_count(1, 10);\n";
1226{ // block
1227cp.code() += "etiss_coverage_count(1, 1169);\n";
1228cp.code() += "{ // block\n";
1229cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1230cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1231cp.code() += "} // block\n";
1232} // block
1233{ // block
1234cp.code() += "etiss_coverage_count(1, 1498);\n";
1235cp.code() += "{ // block\n";
1236cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1237cp.code() += "etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";
1238cp.code() += "etiss_uint8 mem_val_0;\n";
1239cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1240cp.code() += "if (cpu->exception) { // conditional\n";
1241{ // procedure
1242cp.code() += "{ // procedure\n";
1243cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1244cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1245cp.code() += "} // procedure\n";
1246} // procedure
1247cp.code() += "} // conditional\n";
1248cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n";
1249cp.code() += "etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";
1250cp.code() += "etiss_coverage_count(1, 1482);\n";
1251if ((rd % 32ULL) != 0LL) { // conditional
1252cp.code() += "etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";
1253cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
1254cp.code() += "etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";
1255} // conditional
1256cp.code() += "} // block\n";
1257} // block
1258cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1259cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1260// -----------------------------------------------------------------------------
1261 cp.getAffectedRegisters().add("instructionPointer", 32);
1262 }
1263 {
1264 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1265
1266 cp.code() = std::string("//LB\n");
1267
1268// -----------------------------------------------------------------------------
1269cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1270// -----------------------------------------------------------------------------
1271 }
1272
1273 return true;
1274 },
1275 0,
1276 [] (BitArray & ba, Instruction & instr)
1277 {
1278// -----------------------------------------------------------------------------
1279etiss_uint8 rd = 0;
1280static BitArrayRange R_rd_0(11, 7);
1281rd += R_rd_0.read(ba) << 0;
1282etiss_uint8 rs1 = 0;
1283static BitArrayRange R_rs1_0(19, 15);
1284rs1 += R_rs1_0.read(ba) << 0;
1285etiss_uint16 imm = 0;
1286static BitArrayRange R_imm_0(31, 20);
1287imm += R_imm_0.read(ba) << 0;
1288
1289// -----------------------------------------------------------------------------
1290
1291 std::stringstream ss;
1292// -----------------------------------------------------------------------------
1293ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1294// -----------------------------------------------------------------------------
1295 return ss.str();
1296 }
1297);
1298
1299// LH --------------------------------------------------------------------------
1300static InstructionDefinition lh_rd_rs1_imm (
1301 ISA32_RV32IMACFD,
1302 "lh",
1303 (uint32_t) 0x001003,
1304 (uint32_t) 0x00707f,
1305 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1306 {
1307
1308// -----------------------------------------------------------------------------
1309
1310// -----------------------------------------------------------------------------
1311
1312// -----------------------------------------------------------------------------
1313etiss_uint8 rd = 0;
1314static BitArrayRange R_rd_0(11, 7);
1315rd += R_rd_0.read(ba) << 0;
1316etiss_uint8 rs1 = 0;
1317static BitArrayRange R_rs1_0(19, 15);
1318rs1 += R_rs1_0.read(ba) << 0;
1319etiss_uint16 imm = 0;
1320static BitArrayRange R_imm_0(31, 20);
1321imm += R_imm_0.read(ba) << 0;
1322
1323// -----------------------------------------------------------------------------
1324
1325 {
1326 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1327
1328 cp.code() = std::string("//LH\n");
1329
1330// -----------------------------------------------------------------------------
1331cp.code() += "etiss_coverage_count(1, 11);\n";
1332{ // block
1333cp.code() += "etiss_coverage_count(1, 1169);\n";
1334cp.code() += "{ // block\n";
1335cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1336cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1337cp.code() += "} // block\n";
1338} // block
1339{ // block
1340cp.code() += "etiss_coverage_count(1, 1532);\n";
1341cp.code() += "{ // block\n";
1342cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1343cp.code() += "etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";
1344cp.code() += "etiss_uint16 mem_val_0;\n";
1345cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1346cp.code() += "if (cpu->exception) { // conditional\n";
1347{ // procedure
1348cp.code() += "{ // procedure\n";
1349cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1350cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1351cp.code() += "} // procedure\n";
1352} // procedure
1353cp.code() += "} // conditional\n";
1354cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n";
1355cp.code() += "etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";
1356cp.code() += "etiss_coverage_count(1, 1516);\n";
1357if ((rd % 32ULL) != 0LL) { // conditional
1358cp.code() += "etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";
1359cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
1360cp.code() += "etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";
1361} // conditional
1362cp.code() += "} // block\n";
1363} // block
1364cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1365cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1366// -----------------------------------------------------------------------------
1367 cp.getAffectedRegisters().add("instructionPointer", 32);
1368 }
1369 {
1370 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1371
1372 cp.code() = std::string("//LH\n");
1373
1374// -----------------------------------------------------------------------------
1375cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1376// -----------------------------------------------------------------------------
1377 }
1378
1379 return true;
1380 },
1381 0,
1382 [] (BitArray & ba, Instruction & instr)
1383 {
1384// -----------------------------------------------------------------------------
1385etiss_uint8 rd = 0;
1386static BitArrayRange R_rd_0(11, 7);
1387rd += R_rd_0.read(ba) << 0;
1388etiss_uint8 rs1 = 0;
1389static BitArrayRange R_rs1_0(19, 15);
1390rs1 += R_rs1_0.read(ba) << 0;
1391etiss_uint16 imm = 0;
1392static BitArrayRange R_imm_0(31, 20);
1393imm += R_imm_0.read(ba) << 0;
1394
1395// -----------------------------------------------------------------------------
1396
1397 std::stringstream ss;
1398// -----------------------------------------------------------------------------
1399ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1400// -----------------------------------------------------------------------------
1401 return ss.str();
1402 }
1403);
1404
1405// LW --------------------------------------------------------------------------
1406static InstructionDefinition lw_rd_rs1_imm (
1407 ISA32_RV32IMACFD,
1408 "lw",
1409 (uint32_t) 0x002003,
1410 (uint32_t) 0x00707f,
1411 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1412 {
1413
1414// -----------------------------------------------------------------------------
1415
1416// -----------------------------------------------------------------------------
1417
1418// -----------------------------------------------------------------------------
1419etiss_uint8 rd = 0;
1420static BitArrayRange R_rd_0(11, 7);
1421rd += R_rd_0.read(ba) << 0;
1422etiss_uint8 rs1 = 0;
1423static BitArrayRange R_rs1_0(19, 15);
1424rs1 += R_rs1_0.read(ba) << 0;
1425etiss_uint16 imm = 0;
1426static BitArrayRange R_imm_0(31, 20);
1427imm += R_imm_0.read(ba) << 0;
1428
1429// -----------------------------------------------------------------------------
1430
1431 {
1432 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1433
1434 cp.code() = std::string("//LW\n");
1435
1436// -----------------------------------------------------------------------------
1437cp.code() += "etiss_coverage_count(1, 12);\n";
1438{ // block
1439cp.code() += "etiss_coverage_count(1, 1169);\n";
1440cp.code() += "{ // block\n";
1441cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1442cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1443cp.code() += "} // block\n";
1444} // block
1445{ // block
1446cp.code() += "etiss_coverage_count(1, 1566);\n";
1447cp.code() += "{ // block\n";
1448cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1449cp.code() += "etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";
1450cp.code() += "etiss_uint32 mem_val_0;\n";
1451cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
1452cp.code() += "if (cpu->exception) { // conditional\n";
1453{ // procedure
1454cp.code() += "{ // procedure\n";
1455cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1456cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1457cp.code() += "} // procedure\n";
1458} // procedure
1459cp.code() += "} // conditional\n";
1460cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
1461cp.code() += "etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";
1462cp.code() += "etiss_coverage_count(1, 1550);\n";
1463if ((rd % 32ULL) != 0LL) { // conditional
1464cp.code() += "etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";
1465cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
1466cp.code() += "etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";
1467} // conditional
1468cp.code() += "} // block\n";
1469} // block
1470cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1471cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1472// -----------------------------------------------------------------------------
1473 cp.getAffectedRegisters().add("instructionPointer", 32);
1474 }
1475 {
1476 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1477
1478 cp.code() = std::string("//LW\n");
1479
1480// -----------------------------------------------------------------------------
1481cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1482// -----------------------------------------------------------------------------
1483 }
1484
1485 return true;
1486 },
1487 0,
1488 [] (BitArray & ba, Instruction & instr)
1489 {
1490// -----------------------------------------------------------------------------
1491etiss_uint8 rd = 0;
1492static BitArrayRange R_rd_0(11, 7);
1493rd += R_rd_0.read(ba) << 0;
1494etiss_uint8 rs1 = 0;
1495static BitArrayRange R_rs1_0(19, 15);
1496rs1 += R_rs1_0.read(ba) << 0;
1497etiss_uint16 imm = 0;
1498static BitArrayRange R_imm_0(31, 20);
1499imm += R_imm_0.read(ba) << 0;
1500
1501// -----------------------------------------------------------------------------
1502
1503 std::stringstream ss;
1504// -----------------------------------------------------------------------------
1505ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1506// -----------------------------------------------------------------------------
1507 return ss.str();
1508 }
1509);
1510
1511// LBU -------------------------------------------------------------------------
1512static InstructionDefinition lbu_rd_rs1_imm (
1513 ISA32_RV32IMACFD,
1514 "lbu",
1515 (uint32_t) 0x004003,
1516 (uint32_t) 0x00707f,
1517 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1518 {
1519
1520// -----------------------------------------------------------------------------
1521
1522// -----------------------------------------------------------------------------
1523
1524// -----------------------------------------------------------------------------
1525etiss_uint8 rd = 0;
1526static BitArrayRange R_rd_0(11, 7);
1527rd += R_rd_0.read(ba) << 0;
1528etiss_uint8 rs1 = 0;
1529static BitArrayRange R_rs1_0(19, 15);
1530rs1 += R_rs1_0.read(ba) << 0;
1531etiss_uint16 imm = 0;
1532static BitArrayRange R_imm_0(31, 20);
1533imm += R_imm_0.read(ba) << 0;
1534
1535// -----------------------------------------------------------------------------
1536
1537 {
1538 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1539
1540 cp.code() = std::string("//LBU\n");
1541
1542// -----------------------------------------------------------------------------
1543cp.code() += "etiss_coverage_count(1, 13);\n";
1544{ // block
1545cp.code() += "etiss_coverage_count(1, 1169);\n";
1546cp.code() += "{ // block\n";
1547cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1548cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1549cp.code() += "} // block\n";
1550} // block
1551{ // block
1552cp.code() += "etiss_coverage_count(1, 1600);\n";
1553cp.code() += "{ // block\n";
1554cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1555cp.code() += "etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";
1556cp.code() += "etiss_uint8 mem_val_0;\n";
1557cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";
1558cp.code() += "if (cpu->exception) { // conditional\n";
1559{ // procedure
1560cp.code() += "{ // procedure\n";
1561cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1562cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1563cp.code() += "} // procedure\n";
1564} // procedure
1565cp.code() += "} // conditional\n";
1566cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";
1567cp.code() += "etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";
1568cp.code() += "etiss_coverage_count(1, 1584);\n";
1569if ((rd % 32ULL) != 0LL) { // conditional
1570cp.code() += "etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";
1571cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
1572cp.code() += "etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";
1573} // conditional
1574cp.code() += "} // block\n";
1575} // block
1576cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1577cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1578// -----------------------------------------------------------------------------
1579 cp.getAffectedRegisters().add("instructionPointer", 32);
1580 }
1581 {
1582 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1583
1584 cp.code() = std::string("//LBU\n");
1585
1586// -----------------------------------------------------------------------------
1587cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1588// -----------------------------------------------------------------------------
1589 }
1590
1591 return true;
1592 },
1593 0,
1594 [] (BitArray & ba, Instruction & instr)
1595 {
1596// -----------------------------------------------------------------------------
1597etiss_uint8 rd = 0;
1598static BitArrayRange R_rd_0(11, 7);
1599rd += R_rd_0.read(ba) << 0;
1600etiss_uint8 rs1 = 0;
1601static BitArrayRange R_rs1_0(19, 15);
1602rs1 += R_rs1_0.read(ba) << 0;
1603etiss_uint16 imm = 0;
1604static BitArrayRange R_imm_0(31, 20);
1605imm += R_imm_0.read(ba) << 0;
1606
1607// -----------------------------------------------------------------------------
1608
1609 std::stringstream ss;
1610// -----------------------------------------------------------------------------
1611ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1612// -----------------------------------------------------------------------------
1613 return ss.str();
1614 }
1615);
1616
1617// LHU -------------------------------------------------------------------------
1618static InstructionDefinition lhu_rd_rs1_imm (
1619 ISA32_RV32IMACFD,
1620 "lhu",
1621 (uint32_t) 0x005003,
1622 (uint32_t) 0x00707f,
1623 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1624 {
1625
1626// -----------------------------------------------------------------------------
1627
1628// -----------------------------------------------------------------------------
1629
1630// -----------------------------------------------------------------------------
1631etiss_uint8 rd = 0;
1632static BitArrayRange R_rd_0(11, 7);
1633rd += R_rd_0.read(ba) << 0;
1634etiss_uint8 rs1 = 0;
1635static BitArrayRange R_rs1_0(19, 15);
1636rs1 += R_rs1_0.read(ba) << 0;
1637etiss_uint16 imm = 0;
1638static BitArrayRange R_imm_0(31, 20);
1639imm += R_imm_0.read(ba) << 0;
1640
1641// -----------------------------------------------------------------------------
1642
1643 {
1644 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1645
1646 cp.code() = std::string("//LHU\n");
1647
1648// -----------------------------------------------------------------------------
1649cp.code() += "etiss_coverage_count(1, 14);\n";
1650{ // block
1651cp.code() += "etiss_coverage_count(1, 1169);\n";
1652cp.code() += "{ // block\n";
1653cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1654cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1655cp.code() += "} // block\n";
1656} // block
1657{ // block
1658cp.code() += "etiss_coverage_count(1, 1634);\n";
1659cp.code() += "{ // block\n";
1660cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1661cp.code() += "etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";
1662cp.code() += "etiss_uint16 mem_val_0;\n";
1663cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";
1664cp.code() += "if (cpu->exception) { // conditional\n";
1665{ // procedure
1666cp.code() += "{ // procedure\n";
1667cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1668cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1669cp.code() += "} // procedure\n";
1670} // procedure
1671cp.code() += "} // conditional\n";
1672cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";
1673cp.code() += "etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";
1674cp.code() += "etiss_coverage_count(1, 1618);\n";
1675if ((rd % 32ULL) != 0LL) { // conditional
1676cp.code() += "etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";
1677cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
1678cp.code() += "etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";
1679} // conditional
1680cp.code() += "} // block\n";
1681} // block
1682cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1683cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1684// -----------------------------------------------------------------------------
1685 cp.getAffectedRegisters().add("instructionPointer", 32);
1686 }
1687 {
1688 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1689
1690 cp.code() = std::string("//LHU\n");
1691
1692// -----------------------------------------------------------------------------
1693cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1694// -----------------------------------------------------------------------------
1695 }
1696
1697 return true;
1698 },
1699 0,
1700 [] (BitArray & ba, Instruction & instr)
1701 {
1702// -----------------------------------------------------------------------------
1703etiss_uint8 rd = 0;
1704static BitArrayRange R_rd_0(11, 7);
1705rd += R_rd_0.read(ba) << 0;
1706etiss_uint8 rs1 = 0;
1707static BitArrayRange R_rs1_0(19, 15);
1708rs1 += R_rs1_0.read(ba) << 0;
1709etiss_uint16 imm = 0;
1710static BitArrayRange R_imm_0(31, 20);
1711imm += R_imm_0.read(ba) << 0;
1712
1713// -----------------------------------------------------------------------------
1714
1715 std::stringstream ss;
1716// -----------------------------------------------------------------------------
1717ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
1718// -----------------------------------------------------------------------------
1719 return ss.str();
1720 }
1721);
1722
1723// SB --------------------------------------------------------------------------
1724static InstructionDefinition sb_imm_rs1_rs2 (
1725 ISA32_RV32IMACFD,
1726 "sb",
1727 (uint32_t) 0x000023,
1728 (uint32_t) 0x00707f,
1729 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1730 {
1731
1732// -----------------------------------------------------------------------------
1733
1734// -----------------------------------------------------------------------------
1735
1736// -----------------------------------------------------------------------------
1737etiss_uint16 imm = 0;
1738static BitArrayRange R_imm_0(11, 7);
1739imm += R_imm_0.read(ba) << 0;
1740etiss_uint8 rs1 = 0;
1741static BitArrayRange R_rs1_0(19, 15);
1742rs1 += R_rs1_0.read(ba) << 0;
1743etiss_uint8 rs2 = 0;
1744static BitArrayRange R_rs2_0(24, 20);
1745rs2 += R_rs2_0.read(ba) << 0;
1746static BitArrayRange R_imm_5(31, 25);
1747imm += R_imm_5.read(ba) << 5;
1748
1749// -----------------------------------------------------------------------------
1750
1751 {
1752 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1753
1754 cp.code() = std::string("//SB\n");
1755
1756// -----------------------------------------------------------------------------
1757cp.code() += "etiss_coverage_count(1, 15);\n";
1758{ // block
1759cp.code() += "etiss_coverage_count(1, 1169);\n";
1760cp.code() += "{ // block\n";
1761cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1762cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1763cp.code() += "} // block\n";
1764} // block
1765{ // block
1766cp.code() += "etiss_coverage_count(1, 1656);\n";
1767cp.code() += "{ // block\n";
1768cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1769cp.code() += "etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";
1770cp.code() += "etiss_uint8 mem_val_0;\n";
1771cp.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1772cp.code() += "etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";
1773cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";
1774cp.code() += "if (cpu->exception) { // conditional\n";
1775{ // procedure
1776cp.code() += "{ // procedure\n";
1777cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1778cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1779cp.code() += "} // procedure\n";
1780} // procedure
1781cp.code() += "} // conditional\n";
1782cp.code() += "} // block\n";
1783} // block
1784cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1785cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1786// -----------------------------------------------------------------------------
1787 cp.getAffectedRegisters().add("instructionPointer", 32);
1788 }
1789 {
1790 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1791
1792 cp.code() = std::string("//SB\n");
1793
1794// -----------------------------------------------------------------------------
1795cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1796// -----------------------------------------------------------------------------
1797 }
1798
1799 return true;
1800 },
1801 0,
1802 [] (BitArray & ba, Instruction & instr)
1803 {
1804// -----------------------------------------------------------------------------
1805etiss_uint16 imm = 0;
1806static BitArrayRange R_imm_0(11, 7);
1807imm += R_imm_0.read(ba) << 0;
1808etiss_uint8 rs1 = 0;
1809static BitArrayRange R_rs1_0(19, 15);
1810rs1 += R_rs1_0.read(ba) << 0;
1811etiss_uint8 rs2 = 0;
1812static BitArrayRange R_rs2_0(24, 20);
1813rs2 += R_rs2_0.read(ba) << 0;
1814static BitArrayRange R_imm_5(31, 25);
1815imm += R_imm_5.read(ba) << 5;
1816
1817// -----------------------------------------------------------------------------
1818
1819 std::stringstream ss;
1820// -----------------------------------------------------------------------------
1821ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1822// -----------------------------------------------------------------------------
1823 return ss.str();
1824 }
1825);
1826
1827// SH --------------------------------------------------------------------------
1828static InstructionDefinition sh_imm_rs1_rs2 (
1829 ISA32_RV32IMACFD,
1830 "sh",
1831 (uint32_t) 0x001023,
1832 (uint32_t) 0x00707f,
1833 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1834 {
1835
1836// -----------------------------------------------------------------------------
1837
1838// -----------------------------------------------------------------------------
1839
1840// -----------------------------------------------------------------------------
1841etiss_uint16 imm = 0;
1842static BitArrayRange R_imm_0(11, 7);
1843imm += R_imm_0.read(ba) << 0;
1844etiss_uint8 rs1 = 0;
1845static BitArrayRange R_rs1_0(19, 15);
1846rs1 += R_rs1_0.read(ba) << 0;
1847etiss_uint8 rs2 = 0;
1848static BitArrayRange R_rs2_0(24, 20);
1849rs2 += R_rs2_0.read(ba) << 0;
1850static BitArrayRange R_imm_5(31, 25);
1851imm += R_imm_5.read(ba) << 5;
1852
1853// -----------------------------------------------------------------------------
1854
1855 {
1856 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1857
1858 cp.code() = std::string("//SH\n");
1859
1860// -----------------------------------------------------------------------------
1861cp.code() += "etiss_coverage_count(1, 16);\n";
1862{ // block
1863cp.code() += "etiss_coverage_count(1, 1169);\n";
1864cp.code() += "{ // block\n";
1865cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1866cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1867cp.code() += "} // block\n";
1868} // block
1869{ // block
1870cp.code() += "etiss_coverage_count(1, 1678);\n";
1871cp.code() += "{ // block\n";
1872cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1873cp.code() += "etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";
1874cp.code() += "etiss_uint16 mem_val_0;\n";
1875cp.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1876cp.code() += "etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";
1877cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";
1878cp.code() += "if (cpu->exception) { // conditional\n";
1879{ // procedure
1880cp.code() += "{ // procedure\n";
1881cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1882cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1883cp.code() += "} // procedure\n";
1884} // procedure
1885cp.code() += "} // conditional\n";
1886cp.code() += "} // block\n";
1887} // block
1888cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1889cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1890// -----------------------------------------------------------------------------
1891 cp.getAffectedRegisters().add("instructionPointer", 32);
1892 }
1893 {
1894 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1895
1896 cp.code() = std::string("//SH\n");
1897
1898// -----------------------------------------------------------------------------
1899cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1900// -----------------------------------------------------------------------------
1901 }
1902
1903 return true;
1904 },
1905 0,
1906 [] (BitArray & ba, Instruction & instr)
1907 {
1908// -----------------------------------------------------------------------------
1909etiss_uint16 imm = 0;
1910static BitArrayRange R_imm_0(11, 7);
1911imm += R_imm_0.read(ba) << 0;
1912etiss_uint8 rs1 = 0;
1913static BitArrayRange R_rs1_0(19, 15);
1914rs1 += R_rs1_0.read(ba) << 0;
1915etiss_uint8 rs2 = 0;
1916static BitArrayRange R_rs2_0(24, 20);
1917rs2 += R_rs2_0.read(ba) << 0;
1918static BitArrayRange R_imm_5(31, 25);
1919imm += R_imm_5.read(ba) << 5;
1920
1921// -----------------------------------------------------------------------------
1922
1923 std::stringstream ss;
1924// -----------------------------------------------------------------------------
1925ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1926// -----------------------------------------------------------------------------
1927 return ss.str();
1928 }
1929);
1930
1931// SW --------------------------------------------------------------------------
1932static InstructionDefinition sw_imm_rs1_rs2 (
1933 ISA32_RV32IMACFD,
1934 "sw",
1935 (uint32_t) 0x002023,
1936 (uint32_t) 0x00707f,
1937 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1938 {
1939
1940// -----------------------------------------------------------------------------
1941
1942// -----------------------------------------------------------------------------
1943
1944// -----------------------------------------------------------------------------
1945etiss_uint16 imm = 0;
1946static BitArrayRange R_imm_0(11, 7);
1947imm += R_imm_0.read(ba) << 0;
1948etiss_uint8 rs1 = 0;
1949static BitArrayRange R_rs1_0(19, 15);
1950rs1 += R_rs1_0.read(ba) << 0;
1951etiss_uint8 rs2 = 0;
1952static BitArrayRange R_rs2_0(24, 20);
1953rs2 += R_rs2_0.read(ba) << 0;
1954static BitArrayRange R_imm_5(31, 25);
1955imm += R_imm_5.read(ba) << 5;
1956
1957// -----------------------------------------------------------------------------
1958
1959 {
1960 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1961
1962 cp.code() = std::string("//SW\n");
1963
1964// -----------------------------------------------------------------------------
1965cp.code() += "etiss_coverage_count(1, 17);\n";
1966{ // block
1967cp.code() += "etiss_coverage_count(1, 1169);\n";
1968cp.code() += "{ // block\n";
1969cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1970cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1971cp.code() += "} // block\n";
1972} // block
1973{ // block
1974cp.code() += "etiss_coverage_count(1, 1700);\n";
1975cp.code() += "{ // block\n";
1976cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1977cp.code() += "etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";
1978cp.code() += "etiss_uint32 mem_val_0;\n";
1979cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1980cp.code() += "etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";
1981cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";
1982cp.code() += "if (cpu->exception) { // conditional\n";
1983{ // procedure
1984cp.code() += "{ // procedure\n";
1985cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1986cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1987cp.code() += "} // procedure\n";
1988} // procedure
1989cp.code() += "} // conditional\n";
1990cp.code() += "} // block\n";
1991} // block
1992cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1993cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1994// -----------------------------------------------------------------------------
1995 cp.getAffectedRegisters().add("instructionPointer", 32);
1996 }
1997 {
1998 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1999
2000 cp.code() = std::string("//SW\n");
2001
2002// -----------------------------------------------------------------------------
2003cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2004// -----------------------------------------------------------------------------
2005 }
2006
2007 return true;
2008 },
2009 0,
2010 [] (BitArray & ba, Instruction & instr)
2011 {
2012// -----------------------------------------------------------------------------
2013etiss_uint16 imm = 0;
2014static BitArrayRange R_imm_0(11, 7);
2015imm += R_imm_0.read(ba) << 0;
2016etiss_uint8 rs1 = 0;
2017static BitArrayRange R_rs1_0(19, 15);
2018rs1 += R_rs1_0.read(ba) << 0;
2019etiss_uint8 rs2 = 0;
2020static BitArrayRange R_rs2_0(24, 20);
2021rs2 += R_rs2_0.read(ba) << 0;
2022static BitArrayRange R_imm_5(31, 25);
2023imm += R_imm_5.read(ba) << 5;
2024
2025// -----------------------------------------------------------------------------
2026
2027 std::stringstream ss;
2028// -----------------------------------------------------------------------------
2029ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2030// -----------------------------------------------------------------------------
2031 return ss.str();
2032 }
2033);
2034
2035// ADDI ------------------------------------------------------------------------
2036static InstructionDefinition addi_rd_rs1_imm (
2037 ISA32_RV32IMACFD,
2038 "addi",
2039 (uint32_t) 0x000013,
2040 (uint32_t) 0x00707f,
2041 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2042 {
2043
2044// -----------------------------------------------------------------------------
2045
2046// -----------------------------------------------------------------------------
2047
2048// -----------------------------------------------------------------------------
2049etiss_uint8 rd = 0;
2050static BitArrayRange R_rd_0(11, 7);
2051rd += R_rd_0.read(ba) << 0;
2052etiss_uint8 rs1 = 0;
2053static BitArrayRange R_rs1_0(19, 15);
2054rs1 += R_rs1_0.read(ba) << 0;
2055etiss_uint16 imm = 0;
2056static BitArrayRange R_imm_0(31, 20);
2057imm += R_imm_0.read(ba) << 0;
2058
2059// -----------------------------------------------------------------------------
2060
2061 {
2062 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2063
2064 cp.code() = std::string("//ADDI\n");
2065
2066// -----------------------------------------------------------------------------
2067cp.code() += "etiss_coverage_count(1, 18);\n";
2068{ // block
2069cp.code() += "etiss_coverage_count(1, 1169);\n";
2070cp.code() += "{ // block\n";
2071cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2072cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2073cp.code() += "} // block\n";
2074} // block
2075cp.code() += "etiss_coverage_count(1, 1701);\n";
2076if ((rd % 32ULL) != 0LL) { // conditional
2077cp.code() += "etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";
2078cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
2079cp.code() += "etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";
2080} // conditional
2081cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2082cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2083// -----------------------------------------------------------------------------
2084 cp.getAffectedRegisters().add("instructionPointer", 32);
2085 }
2086
2087 return true;
2088 },
2089 0,
2090 [] (BitArray & ba, Instruction & instr)
2091 {
2092// -----------------------------------------------------------------------------
2093etiss_uint8 rd = 0;
2094static BitArrayRange R_rd_0(11, 7);
2095rd += R_rd_0.read(ba) << 0;
2096etiss_uint8 rs1 = 0;
2097static BitArrayRange R_rs1_0(19, 15);
2098rs1 += R_rs1_0.read(ba) << 0;
2099etiss_uint16 imm = 0;
2100static BitArrayRange R_imm_0(31, 20);
2101imm += R_imm_0.read(ba) << 0;
2102
2103// -----------------------------------------------------------------------------
2104
2105 std::stringstream ss;
2106// -----------------------------------------------------------------------------
2107ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2108// -----------------------------------------------------------------------------
2109 return ss.str();
2110 }
2111);
2112
2113// SLTI ------------------------------------------------------------------------
2114static InstructionDefinition slti_rd_rs1_imm (
2115 ISA32_RV32IMACFD,
2116 "slti",
2117 (uint32_t) 0x002013,
2118 (uint32_t) 0x00707f,
2119 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2120 {
2121
2122// -----------------------------------------------------------------------------
2123
2124// -----------------------------------------------------------------------------
2125
2126// -----------------------------------------------------------------------------
2127etiss_uint8 rd = 0;
2128static BitArrayRange R_rd_0(11, 7);
2129rd += R_rd_0.read(ba) << 0;
2130etiss_uint8 rs1 = 0;
2131static BitArrayRange R_rs1_0(19, 15);
2132rs1 += R_rs1_0.read(ba) << 0;
2133etiss_uint16 imm = 0;
2134static BitArrayRange R_imm_0(31, 20);
2135imm += R_imm_0.read(ba) << 0;
2136
2137// -----------------------------------------------------------------------------
2138
2139 {
2140 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2141
2142 cp.code() = std::string("//SLTI\n");
2143
2144// -----------------------------------------------------------------------------
2145cp.code() += "etiss_coverage_count(1, 19);\n";
2146{ // block
2147cp.code() += "etiss_coverage_count(1, 1169);\n";
2148cp.code() += "{ // block\n";
2149cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2150cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2151cp.code() += "} // block\n";
2152} // block
2153cp.code() += "etiss_coverage_count(1, 1722);\n";
2154if ((rd % 32ULL) != 0LL) { // conditional
2155cp.code() += "etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";
2156cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0LL);\n";
2157cp.code() += "etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";
2158} // conditional
2159cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2160cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2161// -----------------------------------------------------------------------------
2162 cp.getAffectedRegisters().add("instructionPointer", 32);
2163 }
2164
2165 return true;
2166 },
2167 0,
2168 [] (BitArray & ba, Instruction & instr)
2169 {
2170// -----------------------------------------------------------------------------
2171etiss_uint8 rd = 0;
2172static BitArrayRange R_rd_0(11, 7);
2173rd += R_rd_0.read(ba) << 0;
2174etiss_uint8 rs1 = 0;
2175static BitArrayRange R_rs1_0(19, 15);
2176rs1 += R_rs1_0.read(ba) << 0;
2177etiss_uint16 imm = 0;
2178static BitArrayRange R_imm_0(31, 20);
2179imm += R_imm_0.read(ba) << 0;
2180
2181// -----------------------------------------------------------------------------
2182
2183 std::stringstream ss;
2184// -----------------------------------------------------------------------------
2185ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2186// -----------------------------------------------------------------------------
2187 return ss.str();
2188 }
2189);
2190
2191// SLTIU -----------------------------------------------------------------------
2192static InstructionDefinition sltiu_rd_rs1_imm (
2193 ISA32_RV32IMACFD,
2194 "sltiu",
2195 (uint32_t) 0x003013,
2196 (uint32_t) 0x00707f,
2197 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2198 {
2199
2200// -----------------------------------------------------------------------------
2201
2202// -----------------------------------------------------------------------------
2203
2204// -----------------------------------------------------------------------------
2205etiss_uint8 rd = 0;
2206static BitArrayRange R_rd_0(11, 7);
2207rd += R_rd_0.read(ba) << 0;
2208etiss_uint8 rs1 = 0;
2209static BitArrayRange R_rs1_0(19, 15);
2210rs1 += R_rs1_0.read(ba) << 0;
2211etiss_uint16 imm = 0;
2212static BitArrayRange R_imm_0(31, 20);
2213imm += R_imm_0.read(ba) << 0;
2214
2215// -----------------------------------------------------------------------------
2216
2217 {
2218 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2219
2220 cp.code() = std::string("//SLTIU\n");
2221
2222// -----------------------------------------------------------------------------
2223cp.code() += "etiss_coverage_count(1, 20);\n";
2224{ // block
2225cp.code() += "etiss_coverage_count(1, 1169);\n";
2226cp.code() += "{ // block\n";
2227cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2228cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2229cp.code() += "} // block\n";
2230} // block
2231cp.code() += "etiss_coverage_count(1, 1748);\n";
2232if ((rd % 32ULL) != 0LL) { // conditional
2233cp.code() += "etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";
2234cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0LL);\n";
2235cp.code() += "etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";
2236} // conditional
2237cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2238cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2239// -----------------------------------------------------------------------------
2240 cp.getAffectedRegisters().add("instructionPointer", 32);
2241 }
2242
2243 return true;
2244 },
2245 0,
2246 [] (BitArray & ba, Instruction & instr)
2247 {
2248// -----------------------------------------------------------------------------
2249etiss_uint8 rd = 0;
2250static BitArrayRange R_rd_0(11, 7);
2251rd += R_rd_0.read(ba) << 0;
2252etiss_uint8 rs1 = 0;
2253static BitArrayRange R_rs1_0(19, 15);
2254rs1 += R_rs1_0.read(ba) << 0;
2255etiss_uint16 imm = 0;
2256static BitArrayRange R_imm_0(31, 20);
2257imm += R_imm_0.read(ba) << 0;
2258
2259// -----------------------------------------------------------------------------
2260
2261 std::stringstream ss;
2262// -----------------------------------------------------------------------------
2263ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2264// -----------------------------------------------------------------------------
2265 return ss.str();
2266 }
2267);
2268
2269// XORI ------------------------------------------------------------------------
2270static InstructionDefinition xori_rd_rs1_imm (
2271 ISA32_RV32IMACFD,
2272 "xori",
2273 (uint32_t) 0x004013,
2274 (uint32_t) 0x00707f,
2275 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2276 {
2277
2278// -----------------------------------------------------------------------------
2279
2280// -----------------------------------------------------------------------------
2281
2282// -----------------------------------------------------------------------------
2283etiss_uint8 rd = 0;
2284static BitArrayRange R_rd_0(11, 7);
2285rd += R_rd_0.read(ba) << 0;
2286etiss_uint8 rs1 = 0;
2287static BitArrayRange R_rs1_0(19, 15);
2288rs1 += R_rs1_0.read(ba) << 0;
2289etiss_uint16 imm = 0;
2290static BitArrayRange R_imm_0(31, 20);
2291imm += R_imm_0.read(ba) << 0;
2292
2293// -----------------------------------------------------------------------------
2294
2295 {
2296 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2297
2298 cp.code() = std::string("//XORI\n");
2299
2300// -----------------------------------------------------------------------------
2301cp.code() += "etiss_coverage_count(1, 21);\n";
2302{ // block
2303cp.code() += "etiss_coverage_count(1, 1169);\n";
2304cp.code() += "{ // block\n";
2305cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2306cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2307cp.code() += "} // block\n";
2308} // block
2309cp.code() += "etiss_coverage_count(1, 1776);\n";
2310if ((rd % 32ULL) != 0LL) { // conditional
2311cp.code() += "etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";
2312cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2313cp.code() += "etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";
2314} // conditional
2315cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2316cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2317// -----------------------------------------------------------------------------
2318 cp.getAffectedRegisters().add("instructionPointer", 32);
2319 }
2320
2321 return true;
2322 },
2323 0,
2324 [] (BitArray & ba, Instruction & instr)
2325 {
2326// -----------------------------------------------------------------------------
2327etiss_uint8 rd = 0;
2328static BitArrayRange R_rd_0(11, 7);
2329rd += R_rd_0.read(ba) << 0;
2330etiss_uint8 rs1 = 0;
2331static BitArrayRange R_rs1_0(19, 15);
2332rs1 += R_rs1_0.read(ba) << 0;
2333etiss_uint16 imm = 0;
2334static BitArrayRange R_imm_0(31, 20);
2335imm += R_imm_0.read(ba) << 0;
2336
2337// -----------------------------------------------------------------------------
2338
2339 std::stringstream ss;
2340// -----------------------------------------------------------------------------
2341ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2342// -----------------------------------------------------------------------------
2343 return ss.str();
2344 }
2345);
2346
2347// ORI -------------------------------------------------------------------------
2348static InstructionDefinition ori_rd_rs1_imm (
2349 ISA32_RV32IMACFD,
2350 "ori",
2351 (uint32_t) 0x006013,
2352 (uint32_t) 0x00707f,
2353 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2354 {
2355
2356// -----------------------------------------------------------------------------
2357
2358// -----------------------------------------------------------------------------
2359
2360// -----------------------------------------------------------------------------
2361etiss_uint8 rd = 0;
2362static BitArrayRange R_rd_0(11, 7);
2363rd += R_rd_0.read(ba) << 0;
2364etiss_uint8 rs1 = 0;
2365static BitArrayRange R_rs1_0(19, 15);
2366rs1 += R_rs1_0.read(ba) << 0;
2367etiss_uint16 imm = 0;
2368static BitArrayRange R_imm_0(31, 20);
2369imm += R_imm_0.read(ba) << 0;
2370
2371// -----------------------------------------------------------------------------
2372
2373 {
2374 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2375
2376 cp.code() = std::string("//ORI\n");
2377
2378// -----------------------------------------------------------------------------
2379cp.code() += "etiss_coverage_count(1, 22);\n";
2380{ // block
2381cp.code() += "etiss_coverage_count(1, 1169);\n";
2382cp.code() += "{ // block\n";
2383cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2384cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2385cp.code() += "} // block\n";
2386} // block
2387cp.code() += "etiss_coverage_count(1, 1800);\n";
2388if ((rd % 32ULL) != 0LL) { // conditional
2389cp.code() += "etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";
2390cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2391cp.code() += "etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";
2392} // conditional
2393cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2394cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2395// -----------------------------------------------------------------------------
2396 cp.getAffectedRegisters().add("instructionPointer", 32);
2397 }
2398
2399 return true;
2400 },
2401 0,
2402 [] (BitArray & ba, Instruction & instr)
2403 {
2404// -----------------------------------------------------------------------------
2405etiss_uint8 rd = 0;
2406static BitArrayRange R_rd_0(11, 7);
2407rd += R_rd_0.read(ba) << 0;
2408etiss_uint8 rs1 = 0;
2409static BitArrayRange R_rs1_0(19, 15);
2410rs1 += R_rs1_0.read(ba) << 0;
2411etiss_uint16 imm = 0;
2412static BitArrayRange R_imm_0(31, 20);
2413imm += R_imm_0.read(ba) << 0;
2414
2415// -----------------------------------------------------------------------------
2416
2417 std::stringstream ss;
2418// -----------------------------------------------------------------------------
2419ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2420// -----------------------------------------------------------------------------
2421 return ss.str();
2422 }
2423);
2424
2425// ANDI ------------------------------------------------------------------------
2426static InstructionDefinition andi_rd_rs1_imm (
2427 ISA32_RV32IMACFD,
2428 "andi",
2429 (uint32_t) 0x007013,
2430 (uint32_t) 0x00707f,
2431 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2432 {
2433
2434// -----------------------------------------------------------------------------
2435
2436// -----------------------------------------------------------------------------
2437
2438// -----------------------------------------------------------------------------
2439etiss_uint8 rd = 0;
2440static BitArrayRange R_rd_0(11, 7);
2441rd += R_rd_0.read(ba) << 0;
2442etiss_uint8 rs1 = 0;
2443static BitArrayRange R_rs1_0(19, 15);
2444rs1 += R_rs1_0.read(ba) << 0;
2445etiss_uint16 imm = 0;
2446static BitArrayRange R_imm_0(31, 20);
2447imm += R_imm_0.read(ba) << 0;
2448
2449// -----------------------------------------------------------------------------
2450
2451 {
2452 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2453
2454 cp.code() = std::string("//ANDI\n");
2455
2456// -----------------------------------------------------------------------------
2457cp.code() += "etiss_coverage_count(1, 23);\n";
2458{ // block
2459cp.code() += "etiss_coverage_count(1, 1169);\n";
2460cp.code() += "{ // block\n";
2461cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2462cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2463cp.code() += "} // block\n";
2464} // block
2465cp.code() += "etiss_coverage_count(1, 1824);\n";
2466if ((rd % 32ULL) != 0LL) { // conditional
2467cp.code() += "etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";
2468cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n";
2469cp.code() += "etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";
2470} // conditional
2471cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2472cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2473// -----------------------------------------------------------------------------
2474 cp.getAffectedRegisters().add("instructionPointer", 32);
2475 }
2476
2477 return true;
2478 },
2479 0,
2480 [] (BitArray & ba, Instruction & instr)
2481 {
2482// -----------------------------------------------------------------------------
2483etiss_uint8 rd = 0;
2484static BitArrayRange R_rd_0(11, 7);
2485rd += R_rd_0.read(ba) << 0;
2486etiss_uint8 rs1 = 0;
2487static BitArrayRange R_rs1_0(19, 15);
2488rs1 += R_rs1_0.read(ba) << 0;
2489etiss_uint16 imm = 0;
2490static BitArrayRange R_imm_0(31, 20);
2491imm += R_imm_0.read(ba) << 0;
2492
2493// -----------------------------------------------------------------------------
2494
2495 std::stringstream ss;
2496// -----------------------------------------------------------------------------
2497ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
2498// -----------------------------------------------------------------------------
2499 return ss.str();
2500 }
2501);
2502
2503// SLLI ------------------------------------------------------------------------
2504static InstructionDefinition slli_rd_rs1_shamt (
2505 ISA32_RV32IMACFD,
2506 "slli",
2507 (uint32_t) 0x001013,
2508 (uint32_t) 0xfe00707f,
2509 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2510 {
2511
2512// -----------------------------------------------------------------------------
2513
2514// -----------------------------------------------------------------------------
2515
2516// -----------------------------------------------------------------------------
2517etiss_uint8 rd = 0;
2518static BitArrayRange R_rd_0(11, 7);
2519rd += R_rd_0.read(ba) << 0;
2520etiss_uint8 rs1 = 0;
2521static BitArrayRange R_rs1_0(19, 15);
2522rs1 += R_rs1_0.read(ba) << 0;
2523etiss_uint8 shamt = 0;
2524static BitArrayRange R_shamt_0(24, 20);
2525shamt += R_shamt_0.read(ba) << 0;
2526
2527// -----------------------------------------------------------------------------
2528
2529 {
2530 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2531
2532 cp.code() = std::string("//SLLI\n");
2533
2534// -----------------------------------------------------------------------------
2535cp.code() += "etiss_coverage_count(1, 24);\n";
2536{ // block
2537cp.code() += "etiss_coverage_count(1, 1169);\n";
2538cp.code() += "{ // block\n";
2539cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2540cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2541cp.code() += "} // block\n";
2542} // block
2543cp.code() += "etiss_coverage_count(1, 1848);\n";
2544if ((rd % 32ULL) != 0LL) { // conditional
2545cp.code() += "etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";
2546cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
2547cp.code() += "etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";
2548} // conditional
2549cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2550cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2551// -----------------------------------------------------------------------------
2552 cp.getAffectedRegisters().add("instructionPointer", 32);
2553 }
2554
2555 return true;
2556 },
2557 0,
2558 [] (BitArray & ba, Instruction & instr)
2559 {
2560// -----------------------------------------------------------------------------
2561etiss_uint8 rd = 0;
2562static BitArrayRange R_rd_0(11, 7);
2563rd += R_rd_0.read(ba) << 0;
2564etiss_uint8 rs1 = 0;
2565static BitArrayRange R_rs1_0(19, 15);
2566rs1 += R_rs1_0.read(ba) << 0;
2567etiss_uint8 shamt = 0;
2568static BitArrayRange R_shamt_0(24, 20);
2569shamt += R_shamt_0.read(ba) << 0;
2570
2571// -----------------------------------------------------------------------------
2572
2573 std::stringstream ss;
2574// -----------------------------------------------------------------------------
2575ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2576// -----------------------------------------------------------------------------
2577 return ss.str();
2578 }
2579);
2580
2581// SRLI ------------------------------------------------------------------------
2582static InstructionDefinition srli_rd_rs1_shamt (
2583 ISA32_RV32IMACFD,
2584 "srli",
2585 (uint32_t) 0x005013,
2586 (uint32_t) 0xfe00707f,
2587 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2588 {
2589
2590// -----------------------------------------------------------------------------
2591
2592// -----------------------------------------------------------------------------
2593
2594// -----------------------------------------------------------------------------
2595etiss_uint8 rd = 0;
2596static BitArrayRange R_rd_0(11, 7);
2597rd += R_rd_0.read(ba) << 0;
2598etiss_uint8 rs1 = 0;
2599static BitArrayRange R_rs1_0(19, 15);
2600rs1 += R_rs1_0.read(ba) << 0;
2601etiss_uint8 shamt = 0;
2602static BitArrayRange R_shamt_0(24, 20);
2603shamt += R_shamt_0.read(ba) << 0;
2604
2605// -----------------------------------------------------------------------------
2606
2607 {
2608 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2609
2610 cp.code() = std::string("//SRLI\n");
2611
2612// -----------------------------------------------------------------------------
2613cp.code() += "etiss_coverage_count(1, 25);\n";
2614{ // block
2615cp.code() += "etiss_coverage_count(1, 1169);\n";
2616cp.code() += "{ // block\n";
2617cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2618cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2619cp.code() += "} // block\n";
2620} // block
2621cp.code() += "etiss_coverage_count(1, 1868);\n";
2622if ((rd % 32ULL) != 0LL) { // conditional
2623cp.code() += "etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";
2624cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
2625cp.code() += "etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";
2626} // conditional
2627cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2628cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2629// -----------------------------------------------------------------------------
2630 cp.getAffectedRegisters().add("instructionPointer", 32);
2631 }
2632
2633 return true;
2634 },
2635 0,
2636 [] (BitArray & ba, Instruction & instr)
2637 {
2638// -----------------------------------------------------------------------------
2639etiss_uint8 rd = 0;
2640static BitArrayRange R_rd_0(11, 7);
2641rd += R_rd_0.read(ba) << 0;
2642etiss_uint8 rs1 = 0;
2643static BitArrayRange R_rs1_0(19, 15);
2644rs1 += R_rs1_0.read(ba) << 0;
2645etiss_uint8 shamt = 0;
2646static BitArrayRange R_shamt_0(24, 20);
2647shamt += R_shamt_0.read(ba) << 0;
2648
2649// -----------------------------------------------------------------------------
2650
2651 std::stringstream ss;
2652// -----------------------------------------------------------------------------
2653ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2654// -----------------------------------------------------------------------------
2655 return ss.str();
2656 }
2657);
2658
2659// SRAI ------------------------------------------------------------------------
2660static InstructionDefinition srai_rd_rs1_shamt (
2661 ISA32_RV32IMACFD,
2662 "srai",
2663 (uint32_t) 0x40005013,
2664 (uint32_t) 0xfe00707f,
2665 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2666 {
2667
2668// -----------------------------------------------------------------------------
2669
2670// -----------------------------------------------------------------------------
2671
2672// -----------------------------------------------------------------------------
2673etiss_uint8 rd = 0;
2674static BitArrayRange R_rd_0(11, 7);
2675rd += R_rd_0.read(ba) << 0;
2676etiss_uint8 rs1 = 0;
2677static BitArrayRange R_rs1_0(19, 15);
2678rs1 += R_rs1_0.read(ba) << 0;
2679etiss_uint8 shamt = 0;
2680static BitArrayRange R_shamt_0(24, 20);
2681shamt += R_shamt_0.read(ba) << 0;
2682
2683// -----------------------------------------------------------------------------
2684
2685 {
2686 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2687
2688 cp.code() = std::string("//SRAI\n");
2689
2690// -----------------------------------------------------------------------------
2691cp.code() += "etiss_coverage_count(1, 26);\n";
2692{ // block
2693cp.code() += "etiss_coverage_count(1, 1169);\n";
2694cp.code() += "{ // block\n";
2695cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2696cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2697cp.code() += "} // block\n";
2698} // block
2699cp.code() += "etiss_coverage_count(1, 1888);\n";
2700if ((rd % 32ULL) != 0LL) { // conditional
2701cp.code() += "etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";
2702cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n";
2703cp.code() += "etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";
2704} // conditional
2705cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2706cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2707// -----------------------------------------------------------------------------
2708 cp.getAffectedRegisters().add("instructionPointer", 32);
2709 }
2710
2711 return true;
2712 },
2713 0,
2714 [] (BitArray & ba, Instruction & instr)
2715 {
2716// -----------------------------------------------------------------------------
2717etiss_uint8 rd = 0;
2718static BitArrayRange R_rd_0(11, 7);
2719rd += R_rd_0.read(ba) << 0;
2720etiss_uint8 rs1 = 0;
2721static BitArrayRange R_rs1_0(19, 15);
2722rs1 += R_rs1_0.read(ba) << 0;
2723etiss_uint8 shamt = 0;
2724static BitArrayRange R_shamt_0(24, 20);
2725shamt += R_shamt_0.read(ba) << 0;
2726
2727// -----------------------------------------------------------------------------
2728
2729 std::stringstream ss;
2730// -----------------------------------------------------------------------------
2731ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
2732// -----------------------------------------------------------------------------
2733 return ss.str();
2734 }
2735);
2736
2737// ADD -------------------------------------------------------------------------
2738static InstructionDefinition add_rd_rs1_rs2 (
2739 ISA32_RV32IMACFD,
2740 "add",
2741 (uint32_t) 0x000033,
2742 (uint32_t) 0xfe00707f,
2743 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2744 {
2745
2746// -----------------------------------------------------------------------------
2747
2748// -----------------------------------------------------------------------------
2749
2750// -----------------------------------------------------------------------------
2751etiss_uint8 rd = 0;
2752static BitArrayRange R_rd_0(11, 7);
2753rd += R_rd_0.read(ba) << 0;
2754etiss_uint8 rs1 = 0;
2755static BitArrayRange R_rs1_0(19, 15);
2756rs1 += R_rs1_0.read(ba) << 0;
2757etiss_uint8 rs2 = 0;
2758static BitArrayRange R_rs2_0(24, 20);
2759rs2 += R_rs2_0.read(ba) << 0;
2760
2761// -----------------------------------------------------------------------------
2762
2763 {
2764 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2765
2766 cp.code() = std::string("//ADD\n");
2767
2768// -----------------------------------------------------------------------------
2769cp.code() += "etiss_coverage_count(1, 27);\n";
2770{ // block
2771cp.code() += "etiss_coverage_count(1, 1169);\n";
2772cp.code() += "{ // block\n";
2773cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2774cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2775cp.code() += "} // block\n";
2776} // block
2777cp.code() += "etiss_coverage_count(1, 1910);\n";
2778if ((rd % 32ULL) != 0LL) { // conditional
2779cp.code() += "etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";
2780cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2781cp.code() += "etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";
2782} // conditional
2783cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2784cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2785// -----------------------------------------------------------------------------
2786 cp.getAffectedRegisters().add("instructionPointer", 32);
2787 }
2788
2789 return true;
2790 },
2791 0,
2792 [] (BitArray & ba, Instruction & instr)
2793 {
2794// -----------------------------------------------------------------------------
2795etiss_uint8 rd = 0;
2796static BitArrayRange R_rd_0(11, 7);
2797rd += R_rd_0.read(ba) << 0;
2798etiss_uint8 rs1 = 0;
2799static BitArrayRange R_rs1_0(19, 15);
2800rs1 += R_rs1_0.read(ba) << 0;
2801etiss_uint8 rs2 = 0;
2802static BitArrayRange R_rs2_0(24, 20);
2803rs2 += R_rs2_0.read(ba) << 0;
2804
2805// -----------------------------------------------------------------------------
2806
2807 std::stringstream ss;
2808// -----------------------------------------------------------------------------
2809ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2810// -----------------------------------------------------------------------------
2811 return ss.str();
2812 }
2813);
2814
2815// SUB -------------------------------------------------------------------------
2816static InstructionDefinition sub_rd_rs1_rs2 (
2817 ISA32_RV32IMACFD,
2818 "sub",
2819 (uint32_t) 0x40000033,
2820 (uint32_t) 0xfe00707f,
2821 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2822 {
2823
2824// -----------------------------------------------------------------------------
2825
2826// -----------------------------------------------------------------------------
2827
2828// -----------------------------------------------------------------------------
2829etiss_uint8 rd = 0;
2830static BitArrayRange R_rd_0(11, 7);
2831rd += R_rd_0.read(ba) << 0;
2832etiss_uint8 rs1 = 0;
2833static BitArrayRange R_rs1_0(19, 15);
2834rs1 += R_rs1_0.read(ba) << 0;
2835etiss_uint8 rs2 = 0;
2836static BitArrayRange R_rs2_0(24, 20);
2837rs2 += R_rs2_0.read(ba) << 0;
2838
2839// -----------------------------------------------------------------------------
2840
2841 {
2842 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2843
2844 cp.code() = std::string("//SUB\n");
2845
2846// -----------------------------------------------------------------------------
2847cp.code() += "etiss_coverage_count(1, 28);\n";
2848{ // block
2849cp.code() += "etiss_coverage_count(1, 1169);\n";
2850cp.code() += "{ // block\n";
2851cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2852cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2853cp.code() += "} // block\n";
2854} // block
2855cp.code() += "etiss_coverage_count(1, 1934);\n";
2856if ((rd % 32ULL) != 0LL) { // conditional
2857cp.code() += "etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";
2858cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2859cp.code() += "etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";
2860} // conditional
2861cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2862cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2863// -----------------------------------------------------------------------------
2864 cp.getAffectedRegisters().add("instructionPointer", 32);
2865 }
2866
2867 return true;
2868 },
2869 0,
2870 [] (BitArray & ba, Instruction & instr)
2871 {
2872// -----------------------------------------------------------------------------
2873etiss_uint8 rd = 0;
2874static BitArrayRange R_rd_0(11, 7);
2875rd += R_rd_0.read(ba) << 0;
2876etiss_uint8 rs1 = 0;
2877static BitArrayRange R_rs1_0(19, 15);
2878rs1 += R_rs1_0.read(ba) << 0;
2879etiss_uint8 rs2 = 0;
2880static BitArrayRange R_rs2_0(24, 20);
2881rs2 += R_rs2_0.read(ba) << 0;
2882
2883// -----------------------------------------------------------------------------
2884
2885 std::stringstream ss;
2886// -----------------------------------------------------------------------------
2887ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2888// -----------------------------------------------------------------------------
2889 return ss.str();
2890 }
2891);
2892
2893// SLL -------------------------------------------------------------------------
2894static InstructionDefinition sll_rd_rs1_rs2 (
2895 ISA32_RV32IMACFD,
2896 "sll",
2897 (uint32_t) 0x001033,
2898 (uint32_t) 0xfe00707f,
2899 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2900 {
2901
2902// -----------------------------------------------------------------------------
2903
2904// -----------------------------------------------------------------------------
2905
2906// -----------------------------------------------------------------------------
2907etiss_uint8 rd = 0;
2908static BitArrayRange R_rd_0(11, 7);
2909rd += R_rd_0.read(ba) << 0;
2910etiss_uint8 rs1 = 0;
2911static BitArrayRange R_rs1_0(19, 15);
2912rs1 += R_rs1_0.read(ba) << 0;
2913etiss_uint8 rs2 = 0;
2914static BitArrayRange R_rs2_0(24, 20);
2915rs2 += R_rs2_0.read(ba) << 0;
2916
2917// -----------------------------------------------------------------------------
2918
2919 {
2920 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2921
2922 cp.code() = std::string("//SLL\n");
2923
2924// -----------------------------------------------------------------------------
2925cp.code() += "etiss_coverage_count(1, 29);\n";
2926{ // block
2927cp.code() += "etiss_coverage_count(1, 1169);\n";
2928cp.code() += "{ // block\n";
2929cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2930cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2931cp.code() += "} // block\n";
2932} // block
2933cp.code() += "etiss_coverage_count(1, 1958);\n";
2934if ((rd % 32ULL) != 0LL) { // conditional
2935cp.code() += "etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";
2936cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
2937cp.code() += "etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";
2938} // conditional
2939cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2940cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2941// -----------------------------------------------------------------------------
2942 cp.getAffectedRegisters().add("instructionPointer", 32);
2943 }
2944
2945 return true;
2946 },
2947 0,
2948 [] (BitArray & ba, Instruction & instr)
2949 {
2950// -----------------------------------------------------------------------------
2951etiss_uint8 rd = 0;
2952static BitArrayRange R_rd_0(11, 7);
2953rd += R_rd_0.read(ba) << 0;
2954etiss_uint8 rs1 = 0;
2955static BitArrayRange R_rs1_0(19, 15);
2956rs1 += R_rs1_0.read(ba) << 0;
2957etiss_uint8 rs2 = 0;
2958static BitArrayRange R_rs2_0(24, 20);
2959rs2 += R_rs2_0.read(ba) << 0;
2960
2961// -----------------------------------------------------------------------------
2962
2963 std::stringstream ss;
2964// -----------------------------------------------------------------------------
2965ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2966// -----------------------------------------------------------------------------
2967 return ss.str();
2968 }
2969);
2970
2971// SLT -------------------------------------------------------------------------
2972static InstructionDefinition slt_rd_rs1_rs2 (
2973 ISA32_RV32IMACFD,
2974 "slt",
2975 (uint32_t) 0x002033,
2976 (uint32_t) 0xfe00707f,
2977 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2978 {
2979
2980// -----------------------------------------------------------------------------
2981
2982// -----------------------------------------------------------------------------
2983
2984// -----------------------------------------------------------------------------
2985etiss_uint8 rd = 0;
2986static BitArrayRange R_rd_0(11, 7);
2987rd += R_rd_0.read(ba) << 0;
2988etiss_uint8 rs1 = 0;
2989static BitArrayRange R_rs1_0(19, 15);
2990rs1 += R_rs1_0.read(ba) << 0;
2991etiss_uint8 rs2 = 0;
2992static BitArrayRange R_rs2_0(24, 20);
2993rs2 += R_rs2_0.read(ba) << 0;
2994
2995// -----------------------------------------------------------------------------
2996
2997 {
2998 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2999
3000 cp.code() = std::string("//SLT\n");
3001
3002// -----------------------------------------------------------------------------
3003cp.code() += "etiss_coverage_count(1, 30);\n";
3004{ // block
3005cp.code() += "etiss_coverage_count(1, 1169);\n";
3006cp.code() += "{ // block\n";
3007cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3008cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3009cp.code() += "} // block\n";
3010} // block
3011cp.code() += "etiss_coverage_count(1, 1988);\n";
3012if ((rd % 32ULL) != 0LL) { // conditional
3013cp.code() += "etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";
3014cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0LL);\n";
3015cp.code() += "etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";
3016} // conditional
3017cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3018cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3019// -----------------------------------------------------------------------------
3020 cp.getAffectedRegisters().add("instructionPointer", 32);
3021 }
3022
3023 return true;
3024 },
3025 0,
3026 [] (BitArray & ba, Instruction & instr)
3027 {
3028// -----------------------------------------------------------------------------
3029etiss_uint8 rd = 0;
3030static BitArrayRange R_rd_0(11, 7);
3031rd += R_rd_0.read(ba) << 0;
3032etiss_uint8 rs1 = 0;
3033static BitArrayRange R_rs1_0(19, 15);
3034rs1 += R_rs1_0.read(ba) << 0;
3035etiss_uint8 rs2 = 0;
3036static BitArrayRange R_rs2_0(24, 20);
3037rs2 += R_rs2_0.read(ba) << 0;
3038
3039// -----------------------------------------------------------------------------
3040
3041 std::stringstream ss;
3042// -----------------------------------------------------------------------------
3043ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3044// -----------------------------------------------------------------------------
3045 return ss.str();
3046 }
3047);
3048
3049// SLTU ------------------------------------------------------------------------
3050static InstructionDefinition sltu_rd_rs1_rs2 (
3051 ISA32_RV32IMACFD,
3052 "sltu",
3053 (uint32_t) 0x003033,
3054 (uint32_t) 0xfe00707f,
3055 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3056 {
3057
3058// -----------------------------------------------------------------------------
3059
3060// -----------------------------------------------------------------------------
3061
3062// -----------------------------------------------------------------------------
3063etiss_uint8 rd = 0;
3064static BitArrayRange R_rd_0(11, 7);
3065rd += R_rd_0.read(ba) << 0;
3066etiss_uint8 rs1 = 0;
3067static BitArrayRange R_rs1_0(19, 15);
3068rs1 += R_rs1_0.read(ba) << 0;
3069etiss_uint8 rs2 = 0;
3070static BitArrayRange R_rs2_0(24, 20);
3071rs2 += R_rs2_0.read(ba) << 0;
3072
3073// -----------------------------------------------------------------------------
3074
3075 {
3076 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3077
3078 cp.code() = std::string("//SLTU\n");
3079
3080// -----------------------------------------------------------------------------
3081cp.code() += "etiss_coverage_count(1, 31);\n";
3082{ // block
3083cp.code() += "etiss_coverage_count(1, 1169);\n";
3084cp.code() += "{ // block\n";
3085cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3086cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3087cp.code() += "} // block\n";
3088} // block
3089cp.code() += "etiss_coverage_count(1, 2017);\n";
3090if ((rd % 32ULL) != 0LL) { // conditional
3091cp.code() += "etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";
3092cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0LL);\n";
3093cp.code() += "etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";
3094} // conditional
3095cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3096cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3097// -----------------------------------------------------------------------------
3098 cp.getAffectedRegisters().add("instructionPointer", 32);
3099 }
3100
3101 return true;
3102 },
3103 0,
3104 [] (BitArray & ba, Instruction & instr)
3105 {
3106// -----------------------------------------------------------------------------
3107etiss_uint8 rd = 0;
3108static BitArrayRange R_rd_0(11, 7);
3109rd += R_rd_0.read(ba) << 0;
3110etiss_uint8 rs1 = 0;
3111static BitArrayRange R_rs1_0(19, 15);
3112rs1 += R_rs1_0.read(ba) << 0;
3113etiss_uint8 rs2 = 0;
3114static BitArrayRange R_rs2_0(24, 20);
3115rs2 += R_rs2_0.read(ba) << 0;
3116
3117// -----------------------------------------------------------------------------
3118
3119 std::stringstream ss;
3120// -----------------------------------------------------------------------------
3121ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3122// -----------------------------------------------------------------------------
3123 return ss.str();
3124 }
3125);
3126
3127// XOR -------------------------------------------------------------------------
3128static InstructionDefinition xor_rd_rs1_rs2 (
3129 ISA32_RV32IMACFD,
3130 "xor",
3131 (uint32_t) 0x004033,
3132 (uint32_t) 0xfe00707f,
3133 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3134 {
3135
3136// -----------------------------------------------------------------------------
3137
3138// -----------------------------------------------------------------------------
3139
3140// -----------------------------------------------------------------------------
3141etiss_uint8 rd = 0;
3142static BitArrayRange R_rd_0(11, 7);
3143rd += R_rd_0.read(ba) << 0;
3144etiss_uint8 rs1 = 0;
3145static BitArrayRange R_rs1_0(19, 15);
3146rs1 += R_rs1_0.read(ba) << 0;
3147etiss_uint8 rs2 = 0;
3148static BitArrayRange R_rs2_0(24, 20);
3149rs2 += R_rs2_0.read(ba) << 0;
3150
3151// -----------------------------------------------------------------------------
3152
3153 {
3154 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3155
3156 cp.code() = std::string("//XOR\n");
3157
3158// -----------------------------------------------------------------------------
3159cp.code() += "etiss_coverage_count(1, 32);\n";
3160{ // block
3161cp.code() += "etiss_coverage_count(1, 1169);\n";
3162cp.code() += "{ // block\n";
3163cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3164cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3165cp.code() += "} // block\n";
3166} // block
3167cp.code() += "etiss_coverage_count(1, 2044);\n";
3168if ((rd % 32ULL) != 0LL) { // conditional
3169cp.code() += "etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";
3170cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3171cp.code() += "etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";
3172} // conditional
3173cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3174cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3175// -----------------------------------------------------------------------------
3176 cp.getAffectedRegisters().add("instructionPointer", 32);
3177 }
3178
3179 return true;
3180 },
3181 0,
3182 [] (BitArray & ba, Instruction & instr)
3183 {
3184// -----------------------------------------------------------------------------
3185etiss_uint8 rd = 0;
3186static BitArrayRange R_rd_0(11, 7);
3187rd += R_rd_0.read(ba) << 0;
3188etiss_uint8 rs1 = 0;
3189static BitArrayRange R_rs1_0(19, 15);
3190rs1 += R_rs1_0.read(ba) << 0;
3191etiss_uint8 rs2 = 0;
3192static BitArrayRange R_rs2_0(24, 20);
3193rs2 += R_rs2_0.read(ba) << 0;
3194
3195// -----------------------------------------------------------------------------
3196
3197 std::stringstream ss;
3198// -----------------------------------------------------------------------------
3199ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3200// -----------------------------------------------------------------------------
3201 return ss.str();
3202 }
3203);
3204
3205// SRL -------------------------------------------------------------------------
3206static InstructionDefinition srl_rd_rs1_rs2 (
3207 ISA32_RV32IMACFD,
3208 "srl",
3209 (uint32_t) 0x005033,
3210 (uint32_t) 0xfe00707f,
3211 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3212 {
3213
3214// -----------------------------------------------------------------------------
3215
3216// -----------------------------------------------------------------------------
3217
3218// -----------------------------------------------------------------------------
3219etiss_uint8 rd = 0;
3220static BitArrayRange R_rd_0(11, 7);
3221rd += R_rd_0.read(ba) << 0;
3222etiss_uint8 rs1 = 0;
3223static BitArrayRange R_rs1_0(19, 15);
3224rs1 += R_rs1_0.read(ba) << 0;
3225etiss_uint8 rs2 = 0;
3226static BitArrayRange R_rs2_0(24, 20);
3227rs2 += R_rs2_0.read(ba) << 0;
3228
3229// -----------------------------------------------------------------------------
3230
3231 {
3232 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3233
3234 cp.code() = std::string("//SRL\n");
3235
3236// -----------------------------------------------------------------------------
3237cp.code() += "etiss_coverage_count(1, 33);\n";
3238{ // block
3239cp.code() += "etiss_coverage_count(1, 1169);\n";
3240cp.code() += "{ // block\n";
3241cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3242cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3243cp.code() += "} // block\n";
3244} // block
3245cp.code() += "etiss_coverage_count(1, 2068);\n";
3246if ((rd % 32ULL) != 0LL) { // conditional
3247cp.code() += "etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";
3248cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
3249cp.code() += "etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";
3250} // conditional
3251cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3252cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3253// -----------------------------------------------------------------------------
3254 cp.getAffectedRegisters().add("instructionPointer", 32);
3255 }
3256
3257 return true;
3258 },
3259 0,
3260 [] (BitArray & ba, Instruction & instr)
3261 {
3262// -----------------------------------------------------------------------------
3263etiss_uint8 rd = 0;
3264static BitArrayRange R_rd_0(11, 7);
3265rd += R_rd_0.read(ba) << 0;
3266etiss_uint8 rs1 = 0;
3267static BitArrayRange R_rs1_0(19, 15);
3268rs1 += R_rs1_0.read(ba) << 0;
3269etiss_uint8 rs2 = 0;
3270static BitArrayRange R_rs2_0(24, 20);
3271rs2 += R_rs2_0.read(ba) << 0;
3272
3273// -----------------------------------------------------------------------------
3274
3275 std::stringstream ss;
3276// -----------------------------------------------------------------------------
3277ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3278// -----------------------------------------------------------------------------
3279 return ss.str();
3280 }
3281);
3282
3283// SRA -------------------------------------------------------------------------
3284static InstructionDefinition sra_rd_rs1_rs2 (
3285 ISA32_RV32IMACFD,
3286 "sra",
3287 (uint32_t) 0x40005033,
3288 (uint32_t) 0xfe00707f,
3289 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3290 {
3291
3292// -----------------------------------------------------------------------------
3293
3294// -----------------------------------------------------------------------------
3295
3296// -----------------------------------------------------------------------------
3297etiss_uint8 rd = 0;
3298static BitArrayRange R_rd_0(11, 7);
3299rd += R_rd_0.read(ba) << 0;
3300etiss_uint8 rs1 = 0;
3301static BitArrayRange R_rs1_0(19, 15);
3302rs1 += R_rs1_0.read(ba) << 0;
3303etiss_uint8 rs2 = 0;
3304static BitArrayRange R_rs2_0(24, 20);
3305rs2 += R_rs2_0.read(ba) << 0;
3306
3307// -----------------------------------------------------------------------------
3308
3309 {
3310 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3311
3312 cp.code() = std::string("//SRA\n");
3313
3314// -----------------------------------------------------------------------------
3315cp.code() += "etiss_coverage_count(1, 34);\n";
3316{ // block
3317cp.code() += "etiss_coverage_count(1, 1169);\n";
3318cp.code() += "{ // block\n";
3319cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3320cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3321cp.code() += "} // block\n";
3322} // block
3323cp.code() += "etiss_coverage_count(1, 2098);\n";
3324if ((rd % 32ULL) != 0LL) { // conditional
3325cp.code() += "etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";
3326cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n";
3327cp.code() += "etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";
3328} // conditional
3329cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3330cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3331// -----------------------------------------------------------------------------
3332 cp.getAffectedRegisters().add("instructionPointer", 32);
3333 }
3334
3335 return true;
3336 },
3337 0,
3338 [] (BitArray & ba, Instruction & instr)
3339 {
3340// -----------------------------------------------------------------------------
3341etiss_uint8 rd = 0;
3342static BitArrayRange R_rd_0(11, 7);
3343rd += R_rd_0.read(ba) << 0;
3344etiss_uint8 rs1 = 0;
3345static BitArrayRange R_rs1_0(19, 15);
3346rs1 += R_rs1_0.read(ba) << 0;
3347etiss_uint8 rs2 = 0;
3348static BitArrayRange R_rs2_0(24, 20);
3349rs2 += R_rs2_0.read(ba) << 0;
3350
3351// -----------------------------------------------------------------------------
3352
3353 std::stringstream ss;
3354// -----------------------------------------------------------------------------
3355ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3356// -----------------------------------------------------------------------------
3357 return ss.str();
3358 }
3359);
3360
3361// OR --------------------------------------------------------------------------
3362static InstructionDefinition or_rd_rs1_rs2 (
3363 ISA32_RV32IMACFD,
3364 "or",
3365 (uint32_t) 0x006033,
3366 (uint32_t) 0xfe00707f,
3367 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3368 {
3369
3370// -----------------------------------------------------------------------------
3371
3372// -----------------------------------------------------------------------------
3373
3374// -----------------------------------------------------------------------------
3375etiss_uint8 rd = 0;
3376static BitArrayRange R_rd_0(11, 7);
3377rd += R_rd_0.read(ba) << 0;
3378etiss_uint8 rs1 = 0;
3379static BitArrayRange R_rs1_0(19, 15);
3380rs1 += R_rs1_0.read(ba) << 0;
3381etiss_uint8 rs2 = 0;
3382static BitArrayRange R_rs2_0(24, 20);
3383rs2 += R_rs2_0.read(ba) << 0;
3384
3385// -----------------------------------------------------------------------------
3386
3387 {
3388 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3389
3390 cp.code() = std::string("//OR\n");
3391
3392// -----------------------------------------------------------------------------
3393cp.code() += "etiss_coverage_count(1, 35);\n";
3394{ // block
3395cp.code() += "etiss_coverage_count(1, 1169);\n";
3396cp.code() += "{ // block\n";
3397cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3398cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3399cp.code() += "} // block\n";
3400} // block
3401cp.code() += "etiss_coverage_count(1, 2129);\n";
3402if ((rd % 32ULL) != 0LL) { // conditional
3403cp.code() += "etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";
3404cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3405cp.code() += "etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";
3406} // conditional
3407cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3408cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3409// -----------------------------------------------------------------------------
3410 cp.getAffectedRegisters().add("instructionPointer", 32);
3411 }
3412
3413 return true;
3414 },
3415 0,
3416 [] (BitArray & ba, Instruction & instr)
3417 {
3418// -----------------------------------------------------------------------------
3419etiss_uint8 rd = 0;
3420static BitArrayRange R_rd_0(11, 7);
3421rd += R_rd_0.read(ba) << 0;
3422etiss_uint8 rs1 = 0;
3423static BitArrayRange R_rs1_0(19, 15);
3424rs1 += R_rs1_0.read(ba) << 0;
3425etiss_uint8 rs2 = 0;
3426static BitArrayRange R_rs2_0(24, 20);
3427rs2 += R_rs2_0.read(ba) << 0;
3428
3429// -----------------------------------------------------------------------------
3430
3431 std::stringstream ss;
3432// -----------------------------------------------------------------------------
3433ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3434// -----------------------------------------------------------------------------
3435 return ss.str();
3436 }
3437);
3438
3439// AND -------------------------------------------------------------------------
3440static InstructionDefinition and_rd_rs1_rs2 (
3441 ISA32_RV32IMACFD,
3442 "and",
3443 (uint32_t) 0x007033,
3444 (uint32_t) 0xfe00707f,
3445 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3446 {
3447
3448// -----------------------------------------------------------------------------
3449
3450// -----------------------------------------------------------------------------
3451
3452// -----------------------------------------------------------------------------
3453etiss_uint8 rd = 0;
3454static BitArrayRange R_rd_0(11, 7);
3455rd += R_rd_0.read(ba) << 0;
3456etiss_uint8 rs1 = 0;
3457static BitArrayRange R_rs1_0(19, 15);
3458rs1 += R_rs1_0.read(ba) << 0;
3459etiss_uint8 rs2 = 0;
3460static BitArrayRange R_rs2_0(24, 20);
3461rs2 += R_rs2_0.read(ba) << 0;
3462
3463// -----------------------------------------------------------------------------
3464
3465 {
3466 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3467
3468 cp.code() = std::string("//AND\n");
3469
3470// -----------------------------------------------------------------------------
3471cp.code() += "etiss_coverage_count(1, 36);\n";
3472{ // block
3473cp.code() += "etiss_coverage_count(1, 1169);\n";
3474cp.code() += "{ // block\n";
3475cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3476cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3477cp.code() += "} // block\n";
3478} // block
3479cp.code() += "etiss_coverage_count(1, 2153);\n";
3480if ((rd % 32ULL) != 0LL) { // conditional
3481cp.code() += "etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";
3482cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
3483cp.code() += "etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";
3484} // conditional
3485cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3486cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3487// -----------------------------------------------------------------------------
3488 cp.getAffectedRegisters().add("instructionPointer", 32);
3489 }
3490
3491 return true;
3492 },
3493 0,
3494 [] (BitArray & ba, Instruction & instr)
3495 {
3496// -----------------------------------------------------------------------------
3497etiss_uint8 rd = 0;
3498static BitArrayRange R_rd_0(11, 7);
3499rd += R_rd_0.read(ba) << 0;
3500etiss_uint8 rs1 = 0;
3501static BitArrayRange R_rs1_0(19, 15);
3502rs1 += R_rs1_0.read(ba) << 0;
3503etiss_uint8 rs2 = 0;
3504static BitArrayRange R_rs2_0(24, 20);
3505rs2 += R_rs2_0.read(ba) << 0;
3506
3507// -----------------------------------------------------------------------------
3508
3509 std::stringstream ss;
3510// -----------------------------------------------------------------------------
3511ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
3512// -----------------------------------------------------------------------------
3513 return ss.str();
3514 }
3515);
3516
3517// FENCE -----------------------------------------------------------------------
3518static InstructionDefinition fence_rd_rs1_succ_pred_fm (
3519 ISA32_RV32IMACFD,
3520 "fence",
3521 (uint32_t) 0x00000f,
3522 (uint32_t) 0x00707f,
3523 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3524 {
3525
3526// -----------------------------------------------------------------------------
3527
3528// -----------------------------------------------------------------------------
3529
3530// -----------------------------------------------------------------------------
3531etiss_uint8 rd = 0;
3532static BitArrayRange R_rd_0(11, 7);
3533rd += R_rd_0.read(ba) << 0;
3534etiss_uint8 rs1 = 0;
3535static BitArrayRange R_rs1_0(19, 15);
3536rs1 += R_rs1_0.read(ba) << 0;
3537etiss_uint8 succ = 0;
3538static BitArrayRange R_succ_0(23, 20);
3539succ += R_succ_0.read(ba) << 0;
3540etiss_uint8 pred = 0;
3541static BitArrayRange R_pred_0(27, 24);
3542pred += R_pred_0.read(ba) << 0;
3543etiss_uint8 fm = 0;
3544static BitArrayRange R_fm_0(31, 28);
3545fm += R_fm_0.read(ba) << 0;
3546
3547// -----------------------------------------------------------------------------
3548
3549 {
3550 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
3551
3552 cp.code() = std::string("//FENCE\n");
3553
3554// -----------------------------------------------------------------------------
3555cp.code() += "etiss_coverage_count(1, 37);\n";
3556{ // block
3557cp.code() += "etiss_coverage_count(1, 1169);\n";
3558cp.code() += "{ // block\n";
3559cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
3560cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
3561cp.code() += "} // block\n";
3562} // block
3563cp.code() += "((RV32IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
3564cp.code() += "etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";
3565cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
3566cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
3567// -----------------------------------------------------------------------------
3568 cp.getAffectedRegisters().add("instructionPointer", 32);
3569 }
3570
3571 return true;
3572 },
3573 0,
3574 [] (BitArray & ba, Instruction & instr)
3575 {
3576// -----------------------------------------------------------------------------
3577etiss_uint8 rd = 0;
3578static BitArrayRange R_rd_0(11, 7);
3579rd += R_rd_0.read(ba) << 0;
3580etiss_uint8 rs1 = 0;
3581static BitArrayRange R_rs1_0(19, 15);
3582rs1 += R_rs1_0.read(ba) << 0;
3583etiss_uint8 succ = 0;
3584static BitArrayRange R_succ_0(23, 20);
3585succ += R_succ_0.read(ba) << 0;
3586etiss_uint8 pred = 0;
3587static BitArrayRange R_pred_0(27, 24);
3588pred += R_pred_0.read(ba) << 0;
3589etiss_uint8 fm = 0;
3590static BitArrayRange R_fm_0(31, 28);
3591fm += R_fm_0.read(ba) << 0;
3592
3593// -----------------------------------------------------------------------------
3594
3595 std::stringstream ss;
3596// -----------------------------------------------------------------------------
3597ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]");
3598// -----------------------------------------------------------------------------
3599 return ss.str();
3600 }
3601);
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
bltu_imm_rs1_rs2
static InstructionDefinition bltu_imm_rs1_rs2(ISA32_RV32IMACFD, "bltu",(uint32_t) 0x006063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="etiss_coverage_count(1, 8);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1435);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1407);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1418, 1412, 1411, 1409, 1417, 1416, 1414);\n";{ cp.code()+="etiss_coverage_count(1, 1434);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1419);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1422, 1420);\n";{ cp.code()+="etiss_coverage_count(1, 1426);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1425, 1423);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1433);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1432, 1427, 1431, 1428, 1430, 1429);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLTU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bltu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bne_imm_rs1_rs2
static InstructionDefinition bne_imm_rs1_rs2(ISA32_RV32IMACFD, "bne",(uint32_t) 0x001063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="etiss_coverage_count(1, 5);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1340);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1312);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] != *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1323, 1317, 1316, 1314, 1322, 1321, 1319);\n";{ cp.code()+="etiss_coverage_count(1, 1339);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1324);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1327, 1325);\n";{ cp.code()+="etiss_coverage_count(1, 1331);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1330, 1328);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1338);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1337, 1332, 1336, 1333, 1335, 1334);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BNE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bne"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV32IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");cp.code()+="etiss_coverage_count(1, 26);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1888);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1894, 1891, 1889, 1892, 1893);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(10, 1909, 1899, 1898, 1896, 1908, 1906, 1904, 1903, 1901, 1907);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
fence_rd_rs1_succ_pred_fm
static InstructionDefinition fence_rd_rs1_succ_pred_fm(ISA32_RV32IMACFD, "fence",(uint32_t) 0x00000f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE\n");cp.code()+="etiss_coverage_count(1, 37);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="((RV32IMACFD*)cpu)->FENCE[0ULL] = "+std::to_string(pred<< 4ULL|succ)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2185, 2179, 2184, 2182, 2180, 2181, 2183);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 succ=0;static BitArrayRange R_succ_0(23, 20);succ+=R_succ_0.read(ba)<< 0;etiss_uint8 pred=0;static BitArrayRange R_pred_0(27, 24);pred+=R_pred_0.read(ba)<< 0;etiss_uint8 fm=0;static BitArrayRange R_fm_0(31, 28);fm+=R_fm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | succ="+std::to_string(succ)+" | pred="+std::to_string(pred)+" | fm="+std::to_string(fm)+"]");return ss.str();})
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RV32IMACFD, "auipc",(uint32_t) 0x000017,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AUIPC\n");cp.code()+="etiss_coverage_count(1, 1);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1188);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1194, 1191, 1189, 1192, 1193);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+(etiss_int32)(imm))+"LL;\n";cp.code()+="etiss_coverage_count(8, 1204, 1199, 1198, 1196, 1203, 1200, 1202, 1201);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "auipc"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
beq_imm_rs1_rs2
static InstructionDefinition beq_imm_rs1_rs2(ISA32_RV32IMACFD, "beq",(uint32_t) 0x000063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="etiss_coverage_count(1, 4);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1311);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1283);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1294, 1288, 1287, 1285, 1293, 1292, 1290);\n";{ cp.code()+="etiss_coverage_count(1, 1310);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1295);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1298, 1296);\n";{ cp.code()+="etiss_coverage_count(1, 1302);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1301, 1299);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1309);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1308, 1303, 1307, 1304, 1306, 1305);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BEQ\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "beq"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RV32IMACFD, "ori",(uint32_t) 0x006013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ORI\n");cp.code()+="etiss_coverage_count(1, 22);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1800);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1806, 1803, 1801, 1804, 1805);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | "+std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1823, 1811, 1810, 1808, 1822, 1816, 1815, 1813, 1821, 1818, 1817, 1819);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RV32IMACFD, "srl",(uint32_t) 0x005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRL\n");cp.code()+="etiss_coverage_count(1, 33);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2068);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2074, 2071, 2069, 2072, 2073);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 31ULL);\n";cp.code()+="etiss_coverage_count(13, 2097, 2079, 2078, 2076, 2096, 2084, 2083, 2081, 2094, 2089, 2088, 2086, 2095);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srl"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RV32IMACFD, "addi",(uint32_t) 0x000013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDI\n");cp.code()+="etiss_coverage_count(1, 18);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1701);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1707, 1704, 1702, 1705, 1706);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(10, 1721, 1712, 1711, 1709, 1720, 1717, 1716, 1714, 1719, 1718);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RV32IMACFD, "and",(uint32_t) 0x007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AND\n");cp.code()+="etiss_coverage_count(1, 36);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2153);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2159, 2156, 2154, 2157, 2158);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2176, 2164, 2163, 2161, 2175, 2169, 2168, 2166, 2174, 2173, 2171);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "and"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV32IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");cp.code()+="etiss_coverage_count(1, 24);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1848);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1854, 1851, 1849, 1852, 1853);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1867, 1859, 1858, 1856, 1866, 1864, 1863, 1861, 1865);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
lw_rd_rs1_imm
static InstructionDefinition lw_rd_rs1_imm(ISA32_RV32IMACFD, "lw",(uint32_t) 0x002003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="etiss_coverage_count(1, 12);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1566);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1542, 1541, 1538, 1537, 1535, 1540, 1539);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1549, 1548, 1546, 1545);\n";cp.code()+="etiss_coverage_count(1, 1550);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1556, 1553, 1551, 1554, 1555);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 1565, 1561, 1560, 1558, 1564, 1562);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RV32IMACFD, "andi",(uint32_t) 0x007013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ANDI\n");cp.code()+="etiss_coverage_count(1, 23);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1824);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1830, 1827, 1825, 1828, 1829);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & "+std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1847, 1835, 1834, 1832, 1846, 1840, 1839, 1837, 1845, 1842, 1841, 1843);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "andi"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lh_rd_rs1_imm
static InstructionDefinition lh_rd_rs1_imm(ISA32_RV32IMACFD, "lh",(uint32_t) 0x001003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="etiss_coverage_count(1, 11);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1532);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1508, 1507, 1504, 1503, 1501, 1506, 1505);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int16 res = (etiss_int16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1515, 1514, 1512, 1511);\n";cp.code()+="etiss_coverage_count(1, 1516);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1522, 1519, 1517, 1520, 1521);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 1531, 1527, 1526, 1524, 1530, 1528);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
bge_imm_rs1_rs2
static InstructionDefinition bge_imm_rs1_rs2(ISA32_RV32IMACFD, "bge",(uint32_t) 0x005063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="etiss_coverage_count(1, 7);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1374);\n";cp.code()+="if ((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1389, 1381, 1379, 1378, 1376, 1388, 1386, 1385, 1383);\n";{ cp.code()+="etiss_coverage_count(1, 1405);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1390);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1393, 1391);\n";{ cp.code()+="etiss_coverage_count(1, 1397);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1396, 1394);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1404);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1403, 1398, 1402, 1399, 1401, 1400);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGE\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bge"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RV32IMACFD, "xor",(uint32_t) 0x004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XOR\n");cp.code()+="etiss_coverage_count(1, 32);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2044);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2050, 2047, 2045, 2048, 2049);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2067, 2055, 2054, 2052, 2066, 2060, 2059, 2057, 2065, 2064, 2062);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "xor"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RV32IMACFD, "slt",(uint32_t) 0x002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLT\n");cp.code()+="etiss_coverage_count(1, 30);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1988);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1994, 1991, 1989, 1992, 1993);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 2016, 1999, 1998, 1996, 2015, 2012, 2005, 2004, 2003, 2001, 2011, 2010, 2009, 2007, 2013, 2014);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "slt"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RV32IMACFD, "slti",(uint32_t) 0x002013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTI\n");cp.code()+="etiss_coverage_count(1, 19);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1722);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1728, 1725, 1723, 1726, 1727);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(15, 1747, 1733, 1732, 1730, 1746, 1742, 1739, 1738, 1737, 1735, 1741, 1740, 1743, 1744, 1745);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "slti"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sh_imm_rs1_rs2
static InstructionDefinition sh_imm_rs1_rs2(ISA32_RV32IMACFD, "sh",(uint32_t) 0x001023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="etiss_coverage_count(1, 16);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1678);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1666, 1665, 1662, 1661, 1659, 1664, 1663);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1677, 1669, 1668, 1676, 1674, 1673, 1671);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SH\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sh"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lbu_rd_rs1_imm
static InstructionDefinition lbu_rd_rs1_imm(ISA32_RV32IMACFD, "lbu",(uint32_t) 0x004003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="etiss_coverage_count(1, 13);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1600);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1576, 1575, 1572, 1571, 1569, 1574, 1573);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint8 res = (etiss_uint8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1583, 1582, 1580, 1579);\n";cp.code()+="etiss_coverage_count(1, 1584);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1590, 1587, 1585, 1588, 1589);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 1599, 1595, 1594, 1592, 1598, 1596);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LBU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lbu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
lhu_rd_rs1_imm
static InstructionDefinition lhu_rd_rs1_imm(ISA32_RV32IMACFD, "lhu",(uint32_t) 0x005003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="etiss_coverage_count(1, 14);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1634);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1610, 1609, 1606, 1605, 1603, 1608, 1607);\n";cp.code()+="etiss_uint16 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint16 res = (etiss_uint16)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1617, 1616, 1614, 1613);\n";cp.code()+="etiss_coverage_count(1, 1618);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1624, 1621, 1619, 1622, 1623);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 1633, 1629, 1628, 1626, 1632, 1630);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LHU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RV32IMACFD, "sltu",(uint32_t) 0x003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTU\n");cp.code()+="etiss_coverage_count(1, 31);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2017);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2023, 2020, 2018, 2021, 2022);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(14, 2043, 2028, 2027, 2025, 2042, 2039, 2033, 2032, 2030, 2038, 2037, 2035, 2040, 2041);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sltu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
bgeu_imm_rs1_rs2
static InstructionDefinition bgeu_imm_rs1_rs2(ISA32_RV32IMACFD, "bgeu",(uint32_t) 0x007063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="etiss_coverage_count(1, 9);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1464);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1436);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >= *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) { // conditional\n";cp.code()+="etiss_coverage_count(7, 1447, 1441, 1440, 1438, 1446, 1445, 1443);\n";{ cp.code()+="etiss_coverage_count(1, 1463);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1448);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1451, 1449);\n";{ cp.code()+="etiss_coverage_count(1, 1455);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1454, 1452);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1462);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1461, 1456, 1460, 1457, 1459, 1458);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BGEU\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "bgeu"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sw_imm_rs1_rs2
static InstructionDefinition sw_imm_rs1_rs2(ISA32_RV32IMACFD, "sw",(uint32_t) 0x002023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="etiss_coverage_count(1, 17);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1700);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1688, 1687, 1684, 1683, 1681, 1686, 1685);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1699, 1691, 1690, 1698, 1696, 1695, 1693);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RV32IMACFD, "xori",(uint32_t) 0x004013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//XORI\n");cp.code()+="etiss_coverage_count(1, 21);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1776);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1782, 1779, 1777, 1780, 1781);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] ^ "+std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL;\n";cp.code()+="etiss_coverage_count(12, 1799, 1787, 1786, 1784, 1798, 1792, 1791, 1789, 1797, 1794, 1793, 1795);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "xori"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RV32IMACFD, "jal",(uint32_t) 0x00006f,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="etiss_coverage_count(1, 2);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1236);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1205);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1208, 1206);\n";{ cp.code()+="etiss_coverage_count(1, 1212);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1211, 1209);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1235);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1213);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1219, 1216, 1214, 1217, 1218);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1228, 1224, 1223, 1221, 1227, 1225, 1226);\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int32)(((etiss_int32) imm)<<(11)) > >(11)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1234, 1229, 1233, 1230, 1232, 1231);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(19, 12);imm+=R_imm_12.read(ba)<< 12;static BitArrayRange R_imm_11(20, 20);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(30, 21);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_20(31, 31);imm+=R_imm_20.read(ba)<< 20;std::stringstream ss;ss<< "jal"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RV32IMACFD, "add",(uint32_t) 0x000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADD\n");cp.code()+="etiss_coverage_count(1, 27);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1910);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1916, 1913, 1911, 1914, 1915);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1933, 1921, 1920, 1918, 1932, 1926, 1925, 1923, 1931, 1930, 1928);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "add"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RV32IMACFD, "or",(uint32_t) 0x006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//OR\n");cp.code()+="etiss_coverage_count(1, 35);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2129);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2135, 2132, 2130, 2133, 2134);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] | *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2152, 2140, 2139, 2137, 2151, 2145, 2144, 2142, 2150, 2149, 2147);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "or"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RV32IMACFD, "jalr",(uint32_t) 0x000067,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="etiss_coverage_count(1, 3);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1282);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL) & -2LL;\n";cp.code()+="etiss_coverage_count(9, 1250, 1249, 1245, 1242, 1241, 1239, 1244, 1243, 1246);\n";cp.code()+="etiss_coverage_count(1, 1251);\n";cp.code()+="if (new_pc % 2ULL) { // conditional\n";cp.code()+="etiss_coverage_count(2, 1254, 1252);\n";{ cp.code()+="etiss_coverage_count(1, 1258);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1257, 1255);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";{ cp.code()+="etiss_coverage_count(1, 1281);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1259);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1265, 1262, 1260, 1263, 1264);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(ic.current_address_+4ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1274, 1270, 1269, 1267, 1273, 1271, 1272);\n";} cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="etiss_coverage_count(4, 1280, 1275, 1279, 1276);\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//JALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "jalr"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sb_imm_rs1_rs2
static InstructionDefinition sb_imm_rs1_rs2(ISA32_RV32IMACFD, "sb",(uint32_t) 0x000023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="etiss_coverage_count(1, 15);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1656);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1644, 1643, 1640, 1639, 1637, 1642, 1641);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 1655, 1647, 1646, 1654, 1652, 1651, 1649);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sb"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RV32IMACFD, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRA\n");cp.code()+="etiss_coverage_count(1, 34);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2098);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2104, 2101, 2099, 2102, 2103);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) >> (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 31ULL);\n";cp.code()+="etiss_coverage_count(14, 2128, 2109, 2108, 2106, 2127, 2115, 2114, 2113, 2111, 2125, 2120, 2119, 2117, 2126);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sra"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RV32IMACFD, "sll",(uint32_t) 0x001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLL\n");cp.code()+="etiss_coverage_count(1, 29);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1958);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1964, 1961, 1959, 1962, 1963);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] & 31ULL);\n";cp.code()+="etiss_coverage_count(13, 1987, 1969, 1968, 1966, 1986, 1974, 1973, 1971, 1984, 1979, 1978, 1976, 1985);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sll"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RV32IMACFD, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUB\n");cp.code()+="etiss_coverage_count(1, 28);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1934);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1940, 1937, 1935, 1938, 1939);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] - *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 1957, 1945, 1944, 1942, 1956, 1950, 1949, 1947, 1955, 1954, 1952);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sub"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RV32IMACFD, "lui",(uint32_t) 0x000037,(uint32_t) 0x00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LUI\n");cp.code()+="etiss_coverage_count(1, 0);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1170);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1176, 1173, 1171, 1174, 1175);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string((etiss_uint32)(((etiss_int32)(imm))))+"ULL;\n";cp.code()+="etiss_coverage_count(8, 1187, 1181, 1180, 1178, 1186, 1183, 1182, 1184);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint32 imm=0;static BitArrayRange R_imm_12(31, 12);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "lui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
blt_imm_rs1_rs2
static InstructionDefinition blt_imm_rs1_rs2(ISA32_RV32IMACFD, "blt",(uint32_t) 0x004063,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="etiss_coverage_count(1, 6);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1373);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1341);\n";cp.code()+="if ((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) { // conditional\n";cp.code()+="etiss_coverage_count(9, 1356, 1348, 1346, 1345, 1343, 1355, 1353, 1352, 1350);\n";{ cp.code()+="etiss_coverage_count(1, 1372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 1357);\n";if(imm % 2ULL) { cp.code()+="etiss_coverage_count(2, 1360, 1358);\n";{ cp.code()+="etiss_coverage_count(1, 1364);\n";cp.code()+="{ // block\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 0LL);\n";cp.code()+="etiss_coverage_count(2, 1363, 1361);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // block\n";} } else { { cp.code()+="etiss_coverage_count(1, 1371);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(3)) > >(3)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 1370, 1365, 1369, 1366, 1368, 1367);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//BLT\n");cp.code()+="if (cpu->return_pending || cpu->exception || cpu->nextPc != "+std::to_string(ic.current_address_+4)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_11(7, 7);imm+=R_imm_11.read(ba)<< 11;static BitArrayRange R_imm_1(11, 8);imm+=R_imm_1.read(ba)<< 1;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(30, 25);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_12(31, 31);imm+=R_imm_12.read(ba)<< 12;std::stringstream ss;ss<< "blt"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lb_rd_rs1_imm
static InstructionDefinition lb_rd_rs1_imm(ISA32_RV32IMACFD, "lb",(uint32_t) 0x000003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="etiss_coverage_count(1, 10);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 1498);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 1474, 1473, 1470, 1469, 1467, 1472, 1471);\n";cp.code()+="etiss_uint8 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int8 res = (etiss_int8)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 1481, 1480, 1478, 1477);\n";cp.code()+="etiss_coverage_count(1, 1482);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1488, 1485, 1483, 1486, 1487);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 1497, 1493, 1492, 1490, 1496, 1494);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LB\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lb"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV32IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");cp.code()+="etiss_coverage_count(1, 25);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1868);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1874, 1871, 1869, 1872, 1873);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 1887, 1879, 1878, 1876, 1886, 1884, 1883, 1881, 1885);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RV32IMACFD, "sltiu",(uint32_t) 0x003013,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLTIU\n");cp.code()+="etiss_coverage_count(1, 20);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 1748);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 1754, 1751, 1749, 1752, 1753);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] < "+std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))))+"ULL)) ? (1ULL) : (0LL);\n";cp.code()+="etiss_coverage_count(16, 1775, 1759, 1758, 1756, 1774, 1770, 1764, 1763, 1761, 1769, 1766, 1765, 1767, 1771, 1772, 1773);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "sltiu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:89
etiss_uint32
uint32_t etiss_uint32
Definition types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss_int32
int32_t etiss_int32
Definition types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition types.h:90
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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