ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV32IMACFD_RV32DInstr.cpp
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1
8#include "RV32IMACFDArch.h"
9#include "RV32IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// FLD -------------------------------------------------------------------------
16static InstructionDefinition fld_rd_rs1_imm (
17 ISA32_RV32IMACFD,
18 "fld",
19 (uint32_t) 0x003007,
20 (uint32_t) 0x00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rs1 = 0;
33static BitArrayRange R_rs1_0(19, 15);
34rs1 += R_rs1_0.read(ba) << 0;
35etiss_uint16 imm = 0;
36static BitArrayRange R_imm_0(31, 20);
37imm += R_imm_0.read(ba) << 0;
38
39// -----------------------------------------------------------------------------
40
41 {
42 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43
44 cp.code() = std::string("//FLD\n");
45
46// -----------------------------------------------------------------------------
47cp.code() += "etiss_coverage_count(1, 118);\n";
48{ // block
49cp.code() += "etiss_coverage_count(1, 1169);\n";
50cp.code() += "{ // block\n";
51cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53cp.code() += "} // block\n";
54} // block
55{ // block
56cp.code() += "etiss_coverage_count(1, 5067);\n";
57cp.code() += "{ // block\n";
58cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
59cp.code() += "etiss_coverage_count(7, 5038, 5037, 5033, 5032, 5030, 5036, 5034);\n";
60cp.code() += "etiss_uint64 mem_val_0;\n";
61cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
62cp.code() += "if (cpu->exception) { // conditional\n";
63{ // procedure
64cp.code() += "{ // procedure\n";
65cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
66cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
67cp.code() += "} // procedure\n";
68} // procedure
69cp.code() += "} // conditional\n";
70cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
71cp.code() += "etiss_coverage_count(4, 5045, 5044, 5042, 5041);\n";
72cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
73cp.code() += "etiss_coverage_count(4, 5054, 5052, 5051, 5053);\n";
74cp.code() += "} // block\n";
75} // block
76cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
77cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
78// -----------------------------------------------------------------------------
79 cp.getAffectedRegisters().add("instructionPointer", 32);
80 }
81 {
82 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
83
84 cp.code() = std::string("//FLD\n");
85
86// -----------------------------------------------------------------------------
87cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
88// -----------------------------------------------------------------------------
89 }
90
91 return true;
92 },
93 0,
94 [] (BitArray & ba, Instruction & instr)
95 {
96// -----------------------------------------------------------------------------
97etiss_uint8 rd = 0;
98static BitArrayRange R_rd_0(11, 7);
99rd += R_rd_0.read(ba) << 0;
100etiss_uint8 rs1 = 0;
101static BitArrayRange R_rs1_0(19, 15);
102rs1 += R_rs1_0.read(ba) << 0;
103etiss_uint16 imm = 0;
104static BitArrayRange R_imm_0(31, 20);
105imm += R_imm_0.read(ba) << 0;
106
107// -----------------------------------------------------------------------------
108
109 std::stringstream ss;
110// -----------------------------------------------------------------------------
111ss << "fld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
112// -----------------------------------------------------------------------------
113 return ss.str();
114 }
115);
116
117// FSD -------------------------------------------------------------------------
118static InstructionDefinition fsd_imm_rs1_rs2 (
119 ISA32_RV32IMACFD,
120 "fsd",
121 (uint32_t) 0x003027,
122 (uint32_t) 0x00707f,
123 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
124 {
125
126// -----------------------------------------------------------------------------
127
128// -----------------------------------------------------------------------------
129
130// -----------------------------------------------------------------------------
131etiss_uint16 imm = 0;
132static BitArrayRange R_imm_0(11, 7);
133imm += R_imm_0.read(ba) << 0;
134etiss_uint8 rs1 = 0;
135static BitArrayRange R_rs1_0(19, 15);
136rs1 += R_rs1_0.read(ba) << 0;
137etiss_uint8 rs2 = 0;
138static BitArrayRange R_rs2_0(24, 20);
139rs2 += R_rs2_0.read(ba) << 0;
140static BitArrayRange R_imm_5(31, 25);
141imm += R_imm_5.read(ba) << 5;
142
143// -----------------------------------------------------------------------------
144
145 {
146 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
147
148 cp.code() = std::string("//FSD\n");
149
150// -----------------------------------------------------------------------------
151cp.code() += "etiss_coverage_count(1, 119);\n";
152{ // block
153cp.code() += "etiss_coverage_count(1, 1169);\n";
154cp.code() += "{ // block\n";
155cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
156cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
157cp.code() += "} // block\n";
158} // block
159{ // block
160cp.code() += "etiss_coverage_count(1, 5088);\n";
161cp.code() += "{ // block\n";
162cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
163cp.code() += "etiss_coverage_count(7, 5078, 5077, 5073, 5072, 5070, 5076, 5074);\n";
164cp.code() += "etiss_uint64 mem_val_0;\n";
165cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
166cp.code() += "etiss_coverage_count(6, 5087, 5081, 5080, 5086, 5084, 5083);\n";
167cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
168cp.code() += "if (cpu->exception) { // conditional\n";
169{ // procedure
170cp.code() += "{ // procedure\n";
171cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
172cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
173cp.code() += "} // procedure\n";
174} // procedure
175cp.code() += "} // conditional\n";
176cp.code() += "} // block\n";
177} // block
178cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
179cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
180// -----------------------------------------------------------------------------
181 cp.getAffectedRegisters().add("instructionPointer", 32);
182 }
183 {
184 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
185
186 cp.code() = std::string("//FSD\n");
187
188// -----------------------------------------------------------------------------
189cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
190// -----------------------------------------------------------------------------
191 }
192
193 return true;
194 },
195 0,
196 [] (BitArray & ba, Instruction & instr)
197 {
198// -----------------------------------------------------------------------------
199etiss_uint16 imm = 0;
200static BitArrayRange R_imm_0(11, 7);
201imm += R_imm_0.read(ba) << 0;
202etiss_uint8 rs1 = 0;
203static BitArrayRange R_rs1_0(19, 15);
204rs1 += R_rs1_0.read(ba) << 0;
205etiss_uint8 rs2 = 0;
206static BitArrayRange R_rs2_0(24, 20);
207rs2 += R_rs2_0.read(ba) << 0;
208static BitArrayRange R_imm_5(31, 25);
209imm += R_imm_5.read(ba) << 5;
210
211// -----------------------------------------------------------------------------
212
213 std::stringstream ss;
214// -----------------------------------------------------------------------------
215ss << "fsd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
216// -----------------------------------------------------------------------------
217 return ss.str();
218 }
219);
220
221// FMADD_D ---------------------------------------------------------------------
222static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 (
223 ISA32_RV32IMACFD,
224 "fmadd_d",
225 (uint32_t) 0x2000043,
226 (uint32_t) 0x600007f,
227 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
228 {
229
230// -----------------------------------------------------------------------------
231
232// -----------------------------------------------------------------------------
233
234// -----------------------------------------------------------------------------
235etiss_uint8 rd = 0;
236static BitArrayRange R_rd_0(11, 7);
237rd += R_rd_0.read(ba) << 0;
238etiss_uint8 rm = 0;
239static BitArrayRange R_rm_0(14, 12);
240rm += R_rm_0.read(ba) << 0;
241etiss_uint8 rs1 = 0;
242static BitArrayRange R_rs1_0(19, 15);
243rs1 += R_rs1_0.read(ba) << 0;
244etiss_uint8 rs2 = 0;
245static BitArrayRange R_rs2_0(24, 20);
246rs2 += R_rs2_0.read(ba) << 0;
247etiss_uint8 rs3 = 0;
248static BitArrayRange R_rs3_0(31, 27);
249rs3 += R_rs3_0.read(ba) << 0;
250
251// -----------------------------------------------------------------------------
252
253 {
254 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
255
256 cp.code() = std::string("//FMADD_D\n");
257
258// -----------------------------------------------------------------------------
259cp.code() += "etiss_coverage_count(1, 120);\n";
260{ // block
261cp.code() += "etiss_coverage_count(1, 1169);\n";
262cp.code() += "{ // block\n";
263cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
264cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
265cp.code() += "} // block\n";
266} // block
267{ // block
268cp.code() += "etiss_coverage_count(1, 5146);\n";
269cp.code() += "{ // block\n";
270cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
271cp.code() += "etiss_coverage_count(14, 5109, 5108, 5094, 5092, 5091, 5099, 5097, 5096, 5104, 5102, 5101, 5105, 5107, 5106);\n";
272cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
273cp.code() += "etiss_coverage_count(4, 5118, 5116, 5115, 5117);\n";
274cp.code() += "etiss_uint32 flags = fget_flags();\n";
275cp.code() += "etiss_coverage_count(2, 5133, 5132);\n";
276cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
277cp.code() += "etiss_coverage_count(9, 5145, 5134, 5144, 5138, 5135, 5139, 5142, 5140, 5143);\n";
278cp.code() += "} // block\n";
279} // block
280cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
281cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
282// -----------------------------------------------------------------------------
283 cp.getAffectedRegisters().add("instructionPointer", 32);
284 }
285
286 return true;
287 },
288 0,
289 [] (BitArray & ba, Instruction & instr)
290 {
291// -----------------------------------------------------------------------------
292etiss_uint8 rd = 0;
293static BitArrayRange R_rd_0(11, 7);
294rd += R_rd_0.read(ba) << 0;
295etiss_uint8 rm = 0;
296static BitArrayRange R_rm_0(14, 12);
297rm += R_rm_0.read(ba) << 0;
298etiss_uint8 rs1 = 0;
299static BitArrayRange R_rs1_0(19, 15);
300rs1 += R_rs1_0.read(ba) << 0;
301etiss_uint8 rs2 = 0;
302static BitArrayRange R_rs2_0(24, 20);
303rs2 += R_rs2_0.read(ba) << 0;
304etiss_uint8 rs3 = 0;
305static BitArrayRange R_rs3_0(31, 27);
306rs3 += R_rs3_0.read(ba) << 0;
307
308// -----------------------------------------------------------------------------
309
310 std::stringstream ss;
311// -----------------------------------------------------------------------------
312ss << "fmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
313// -----------------------------------------------------------------------------
314 return ss.str();
315 }
316);
317
318// FMSUB_D ---------------------------------------------------------------------
319static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 (
320 ISA32_RV32IMACFD,
321 "fmsub_d",
322 (uint32_t) 0x2000047,
323 (uint32_t) 0x600007f,
324 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
325 {
326
327// -----------------------------------------------------------------------------
328
329// -----------------------------------------------------------------------------
330
331// -----------------------------------------------------------------------------
332etiss_uint8 rd = 0;
333static BitArrayRange R_rd_0(11, 7);
334rd += R_rd_0.read(ba) << 0;
335etiss_uint8 rm = 0;
336static BitArrayRange R_rm_0(14, 12);
337rm += R_rm_0.read(ba) << 0;
338etiss_uint8 rs1 = 0;
339static BitArrayRange R_rs1_0(19, 15);
340rs1 += R_rs1_0.read(ba) << 0;
341etiss_uint8 rs2 = 0;
342static BitArrayRange R_rs2_0(24, 20);
343rs2 += R_rs2_0.read(ba) << 0;
344etiss_uint8 rs3 = 0;
345static BitArrayRange R_rs3_0(31, 27);
346rs3 += R_rs3_0.read(ba) << 0;
347
348// -----------------------------------------------------------------------------
349
350 {
351 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
352
353 cp.code() = std::string("//FMSUB_D\n");
354
355// -----------------------------------------------------------------------------
356cp.code() += "etiss_coverage_count(1, 121);\n";
357{ // block
358cp.code() += "etiss_coverage_count(1, 1169);\n";
359cp.code() += "{ // block\n";
360cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
361cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
362cp.code() += "} // block\n";
363} // block
364{ // block
365cp.code() += "etiss_coverage_count(1, 5204);\n";
366cp.code() += "{ // block\n";
367cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
368cp.code() += "etiss_coverage_count(14, 5167, 5166, 5152, 5150, 5149, 5157, 5155, 5154, 5162, 5160, 5159, 5163, 5165, 5164);\n";
369cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
370cp.code() += "etiss_coverage_count(4, 5176, 5174, 5173, 5175);\n";
371cp.code() += "etiss_uint32 flags = fget_flags();\n";
372cp.code() += "etiss_coverage_count(2, 5191, 5190);\n";
373cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
374cp.code() += "etiss_coverage_count(9, 5203, 5192, 5202, 5196, 5193, 5197, 5200, 5198, 5201);\n";
375cp.code() += "} // block\n";
376} // block
377cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
378cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
379// -----------------------------------------------------------------------------
380 cp.getAffectedRegisters().add("instructionPointer", 32);
381 }
382
383 return true;
384 },
385 0,
386 [] (BitArray & ba, Instruction & instr)
387 {
388// -----------------------------------------------------------------------------
389etiss_uint8 rd = 0;
390static BitArrayRange R_rd_0(11, 7);
391rd += R_rd_0.read(ba) << 0;
392etiss_uint8 rm = 0;
393static BitArrayRange R_rm_0(14, 12);
394rm += R_rm_0.read(ba) << 0;
395etiss_uint8 rs1 = 0;
396static BitArrayRange R_rs1_0(19, 15);
397rs1 += R_rs1_0.read(ba) << 0;
398etiss_uint8 rs2 = 0;
399static BitArrayRange R_rs2_0(24, 20);
400rs2 += R_rs2_0.read(ba) << 0;
401etiss_uint8 rs3 = 0;
402static BitArrayRange R_rs3_0(31, 27);
403rs3 += R_rs3_0.read(ba) << 0;
404
405// -----------------------------------------------------------------------------
406
407 std::stringstream ss;
408// -----------------------------------------------------------------------------
409ss << "fmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
410// -----------------------------------------------------------------------------
411 return ss.str();
412 }
413);
414
415// FNMADD_D --------------------------------------------------------------------
416static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 (
417 ISA32_RV32IMACFD,
418 "fnmadd_d",
419 (uint32_t) 0x200004f,
420 (uint32_t) 0x600007f,
421 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
422 {
423
424// -----------------------------------------------------------------------------
425
426// -----------------------------------------------------------------------------
427
428// -----------------------------------------------------------------------------
429etiss_uint8 rd = 0;
430static BitArrayRange R_rd_0(11, 7);
431rd += R_rd_0.read(ba) << 0;
432etiss_uint8 rm = 0;
433static BitArrayRange R_rm_0(14, 12);
434rm += R_rm_0.read(ba) << 0;
435etiss_uint8 rs1 = 0;
436static BitArrayRange R_rs1_0(19, 15);
437rs1 += R_rs1_0.read(ba) << 0;
438etiss_uint8 rs2 = 0;
439static BitArrayRange R_rs2_0(24, 20);
440rs2 += R_rs2_0.read(ba) << 0;
441etiss_uint8 rs3 = 0;
442static BitArrayRange R_rs3_0(31, 27);
443rs3 += R_rs3_0.read(ba) << 0;
444
445// -----------------------------------------------------------------------------
446
447 {
448 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
449
450 cp.code() = std::string("//FNMADD_D\n");
451
452// -----------------------------------------------------------------------------
453cp.code() += "etiss_coverage_count(1, 122);\n";
454{ // block
455cp.code() += "etiss_coverage_count(1, 1169);\n";
456cp.code() += "{ // block\n";
457cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
458cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
459cp.code() += "} // block\n";
460} // block
461{ // block
462cp.code() += "etiss_coverage_count(1, 5262);\n";
463cp.code() += "{ // block\n";
464cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
465cp.code() += "etiss_coverage_count(14, 5225, 5224, 5210, 5208, 5207, 5215, 5213, 5212, 5220, 5218, 5217, 5221, 5223, 5222);\n";
466cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
467cp.code() += "etiss_coverage_count(4, 5234, 5232, 5231, 5233);\n";
468cp.code() += "etiss_uint32 flags = fget_flags();\n";
469cp.code() += "etiss_coverage_count(2, 5249, 5248);\n";
470cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
471cp.code() += "etiss_coverage_count(9, 5261, 5250, 5260, 5254, 5251, 5255, 5258, 5256, 5259);\n";
472cp.code() += "} // block\n";
473} // block
474cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
475cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
476// -----------------------------------------------------------------------------
477 cp.getAffectedRegisters().add("instructionPointer", 32);
478 }
479
480 return true;
481 },
482 0,
483 [] (BitArray & ba, Instruction & instr)
484 {
485// -----------------------------------------------------------------------------
486etiss_uint8 rd = 0;
487static BitArrayRange R_rd_0(11, 7);
488rd += R_rd_0.read(ba) << 0;
489etiss_uint8 rm = 0;
490static BitArrayRange R_rm_0(14, 12);
491rm += R_rm_0.read(ba) << 0;
492etiss_uint8 rs1 = 0;
493static BitArrayRange R_rs1_0(19, 15);
494rs1 += R_rs1_0.read(ba) << 0;
495etiss_uint8 rs2 = 0;
496static BitArrayRange R_rs2_0(24, 20);
497rs2 += R_rs2_0.read(ba) << 0;
498etiss_uint8 rs3 = 0;
499static BitArrayRange R_rs3_0(31, 27);
500rs3 += R_rs3_0.read(ba) << 0;
501
502// -----------------------------------------------------------------------------
503
504 std::stringstream ss;
505// -----------------------------------------------------------------------------
506ss << "fnmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
507// -----------------------------------------------------------------------------
508 return ss.str();
509 }
510);
511
512// FNMSUB_D --------------------------------------------------------------------
513static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 (
514 ISA32_RV32IMACFD,
515 "fnmsub_d",
516 (uint32_t) 0x200004b,
517 (uint32_t) 0x600007f,
518 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
519 {
520
521// -----------------------------------------------------------------------------
522
523// -----------------------------------------------------------------------------
524
525// -----------------------------------------------------------------------------
526etiss_uint8 rd = 0;
527static BitArrayRange R_rd_0(11, 7);
528rd += R_rd_0.read(ba) << 0;
529etiss_uint8 rm = 0;
530static BitArrayRange R_rm_0(14, 12);
531rm += R_rm_0.read(ba) << 0;
532etiss_uint8 rs1 = 0;
533static BitArrayRange R_rs1_0(19, 15);
534rs1 += R_rs1_0.read(ba) << 0;
535etiss_uint8 rs2 = 0;
536static BitArrayRange R_rs2_0(24, 20);
537rs2 += R_rs2_0.read(ba) << 0;
538etiss_uint8 rs3 = 0;
539static BitArrayRange R_rs3_0(31, 27);
540rs3 += R_rs3_0.read(ba) << 0;
541
542// -----------------------------------------------------------------------------
543
544 {
545 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
546
547 cp.code() = std::string("//FNMSUB_D\n");
548
549// -----------------------------------------------------------------------------
550cp.code() += "etiss_coverage_count(1, 123);\n";
551{ // block
552cp.code() += "etiss_coverage_count(1, 1169);\n";
553cp.code() += "{ // block\n";
554cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
555cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
556cp.code() += "} // block\n";
557} // block
558{ // block
559cp.code() += "etiss_coverage_count(1, 5320);\n";
560cp.code() += "{ // block\n";
561cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
562cp.code() += "etiss_coverage_count(14, 5283, 5282, 5268, 5266, 5265, 5273, 5271, 5270, 5278, 5276, 5275, 5279, 5281, 5280);\n";
563cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
564cp.code() += "etiss_coverage_count(4, 5292, 5290, 5289, 5291);\n";
565cp.code() += "etiss_uint32 flags = fget_flags();\n";
566cp.code() += "etiss_coverage_count(2, 5307, 5306);\n";
567cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
568cp.code() += "etiss_coverage_count(9, 5319, 5308, 5318, 5312, 5309, 5313, 5316, 5314, 5317);\n";
569cp.code() += "} // block\n";
570} // block
571cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
572cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
573// -----------------------------------------------------------------------------
574 cp.getAffectedRegisters().add("instructionPointer", 32);
575 }
576
577 return true;
578 },
579 0,
580 [] (BitArray & ba, Instruction & instr)
581 {
582// -----------------------------------------------------------------------------
583etiss_uint8 rd = 0;
584static BitArrayRange R_rd_0(11, 7);
585rd += R_rd_0.read(ba) << 0;
586etiss_uint8 rm = 0;
587static BitArrayRange R_rm_0(14, 12);
588rm += R_rm_0.read(ba) << 0;
589etiss_uint8 rs1 = 0;
590static BitArrayRange R_rs1_0(19, 15);
591rs1 += R_rs1_0.read(ba) << 0;
592etiss_uint8 rs2 = 0;
593static BitArrayRange R_rs2_0(24, 20);
594rs2 += R_rs2_0.read(ba) << 0;
595etiss_uint8 rs3 = 0;
596static BitArrayRange R_rs3_0(31, 27);
597rs3 += R_rs3_0.read(ba) << 0;
598
599// -----------------------------------------------------------------------------
600
601 std::stringstream ss;
602// -----------------------------------------------------------------------------
603ss << "fnmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
604// -----------------------------------------------------------------------------
605 return ss.str();
606 }
607);
608
609// FADD_D ----------------------------------------------------------------------
610static InstructionDefinition fadd_d_rd_rm_rs1_rs2 (
611 ISA32_RV32IMACFD,
612 "fadd_d",
613 (uint32_t) 0x2000053,
614 (uint32_t) 0xfe00007f,
615 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
616 {
617
618// -----------------------------------------------------------------------------
619
620// -----------------------------------------------------------------------------
621
622// -----------------------------------------------------------------------------
623etiss_uint8 rd = 0;
624static BitArrayRange R_rd_0(11, 7);
625rd += R_rd_0.read(ba) << 0;
626etiss_uint8 rm = 0;
627static BitArrayRange R_rm_0(14, 12);
628rm += R_rm_0.read(ba) << 0;
629etiss_uint8 rs1 = 0;
630static BitArrayRange R_rs1_0(19, 15);
631rs1 += R_rs1_0.read(ba) << 0;
632etiss_uint8 rs2 = 0;
633static BitArrayRange R_rs2_0(24, 20);
634rs2 += R_rs2_0.read(ba) << 0;
635
636// -----------------------------------------------------------------------------
637
638 {
639 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
640
641 cp.code() = std::string("//FADD_D\n");
642
643// -----------------------------------------------------------------------------
644cp.code() += "etiss_coverage_count(1, 124);\n";
645{ // block
646cp.code() += "etiss_coverage_count(1, 1169);\n";
647cp.code() += "{ // block\n";
648cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
649cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
650cp.code() += "} // block\n";
651} // block
652{ // block
653cp.code() += "etiss_coverage_count(1, 5372);\n";
654cp.code() += "{ // block\n";
655cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
656cp.code() += "etiss_coverage_count(10, 5335, 5334, 5326, 5324, 5323, 5331, 5329, 5328, 5333, 5332);\n";
657cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
658cp.code() += "etiss_coverage_count(4, 5344, 5342, 5341, 5343);\n";
659cp.code() += "etiss_uint32 flags = fget_flags();\n";
660cp.code() += "etiss_coverage_count(2, 5359, 5358);\n";
661cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
662cp.code() += "etiss_coverage_count(9, 5371, 5360, 5370, 5364, 5361, 5365, 5368, 5366, 5369);\n";
663cp.code() += "} // block\n";
664} // block
665cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
666cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
667// -----------------------------------------------------------------------------
668 cp.getAffectedRegisters().add("instructionPointer", 32);
669 }
670
671 return true;
672 },
673 0,
674 [] (BitArray & ba, Instruction & instr)
675 {
676// -----------------------------------------------------------------------------
677etiss_uint8 rd = 0;
678static BitArrayRange R_rd_0(11, 7);
679rd += R_rd_0.read(ba) << 0;
680etiss_uint8 rm = 0;
681static BitArrayRange R_rm_0(14, 12);
682rm += R_rm_0.read(ba) << 0;
683etiss_uint8 rs1 = 0;
684static BitArrayRange R_rs1_0(19, 15);
685rs1 += R_rs1_0.read(ba) << 0;
686etiss_uint8 rs2 = 0;
687static BitArrayRange R_rs2_0(24, 20);
688rs2 += R_rs2_0.read(ba) << 0;
689
690// -----------------------------------------------------------------------------
691
692 std::stringstream ss;
693// -----------------------------------------------------------------------------
694ss << "fadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
695// -----------------------------------------------------------------------------
696 return ss.str();
697 }
698);
699
700// FSUB_D ----------------------------------------------------------------------
701static InstructionDefinition fsub_d_rd_rm_rs1_rs2 (
702 ISA32_RV32IMACFD,
703 "fsub_d",
704 (uint32_t) 0xa000053,
705 (uint32_t) 0xfe00007f,
706 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
707 {
708
709// -----------------------------------------------------------------------------
710
711// -----------------------------------------------------------------------------
712
713// -----------------------------------------------------------------------------
714etiss_uint8 rd = 0;
715static BitArrayRange R_rd_0(11, 7);
716rd += R_rd_0.read(ba) << 0;
717etiss_uint8 rm = 0;
718static BitArrayRange R_rm_0(14, 12);
719rm += R_rm_0.read(ba) << 0;
720etiss_uint8 rs1 = 0;
721static BitArrayRange R_rs1_0(19, 15);
722rs1 += R_rs1_0.read(ba) << 0;
723etiss_uint8 rs2 = 0;
724static BitArrayRange R_rs2_0(24, 20);
725rs2 += R_rs2_0.read(ba) << 0;
726
727// -----------------------------------------------------------------------------
728
729 {
730 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
731
732 cp.code() = std::string("//FSUB_D\n");
733
734// -----------------------------------------------------------------------------
735cp.code() += "etiss_coverage_count(1, 125);\n";
736{ // block
737cp.code() += "etiss_coverage_count(1, 1169);\n";
738cp.code() += "{ // block\n";
739cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
740cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
741cp.code() += "} // block\n";
742} // block
743{ // block
744cp.code() += "etiss_coverage_count(1, 5424);\n";
745cp.code() += "{ // block\n";
746cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
747cp.code() += "etiss_coverage_count(10, 5387, 5386, 5378, 5376, 5375, 5383, 5381, 5380, 5385, 5384);\n";
748cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
749cp.code() += "etiss_coverage_count(4, 5396, 5394, 5393, 5395);\n";
750cp.code() += "etiss_uint32 flags = fget_flags();\n";
751cp.code() += "etiss_coverage_count(2, 5411, 5410);\n";
752cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
753cp.code() += "etiss_coverage_count(9, 5423, 5412, 5422, 5416, 5413, 5417, 5420, 5418, 5421);\n";
754cp.code() += "} // block\n";
755} // block
756cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
757cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
758// -----------------------------------------------------------------------------
759 cp.getAffectedRegisters().add("instructionPointer", 32);
760 }
761
762 return true;
763 },
764 0,
765 [] (BitArray & ba, Instruction & instr)
766 {
767// -----------------------------------------------------------------------------
768etiss_uint8 rd = 0;
769static BitArrayRange R_rd_0(11, 7);
770rd += R_rd_0.read(ba) << 0;
771etiss_uint8 rm = 0;
772static BitArrayRange R_rm_0(14, 12);
773rm += R_rm_0.read(ba) << 0;
774etiss_uint8 rs1 = 0;
775static BitArrayRange R_rs1_0(19, 15);
776rs1 += R_rs1_0.read(ba) << 0;
777etiss_uint8 rs2 = 0;
778static BitArrayRange R_rs2_0(24, 20);
779rs2 += R_rs2_0.read(ba) << 0;
780
781// -----------------------------------------------------------------------------
782
783 std::stringstream ss;
784// -----------------------------------------------------------------------------
785ss << "fsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
786// -----------------------------------------------------------------------------
787 return ss.str();
788 }
789);
790
791// FMUL_D ----------------------------------------------------------------------
792static InstructionDefinition fmul_d_rd_rm_rs1_rs2 (
793 ISA32_RV32IMACFD,
794 "fmul_d",
795 (uint32_t) 0x12000053,
796 (uint32_t) 0xfe00007f,
797 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
798 {
799
800// -----------------------------------------------------------------------------
801
802// -----------------------------------------------------------------------------
803
804// -----------------------------------------------------------------------------
805etiss_uint8 rd = 0;
806static BitArrayRange R_rd_0(11, 7);
807rd += R_rd_0.read(ba) << 0;
808etiss_uint8 rm = 0;
809static BitArrayRange R_rm_0(14, 12);
810rm += R_rm_0.read(ba) << 0;
811etiss_uint8 rs1 = 0;
812static BitArrayRange R_rs1_0(19, 15);
813rs1 += R_rs1_0.read(ba) << 0;
814etiss_uint8 rs2 = 0;
815static BitArrayRange R_rs2_0(24, 20);
816rs2 += R_rs2_0.read(ba) << 0;
817
818// -----------------------------------------------------------------------------
819
820 {
821 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
822
823 cp.code() = std::string("//FMUL_D\n");
824
825// -----------------------------------------------------------------------------
826cp.code() += "etiss_coverage_count(1, 126);\n";
827{ // block
828cp.code() += "etiss_coverage_count(1, 1169);\n";
829cp.code() += "{ // block\n";
830cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
831cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
832cp.code() += "} // block\n";
833} // block
834{ // block
835cp.code() += "etiss_coverage_count(1, 5476);\n";
836cp.code() += "{ // block\n";
837cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
838cp.code() += "etiss_coverage_count(10, 5439, 5438, 5430, 5428, 5427, 5435, 5433, 5432, 5437, 5436);\n";
839cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
840cp.code() += "etiss_coverage_count(4, 5448, 5446, 5445, 5447);\n";
841cp.code() += "etiss_uint32 flags = fget_flags();\n";
842cp.code() += "etiss_coverage_count(2, 5463, 5462);\n";
843cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
844cp.code() += "etiss_coverage_count(9, 5475, 5464, 5474, 5468, 5465, 5469, 5472, 5470, 5473);\n";
845cp.code() += "} // block\n";
846} // block
847cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
848cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
849// -----------------------------------------------------------------------------
850 cp.getAffectedRegisters().add("instructionPointer", 32);
851 }
852
853 return true;
854 },
855 0,
856 [] (BitArray & ba, Instruction & instr)
857 {
858// -----------------------------------------------------------------------------
859etiss_uint8 rd = 0;
860static BitArrayRange R_rd_0(11, 7);
861rd += R_rd_0.read(ba) << 0;
862etiss_uint8 rm = 0;
863static BitArrayRange R_rm_0(14, 12);
864rm += R_rm_0.read(ba) << 0;
865etiss_uint8 rs1 = 0;
866static BitArrayRange R_rs1_0(19, 15);
867rs1 += R_rs1_0.read(ba) << 0;
868etiss_uint8 rs2 = 0;
869static BitArrayRange R_rs2_0(24, 20);
870rs2 += R_rs2_0.read(ba) << 0;
871
872// -----------------------------------------------------------------------------
873
874 std::stringstream ss;
875// -----------------------------------------------------------------------------
876ss << "fmul_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
877// -----------------------------------------------------------------------------
878 return ss.str();
879 }
880);
881
882// FDIV_D ----------------------------------------------------------------------
883static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 (
884 ISA32_RV32IMACFD,
885 "fdiv_d",
886 (uint32_t) 0x1a000053,
887 (uint32_t) 0xfe00007f,
888 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
889 {
890
891// -----------------------------------------------------------------------------
892
893// -----------------------------------------------------------------------------
894
895// -----------------------------------------------------------------------------
896etiss_uint8 rd = 0;
897static BitArrayRange R_rd_0(11, 7);
898rd += R_rd_0.read(ba) << 0;
899etiss_uint8 rm = 0;
900static BitArrayRange R_rm_0(14, 12);
901rm += R_rm_0.read(ba) << 0;
902etiss_uint8 rs1 = 0;
903static BitArrayRange R_rs1_0(19, 15);
904rs1 += R_rs1_0.read(ba) << 0;
905etiss_uint8 rs2 = 0;
906static BitArrayRange R_rs2_0(24, 20);
907rs2 += R_rs2_0.read(ba) << 0;
908
909// -----------------------------------------------------------------------------
910
911 {
912 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
913
914 cp.code() = std::string("//FDIV_D\n");
915
916// -----------------------------------------------------------------------------
917cp.code() += "etiss_coverage_count(1, 127);\n";
918{ // block
919cp.code() += "etiss_coverage_count(1, 1169);\n";
920cp.code() += "{ // block\n";
921cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
922cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
923cp.code() += "} // block\n";
924} // block
925{ // block
926cp.code() += "etiss_coverage_count(1, 5528);\n";
927cp.code() += "{ // block\n";
928cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
929cp.code() += "etiss_coverage_count(10, 5491, 5490, 5482, 5480, 5479, 5487, 5485, 5484, 5489, 5488);\n";
930cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
931cp.code() += "etiss_coverage_count(4, 5500, 5498, 5497, 5499);\n";
932cp.code() += "etiss_uint32 flags = fget_flags();\n";
933cp.code() += "etiss_coverage_count(2, 5515, 5514);\n";
934cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
935cp.code() += "etiss_coverage_count(9, 5527, 5516, 5526, 5520, 5517, 5521, 5524, 5522, 5525);\n";
936cp.code() += "} // block\n";
937} // block
938cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
939cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
940// -----------------------------------------------------------------------------
941 cp.getAffectedRegisters().add("instructionPointer", 32);
942 }
943
944 return true;
945 },
946 0,
947 [] (BitArray & ba, Instruction & instr)
948 {
949// -----------------------------------------------------------------------------
950etiss_uint8 rd = 0;
951static BitArrayRange R_rd_0(11, 7);
952rd += R_rd_0.read(ba) << 0;
953etiss_uint8 rm = 0;
954static BitArrayRange R_rm_0(14, 12);
955rm += R_rm_0.read(ba) << 0;
956etiss_uint8 rs1 = 0;
957static BitArrayRange R_rs1_0(19, 15);
958rs1 += R_rs1_0.read(ba) << 0;
959etiss_uint8 rs2 = 0;
960static BitArrayRange R_rs2_0(24, 20);
961rs2 += R_rs2_0.read(ba) << 0;
962
963// -----------------------------------------------------------------------------
964
965 std::stringstream ss;
966// -----------------------------------------------------------------------------
967ss << "fdiv_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
968// -----------------------------------------------------------------------------
969 return ss.str();
970 }
971);
972
973// FSQRT_D ---------------------------------------------------------------------
974static InstructionDefinition fsqrt_d_rd_rm_rs1 (
975 ISA32_RV32IMACFD,
976 "fsqrt_d",
977 (uint32_t) 0x5a000053,
978 (uint32_t) 0xfff0007f,
979 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
980 {
981
982// -----------------------------------------------------------------------------
983
984// -----------------------------------------------------------------------------
985
986// -----------------------------------------------------------------------------
987etiss_uint8 rd = 0;
988static BitArrayRange R_rd_0(11, 7);
989rd += R_rd_0.read(ba) << 0;
990etiss_uint8 rm = 0;
991static BitArrayRange R_rm_0(14, 12);
992rm += R_rm_0.read(ba) << 0;
993etiss_uint8 rs1 = 0;
994static BitArrayRange R_rs1_0(19, 15);
995rs1 += R_rs1_0.read(ba) << 0;
996
997// -----------------------------------------------------------------------------
998
999 {
1000 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1001
1002 cp.code() = std::string("//FSQRT_D\n");
1003
1004// -----------------------------------------------------------------------------
1005cp.code() += "etiss_coverage_count(1, 128);\n";
1006{ // block
1007cp.code() += "etiss_coverage_count(1, 1169);\n";
1008cp.code() += "{ // block\n";
1009cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1010cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1011cp.code() += "} // block\n";
1012} // block
1013{ // block
1014cp.code() += "etiss_coverage_count(1, 5575);\n";
1015cp.code() += "{ // block\n";
1016cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1017cp.code() += "etiss_coverage_count(7, 5538, 5537, 5534, 5532, 5531, 5536, 5535);\n";
1018cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1019cp.code() += "etiss_coverage_count(4, 5547, 5545, 5544, 5546);\n";
1020cp.code() += "etiss_uint32 flags = fget_flags();\n";
1021cp.code() += "etiss_coverage_count(2, 5562, 5561);\n";
1022cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1023cp.code() += "etiss_coverage_count(9, 5574, 5563, 5573, 5567, 5564, 5568, 5571, 5569, 5572);\n";
1024cp.code() += "} // block\n";
1025} // block
1026cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1027cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1028// -----------------------------------------------------------------------------
1029 cp.getAffectedRegisters().add("instructionPointer", 32);
1030 }
1031
1032 return true;
1033 },
1034 0,
1035 [] (BitArray & ba, Instruction & instr)
1036 {
1037// -----------------------------------------------------------------------------
1038etiss_uint8 rd = 0;
1039static BitArrayRange R_rd_0(11, 7);
1040rd += R_rd_0.read(ba) << 0;
1041etiss_uint8 rm = 0;
1042static BitArrayRange R_rm_0(14, 12);
1043rm += R_rm_0.read(ba) << 0;
1044etiss_uint8 rs1 = 0;
1045static BitArrayRange R_rs1_0(19, 15);
1046rs1 += R_rs1_0.read(ba) << 0;
1047
1048// -----------------------------------------------------------------------------
1049
1050 std::stringstream ss;
1051// -----------------------------------------------------------------------------
1052ss << "fsqrt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1053// -----------------------------------------------------------------------------
1054 return ss.str();
1055 }
1056);
1057
1058// FSGNJ_D ---------------------------------------------------------------------
1059static InstructionDefinition fsgnj_d_rd_rs1_rs2 (
1060 ISA32_RV32IMACFD,
1061 "fsgnj_d",
1062 (uint32_t) 0x22000053,
1063 (uint32_t) 0xfe00707f,
1064 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1065 {
1066
1067// -----------------------------------------------------------------------------
1068
1069// -----------------------------------------------------------------------------
1070
1071// -----------------------------------------------------------------------------
1072etiss_uint8 rd = 0;
1073static BitArrayRange R_rd_0(11, 7);
1074rd += R_rd_0.read(ba) << 0;
1075etiss_uint8 rs1 = 0;
1076static BitArrayRange R_rs1_0(19, 15);
1077rs1 += R_rs1_0.read(ba) << 0;
1078etiss_uint8 rs2 = 0;
1079static BitArrayRange R_rs2_0(24, 20);
1080rs2 += R_rs2_0.read(ba) << 0;
1081
1082// -----------------------------------------------------------------------------
1083
1084 {
1085 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1086
1087 cp.code() = std::string("//FSGNJ_D\n");
1088
1089// -----------------------------------------------------------------------------
1090cp.code() += "etiss_coverage_count(1, 129);\n";
1091{ // block
1092cp.code() += "etiss_coverage_count(1, 1169);\n";
1093cp.code() += "{ // block\n";
1094cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1095cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1096cp.code() += "} // block\n";
1097} // block
1098{ // block
1099cp.code() += "etiss_coverage_count(1, 5612);\n";
1100cp.code() += "{ // block\n";
1101cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1ULL)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";
1102cp.code() += "etiss_coverage_count(12, 5590, 5589, 5582, 5579, 5578, 5580, 5581, 5588, 5585, 5584, 5586, 5587);\n";
1103cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1104cp.code() += "etiss_coverage_count(4, 5599, 5597, 5596, 5598);\n";
1105cp.code() += "} // block\n";
1106} // block
1107cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1108cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1109// -----------------------------------------------------------------------------
1110 cp.getAffectedRegisters().add("instructionPointer", 32);
1111 }
1112
1113 return true;
1114 },
1115 0,
1116 [] (BitArray & ba, Instruction & instr)
1117 {
1118// -----------------------------------------------------------------------------
1119etiss_uint8 rd = 0;
1120static BitArrayRange R_rd_0(11, 7);
1121rd += R_rd_0.read(ba) << 0;
1122etiss_uint8 rs1 = 0;
1123static BitArrayRange R_rs1_0(19, 15);
1124rs1 += R_rs1_0.read(ba) << 0;
1125etiss_uint8 rs2 = 0;
1126static BitArrayRange R_rs2_0(24, 20);
1127rs2 += R_rs2_0.read(ba) << 0;
1128
1129// -----------------------------------------------------------------------------
1130
1131 std::stringstream ss;
1132// -----------------------------------------------------------------------------
1133ss << "fsgnj_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1134// -----------------------------------------------------------------------------
1135 return ss.str();
1136 }
1137);
1138
1139// FSGNJN_D --------------------------------------------------------------------
1140static InstructionDefinition fsgnjn_d_rd_rs1_rs2 (
1141 ISA32_RV32IMACFD,
1142 "fsgnjn_d",
1143 (uint32_t) 0x22001053,
1144 (uint32_t) 0xfe00707f,
1145 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1146 {
1147
1148// -----------------------------------------------------------------------------
1149
1150// -----------------------------------------------------------------------------
1151
1152// -----------------------------------------------------------------------------
1153etiss_uint8 rd = 0;
1154static BitArrayRange R_rd_0(11, 7);
1155rd += R_rd_0.read(ba) << 0;
1156etiss_uint8 rs1 = 0;
1157static BitArrayRange R_rs1_0(19, 15);
1158rs1 += R_rs1_0.read(ba) << 0;
1159etiss_uint8 rs2 = 0;
1160static BitArrayRange R_rs2_0(24, 20);
1161rs2 += R_rs2_0.read(ba) << 0;
1162
1163// -----------------------------------------------------------------------------
1164
1165 {
1166 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1167
1168 cp.code() = std::string("//FSGNJN_D\n");
1169
1170// -----------------------------------------------------------------------------
1171cp.code() += "etiss_coverage_count(1, 130);\n";
1172{ // block
1173cp.code() += "etiss_coverage_count(1, 1169);\n";
1174cp.code() += "{ // block\n";
1175cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1176cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1177cp.code() += "} // block\n";
1178} // block
1179{ // block
1180cp.code() += "etiss_coverage_count(1, 5650);\n";
1181cp.code() += "{ // block\n";
1182cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1ULL))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";
1183cp.code() += "etiss_coverage_count(13, 5628, 5627, 5620, 5619, 5616, 5615, 5617, 5618, 5626, 5623, 5622, 5624, 5625);\n";
1184cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1185cp.code() += "etiss_coverage_count(4, 5637, 5635, 5634, 5636);\n";
1186cp.code() += "} // block\n";
1187} // block
1188cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1189cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1190// -----------------------------------------------------------------------------
1191 cp.getAffectedRegisters().add("instructionPointer", 32);
1192 }
1193
1194 return true;
1195 },
1196 0,
1197 [] (BitArray & ba, Instruction & instr)
1198 {
1199// -----------------------------------------------------------------------------
1200etiss_uint8 rd = 0;
1201static BitArrayRange R_rd_0(11, 7);
1202rd += R_rd_0.read(ba) << 0;
1203etiss_uint8 rs1 = 0;
1204static BitArrayRange R_rs1_0(19, 15);
1205rs1 += R_rs1_0.read(ba) << 0;
1206etiss_uint8 rs2 = 0;
1207static BitArrayRange R_rs2_0(24, 20);
1208rs2 += R_rs2_0.read(ba) << 0;
1209
1210// -----------------------------------------------------------------------------
1211
1212 std::stringstream ss;
1213// -----------------------------------------------------------------------------
1214ss << "fsgnjn_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1215// -----------------------------------------------------------------------------
1216 return ss.str();
1217 }
1218);
1219
1220// FSGNJX_D --------------------------------------------------------------------
1221static InstructionDefinition fsgnjx_d_rd_rs1_rs2 (
1222 ISA32_RV32IMACFD,
1223 "fsgnjx_d",
1224 (uint32_t) 0x22002053,
1225 (uint32_t) 0xfe00707f,
1226 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1227 {
1228
1229// -----------------------------------------------------------------------------
1230
1231// -----------------------------------------------------------------------------
1232
1233// -----------------------------------------------------------------------------
1234etiss_uint8 rd = 0;
1235static BitArrayRange R_rd_0(11, 7);
1236rd += R_rd_0.read(ba) << 0;
1237etiss_uint8 rs1 = 0;
1238static BitArrayRange R_rs1_0(19, 15);
1239rs1 += R_rs1_0.read(ba) << 0;
1240etiss_uint8 rs2 = 0;
1241static BitArrayRange R_rs2_0(24, 20);
1242rs2 += R_rs2_0.read(ba) << 0;
1243
1244// -----------------------------------------------------------------------------
1245
1246 {
1247 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1248
1249 cp.code() = std::string("//FSGNJX_D\n");
1250
1251// -----------------------------------------------------------------------------
1252cp.code() += "etiss_coverage_count(1, 131);\n";
1253{ // block
1254cp.code() += "etiss_coverage_count(1, 1169);\n";
1255cp.code() += "{ // block\n";
1256cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1257cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1258cp.code() += "} // block\n";
1259} // block
1260{ // block
1261cp.code() += "etiss_coverage_count(1, 5691);\n";
1262cp.code() += "{ // block\n";
1263cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n";
1264cp.code() += "etiss_coverage_count(10, 5669, 5668, 5656, 5654, 5653, 5666, 5661, 5659, 5658, 5667);\n";
1265cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1266cp.code() += "etiss_coverage_count(4, 5678, 5676, 5675, 5677);\n";
1267cp.code() += "} // block\n";
1268} // block
1269cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1270cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1271// -----------------------------------------------------------------------------
1272 cp.getAffectedRegisters().add("instructionPointer", 32);
1273 }
1274
1275 return true;
1276 },
1277 0,
1278 [] (BitArray & ba, Instruction & instr)
1279 {
1280// -----------------------------------------------------------------------------
1281etiss_uint8 rd = 0;
1282static BitArrayRange R_rd_0(11, 7);
1283rd += R_rd_0.read(ba) << 0;
1284etiss_uint8 rs1 = 0;
1285static BitArrayRange R_rs1_0(19, 15);
1286rs1 += R_rs1_0.read(ba) << 0;
1287etiss_uint8 rs2 = 0;
1288static BitArrayRange R_rs2_0(24, 20);
1289rs2 += R_rs2_0.read(ba) << 0;
1290
1291// -----------------------------------------------------------------------------
1292
1293 std::stringstream ss;
1294// -----------------------------------------------------------------------------
1295ss << "fsgnjx_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1296// -----------------------------------------------------------------------------
1297 return ss.str();
1298 }
1299);
1300
1301// FMIN_D ----------------------------------------------------------------------
1302static InstructionDefinition fmin_d_rd_rs1_rs2 (
1303 ISA32_RV32IMACFD,
1304 "fmin_d",
1305 (uint32_t) 0x2a000053,
1306 (uint32_t) 0xfe00707f,
1307 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1308 {
1309
1310// -----------------------------------------------------------------------------
1311
1312// -----------------------------------------------------------------------------
1313
1314// -----------------------------------------------------------------------------
1315etiss_uint8 rd = 0;
1316static BitArrayRange R_rd_0(11, 7);
1317rd += R_rd_0.read(ba) << 0;
1318etiss_uint8 rs1 = 0;
1319static BitArrayRange R_rs1_0(19, 15);
1320rs1 += R_rs1_0.read(ba) << 0;
1321etiss_uint8 rs2 = 0;
1322static BitArrayRange R_rs2_0(24, 20);
1323rs2 += R_rs2_0.read(ba) << 0;
1324
1325// -----------------------------------------------------------------------------
1326
1327 {
1328 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1329
1330 cp.code() = std::string("//FMIN_D\n");
1331
1332// -----------------------------------------------------------------------------
1333cp.code() += "etiss_coverage_count(1, 132);\n";
1334{ // block
1335cp.code() += "etiss_coverage_count(1, 1169);\n";
1336cp.code() += "{ // block\n";
1337cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1338cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1339cp.code() += "} // block\n";
1340} // block
1341{ // block
1342cp.code() += "etiss_coverage_count(1, 5742);\n";
1343cp.code() += "{ // block\n";
1344cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0LL);\n";
1345cp.code() += "etiss_coverage_count(9, 5705, 5704, 5697, 5695, 5694, 5702, 5700, 5699, 5703);\n";
1346cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1347cp.code() += "etiss_coverage_count(4, 5714, 5712, 5711, 5713);\n";
1348cp.code() += "etiss_uint32 flags = fget_flags();\n";
1349cp.code() += "etiss_coverage_count(2, 5729, 5728);\n";
1350cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1351cp.code() += "etiss_coverage_count(9, 5741, 5730, 5740, 5734, 5731, 5735, 5738, 5736, 5739);\n";
1352cp.code() += "} // block\n";
1353} // block
1354cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1355cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1356// -----------------------------------------------------------------------------
1357 cp.getAffectedRegisters().add("instructionPointer", 32);
1358 }
1359
1360 return true;
1361 },
1362 0,
1363 [] (BitArray & ba, Instruction & instr)
1364 {
1365// -----------------------------------------------------------------------------
1366etiss_uint8 rd = 0;
1367static BitArrayRange R_rd_0(11, 7);
1368rd += R_rd_0.read(ba) << 0;
1369etiss_uint8 rs1 = 0;
1370static BitArrayRange R_rs1_0(19, 15);
1371rs1 += R_rs1_0.read(ba) << 0;
1372etiss_uint8 rs2 = 0;
1373static BitArrayRange R_rs2_0(24, 20);
1374rs2 += R_rs2_0.read(ba) << 0;
1375
1376// -----------------------------------------------------------------------------
1377
1378 std::stringstream ss;
1379// -----------------------------------------------------------------------------
1380ss << "fmin_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1381// -----------------------------------------------------------------------------
1382 return ss.str();
1383 }
1384);
1385
1386// FMAX_D ----------------------------------------------------------------------
1387static InstructionDefinition fmax_d_rd_rs1_rs2 (
1388 ISA32_RV32IMACFD,
1389 "fmax_d",
1390 (uint32_t) 0x2a001053,
1391 (uint32_t) 0xfe00707f,
1392 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1393 {
1394
1395// -----------------------------------------------------------------------------
1396
1397// -----------------------------------------------------------------------------
1398
1399// -----------------------------------------------------------------------------
1400etiss_uint8 rd = 0;
1401static BitArrayRange R_rd_0(11, 7);
1402rd += R_rd_0.read(ba) << 0;
1403etiss_uint8 rs1 = 0;
1404static BitArrayRange R_rs1_0(19, 15);
1405rs1 += R_rs1_0.read(ba) << 0;
1406etiss_uint8 rs2 = 0;
1407static BitArrayRange R_rs2_0(24, 20);
1408rs2 += R_rs2_0.read(ba) << 0;
1409
1410// -----------------------------------------------------------------------------
1411
1412 {
1413 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1414
1415 cp.code() = std::string("//FMAX_D\n");
1416
1417// -----------------------------------------------------------------------------
1418cp.code() += "etiss_coverage_count(1, 133);\n";
1419{ // block
1420cp.code() += "etiss_coverage_count(1, 1169);\n";
1421cp.code() += "{ // block\n";
1422cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1423cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1424cp.code() += "} // block\n";
1425} // block
1426{ // block
1427cp.code() += "etiss_coverage_count(1, 5793);\n";
1428cp.code() += "{ // block\n";
1429cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n";
1430cp.code() += "etiss_coverage_count(9, 5756, 5755, 5748, 5746, 5745, 5753, 5751, 5750, 5754);\n";
1431cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1432cp.code() += "etiss_coverage_count(4, 5765, 5763, 5762, 5764);\n";
1433cp.code() += "etiss_uint32 flags = fget_flags();\n";
1434cp.code() += "etiss_coverage_count(2, 5780, 5779);\n";
1435cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1436cp.code() += "etiss_coverage_count(9, 5792, 5781, 5791, 5785, 5782, 5786, 5789, 5787, 5790);\n";
1437cp.code() += "} // block\n";
1438} // block
1439cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1440cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1441// -----------------------------------------------------------------------------
1442 cp.getAffectedRegisters().add("instructionPointer", 32);
1443 }
1444
1445 return true;
1446 },
1447 0,
1448 [] (BitArray & ba, Instruction & instr)
1449 {
1450// -----------------------------------------------------------------------------
1451etiss_uint8 rd = 0;
1452static BitArrayRange R_rd_0(11, 7);
1453rd += R_rd_0.read(ba) << 0;
1454etiss_uint8 rs1 = 0;
1455static BitArrayRange R_rs1_0(19, 15);
1456rs1 += R_rs1_0.read(ba) << 0;
1457etiss_uint8 rs2 = 0;
1458static BitArrayRange R_rs2_0(24, 20);
1459rs2 += R_rs2_0.read(ba) << 0;
1460
1461// -----------------------------------------------------------------------------
1462
1463 std::stringstream ss;
1464// -----------------------------------------------------------------------------
1465ss << "fmax_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1466// -----------------------------------------------------------------------------
1467 return ss.str();
1468 }
1469);
1470
1471// FCVT_S_D --------------------------------------------------------------------
1472static InstructionDefinition fcvt_s_d_rd_rm_rs1 (
1473 ISA32_RV32IMACFD,
1474 "fcvt_s_d",
1475 (uint32_t) 0x40100053,
1476 (uint32_t) 0xfff0007f,
1477 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1478 {
1479
1480// -----------------------------------------------------------------------------
1481
1482// -----------------------------------------------------------------------------
1483
1484// -----------------------------------------------------------------------------
1485etiss_uint8 rd = 0;
1486static BitArrayRange R_rd_0(11, 7);
1487rd += R_rd_0.read(ba) << 0;
1488etiss_uint8 rm = 0;
1489static BitArrayRange R_rm_0(14, 12);
1490rm += R_rm_0.read(ba) << 0;
1491etiss_uint8 rs1 = 0;
1492static BitArrayRange R_rs1_0(19, 15);
1493rs1 += R_rs1_0.read(ba) << 0;
1494
1495// -----------------------------------------------------------------------------
1496
1497 {
1498 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1499
1500 cp.code() = std::string("//FCVT_S_D\n");
1501
1502// -----------------------------------------------------------------------------
1503cp.code() += "etiss_coverage_count(1, 134);\n";
1504{ // block
1505cp.code() += "etiss_coverage_count(1, 1169);\n";
1506cp.code() += "{ // block\n";
1507cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1508cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1509cp.code() += "} // block\n";
1510} // block
1511{ // block
1512cp.code() += "etiss_coverage_count(1, 5812);\n";
1513cp.code() += "{ // block\n";
1514cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n";
1515cp.code() += "etiss_coverage_count(5, 5800, 5799, 5797, 5796, 5798);\n";
1516cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n";
1517cp.code() += "etiss_coverage_count(5, 5811, 5803, 5802, 5810, 5809);\n";
1518cp.code() += "} // block\n";
1519} // block
1520cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1521cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1522// -----------------------------------------------------------------------------
1523 cp.getAffectedRegisters().add("instructionPointer", 32);
1524 }
1525
1526 return true;
1527 },
1528 0,
1529 [] (BitArray & ba, Instruction & instr)
1530 {
1531// -----------------------------------------------------------------------------
1532etiss_uint8 rd = 0;
1533static BitArrayRange R_rd_0(11, 7);
1534rd += R_rd_0.read(ba) << 0;
1535etiss_uint8 rm = 0;
1536static BitArrayRange R_rm_0(14, 12);
1537rm += R_rm_0.read(ba) << 0;
1538etiss_uint8 rs1 = 0;
1539static BitArrayRange R_rs1_0(19, 15);
1540rs1 += R_rs1_0.read(ba) << 0;
1541
1542// -----------------------------------------------------------------------------
1543
1544 std::stringstream ss;
1545// -----------------------------------------------------------------------------
1546ss << "fcvt_s_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1547// -----------------------------------------------------------------------------
1548 return ss.str();
1549 }
1550);
1551
1552// FCVT_D_S --------------------------------------------------------------------
1553static InstructionDefinition fcvt_d_s_rd_rm_rs1 (
1554 ISA32_RV32IMACFD,
1555 "fcvt_d_s",
1556 (uint32_t) 0x42000053,
1557 (uint32_t) 0xfff0007f,
1558 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1559 {
1560
1561// -----------------------------------------------------------------------------
1562
1563// -----------------------------------------------------------------------------
1564
1565// -----------------------------------------------------------------------------
1566etiss_uint8 rd = 0;
1567static BitArrayRange R_rd_0(11, 7);
1568rd += R_rd_0.read(ba) << 0;
1569etiss_uint8 rm = 0;
1570static BitArrayRange R_rm_0(14, 12);
1571rm += R_rm_0.read(ba) << 0;
1572etiss_uint8 rs1 = 0;
1573static BitArrayRange R_rs1_0(19, 15);
1574rs1 += R_rs1_0.read(ba) << 0;
1575
1576// -----------------------------------------------------------------------------
1577
1578 {
1579 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1580
1581 cp.code() = std::string("//FCVT_D_S\n");
1582
1583// -----------------------------------------------------------------------------
1584cp.code() += "etiss_coverage_count(1, 135);\n";
1585{ // block
1586cp.code() += "etiss_coverage_count(1, 1169);\n";
1587cp.code() += "{ // block\n";
1588cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1589cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1590cp.code() += "} // block\n";
1591} // block
1592{ // block
1593cp.code() += "etiss_coverage_count(1, 5843);\n";
1594cp.code() += "{ // block\n";
1595cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n";
1596cp.code() += "etiss_coverage_count(6, 5820, 5819, 5817, 5816, 5815, 5818);\n";
1597{ // block
1598cp.code() += "etiss_coverage_count(1, 5830);\n";
1599cp.code() += "{ // block\n";
1600cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
1601cp.code() += "etiss_coverage_count(4, 5829, 5827, 5826, 5828);\n";
1602cp.code() += "} // block\n";
1603} // block
1604cp.code() += "} // block\n";
1605} // block
1606cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1607cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1608// -----------------------------------------------------------------------------
1609 cp.getAffectedRegisters().add("instructionPointer", 32);
1610 }
1611
1612 return true;
1613 },
1614 0,
1615 [] (BitArray & ba, Instruction & instr)
1616 {
1617// -----------------------------------------------------------------------------
1618etiss_uint8 rd = 0;
1619static BitArrayRange R_rd_0(11, 7);
1620rd += R_rd_0.read(ba) << 0;
1621etiss_uint8 rm = 0;
1622static BitArrayRange R_rm_0(14, 12);
1623rm += R_rm_0.read(ba) << 0;
1624etiss_uint8 rs1 = 0;
1625static BitArrayRange R_rs1_0(19, 15);
1626rs1 += R_rs1_0.read(ba) << 0;
1627
1628// -----------------------------------------------------------------------------
1629
1630 std::stringstream ss;
1631// -----------------------------------------------------------------------------
1632ss << "fcvt_d_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1633// -----------------------------------------------------------------------------
1634 return ss.str();
1635 }
1636);
1637
1638// FEQ_D -----------------------------------------------------------------------
1639static InstructionDefinition feq_d_rd_rs1_rs2 (
1640 ISA32_RV32IMACFD,
1641 "feq_d",
1642 (uint32_t) 0xa2002053,
1643 (uint32_t) 0xfe00707f,
1644 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1645 {
1646
1647// -----------------------------------------------------------------------------
1648
1649// -----------------------------------------------------------------------------
1650
1651// -----------------------------------------------------------------------------
1652etiss_uint8 rd = 0;
1653static BitArrayRange R_rd_0(11, 7);
1654rd += R_rd_0.read(ba) << 0;
1655etiss_uint8 rs1 = 0;
1656static BitArrayRange R_rs1_0(19, 15);
1657rs1 += R_rs1_0.read(ba) << 0;
1658etiss_uint8 rs2 = 0;
1659static BitArrayRange R_rs2_0(24, 20);
1660rs2 += R_rs2_0.read(ba) << 0;
1661
1662// -----------------------------------------------------------------------------
1663
1664 {
1665 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1666
1667 cp.code() = std::string("//FEQ_D\n");
1668
1669// -----------------------------------------------------------------------------
1670cp.code() += "etiss_coverage_count(1, 136);\n";
1671{ // block
1672cp.code() += "etiss_coverage_count(1, 1169);\n";
1673cp.code() += "{ // block\n";
1674cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1675cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1676cp.code() += "} // block\n";
1677} // block
1678{ // block
1679cp.code() += "etiss_coverage_count(1, 5909);\n";
1680cp.code() += "{ // block\n";
1681cp.code() += "etiss_uint64 res = 0LL;\n";
1682cp.code() += "etiss_coverage_count(2, 5846, 5845);\n";
1683cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0LL);\n";
1684cp.code() += "etiss_coverage_count(8, 5860, 5851, 5859, 5854, 5853, 5857, 5856, 5858);\n";
1685cp.code() += "etiss_coverage_count(1, 5880);\n";
1686if ((rd % 32ULL) != 0LL) { // conditional
1687cp.code() += "etiss_coverage_count(5, 5886, 5883, 5881, 5884, 5885);\n";
1688cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1689cp.code() += "etiss_coverage_count(5, 5893, 5891, 5890, 5888, 5892);\n";
1690} // conditional
1691cp.code() += "etiss_uint32 flags = fget_flags();\n";
1692cp.code() += "etiss_coverage_count(2, 5896, 5895);\n";
1693cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1694cp.code() += "etiss_coverage_count(9, 5908, 5897, 5907, 5901, 5898, 5902, 5905, 5903, 5906);\n";
1695cp.code() += "} // block\n";
1696} // block
1697cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1698cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1699// -----------------------------------------------------------------------------
1700 cp.getAffectedRegisters().add("instructionPointer", 32);
1701 }
1702
1703 return true;
1704 },
1705 0,
1706 [] (BitArray & ba, Instruction & instr)
1707 {
1708// -----------------------------------------------------------------------------
1709etiss_uint8 rd = 0;
1710static BitArrayRange R_rd_0(11, 7);
1711rd += R_rd_0.read(ba) << 0;
1712etiss_uint8 rs1 = 0;
1713static BitArrayRange R_rs1_0(19, 15);
1714rs1 += R_rs1_0.read(ba) << 0;
1715etiss_uint8 rs2 = 0;
1716static BitArrayRange R_rs2_0(24, 20);
1717rs2 += R_rs2_0.read(ba) << 0;
1718
1719// -----------------------------------------------------------------------------
1720
1721 std::stringstream ss;
1722// -----------------------------------------------------------------------------
1723ss << "feq_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1724// -----------------------------------------------------------------------------
1725 return ss.str();
1726 }
1727);
1728
1729// FLT_D -----------------------------------------------------------------------
1730static InstructionDefinition flt_d_rd_rs1_rs2 (
1731 ISA32_RV32IMACFD,
1732 "flt_d",
1733 (uint32_t) 0xa2001053,
1734 (uint32_t) 0xfe00707f,
1735 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1736 {
1737
1738// -----------------------------------------------------------------------------
1739
1740// -----------------------------------------------------------------------------
1741
1742// -----------------------------------------------------------------------------
1743etiss_uint8 rd = 0;
1744static BitArrayRange R_rd_0(11, 7);
1745rd += R_rd_0.read(ba) << 0;
1746etiss_uint8 rs1 = 0;
1747static BitArrayRange R_rs1_0(19, 15);
1748rs1 += R_rs1_0.read(ba) << 0;
1749etiss_uint8 rs2 = 0;
1750static BitArrayRange R_rs2_0(24, 20);
1751rs2 += R_rs2_0.read(ba) << 0;
1752
1753// -----------------------------------------------------------------------------
1754
1755 {
1756 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1757
1758 cp.code() = std::string("//FLT_D\n");
1759
1760// -----------------------------------------------------------------------------
1761cp.code() += "etiss_coverage_count(1, 137);\n";
1762{ // block
1763cp.code() += "etiss_coverage_count(1, 1169);\n";
1764cp.code() += "{ // block\n";
1765cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1766cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1767cp.code() += "} // block\n";
1768} // block
1769{ // block
1770cp.code() += "etiss_coverage_count(1, 5975);\n";
1771cp.code() += "{ // block\n";
1772cp.code() += "etiss_uint64 res = 0LL;\n";
1773cp.code() += "etiss_coverage_count(2, 5912, 5911);\n";
1774cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n";
1775cp.code() += "etiss_coverage_count(8, 5926, 5917, 5925, 5920, 5919, 5923, 5922, 5924);\n";
1776cp.code() += "etiss_coverage_count(1, 5946);\n";
1777if ((rd % 32ULL) != 0LL) { // conditional
1778cp.code() += "etiss_coverage_count(5, 5952, 5949, 5947, 5950, 5951);\n";
1779cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1780cp.code() += "etiss_coverage_count(5, 5959, 5957, 5956, 5954, 5958);\n";
1781} // conditional
1782cp.code() += "etiss_uint32 flags = fget_flags();\n";
1783cp.code() += "etiss_coverage_count(2, 5962, 5961);\n";
1784cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1785cp.code() += "etiss_coverage_count(9, 5974, 5963, 5973, 5967, 5964, 5968, 5971, 5969, 5972);\n";
1786cp.code() += "} // block\n";
1787} // block
1788cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1789cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1790// -----------------------------------------------------------------------------
1791 cp.getAffectedRegisters().add("instructionPointer", 32);
1792 }
1793
1794 return true;
1795 },
1796 0,
1797 [] (BitArray & ba, Instruction & instr)
1798 {
1799// -----------------------------------------------------------------------------
1800etiss_uint8 rd = 0;
1801static BitArrayRange R_rd_0(11, 7);
1802rd += R_rd_0.read(ba) << 0;
1803etiss_uint8 rs1 = 0;
1804static BitArrayRange R_rs1_0(19, 15);
1805rs1 += R_rs1_0.read(ba) << 0;
1806etiss_uint8 rs2 = 0;
1807static BitArrayRange R_rs2_0(24, 20);
1808rs2 += R_rs2_0.read(ba) << 0;
1809
1810// -----------------------------------------------------------------------------
1811
1812 std::stringstream ss;
1813// -----------------------------------------------------------------------------
1814ss << "flt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1815// -----------------------------------------------------------------------------
1816 return ss.str();
1817 }
1818);
1819
1820// FLE_D -----------------------------------------------------------------------
1821static InstructionDefinition fle_d_rd_rs1_rs2 (
1822 ISA32_RV32IMACFD,
1823 "fle_d",
1824 (uint32_t) 0xa2000053,
1825 (uint32_t) 0xfe00707f,
1826 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1827 {
1828
1829// -----------------------------------------------------------------------------
1830
1831// -----------------------------------------------------------------------------
1832
1833// -----------------------------------------------------------------------------
1834etiss_uint8 rd = 0;
1835static BitArrayRange R_rd_0(11, 7);
1836rd += R_rd_0.read(ba) << 0;
1837etiss_uint8 rs1 = 0;
1838static BitArrayRange R_rs1_0(19, 15);
1839rs1 += R_rs1_0.read(ba) << 0;
1840etiss_uint8 rs2 = 0;
1841static BitArrayRange R_rs2_0(24, 20);
1842rs2 += R_rs2_0.read(ba) << 0;
1843
1844// -----------------------------------------------------------------------------
1845
1846 {
1847 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1848
1849 cp.code() = std::string("//FLE_D\n");
1850
1851// -----------------------------------------------------------------------------
1852cp.code() += "etiss_coverage_count(1, 138);\n";
1853{ // block
1854cp.code() += "etiss_coverage_count(1, 1169);\n";
1855cp.code() += "{ // block\n";
1856cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1857cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1858cp.code() += "} // block\n";
1859} // block
1860{ // block
1861cp.code() += "etiss_coverage_count(1, 6041);\n";
1862cp.code() += "{ // block\n";
1863cp.code() += "etiss_uint64 res = 0LL;\n";
1864cp.code() += "etiss_coverage_count(2, 5978, 5977);\n";
1865cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n";
1866cp.code() += "etiss_coverage_count(8, 5992, 5983, 5991, 5986, 5985, 5989, 5988, 5990);\n";
1867cp.code() += "etiss_coverage_count(1, 6012);\n";
1868if ((rd % 32ULL) != 0LL) { // conditional
1869cp.code() += "etiss_coverage_count(5, 6018, 6015, 6013, 6016, 6017);\n";
1870cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1871cp.code() += "etiss_coverage_count(5, 6025, 6023, 6022, 6020, 6024);\n";
1872} // conditional
1873cp.code() += "etiss_uint32 flags = fget_flags();\n";
1874cp.code() += "etiss_coverage_count(2, 6028, 6027);\n";
1875cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1876cp.code() += "etiss_coverage_count(9, 6040, 6029, 6039, 6033, 6030, 6034, 6037, 6035, 6038);\n";
1877cp.code() += "} // block\n";
1878} // block
1879cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1880cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1881// -----------------------------------------------------------------------------
1882 cp.getAffectedRegisters().add("instructionPointer", 32);
1883 }
1884
1885 return true;
1886 },
1887 0,
1888 [] (BitArray & ba, Instruction & instr)
1889 {
1890// -----------------------------------------------------------------------------
1891etiss_uint8 rd = 0;
1892static BitArrayRange R_rd_0(11, 7);
1893rd += R_rd_0.read(ba) << 0;
1894etiss_uint8 rs1 = 0;
1895static BitArrayRange R_rs1_0(19, 15);
1896rs1 += R_rs1_0.read(ba) << 0;
1897etiss_uint8 rs2 = 0;
1898static BitArrayRange R_rs2_0(24, 20);
1899rs2 += R_rs2_0.read(ba) << 0;
1900
1901// -----------------------------------------------------------------------------
1902
1903 std::stringstream ss;
1904// -----------------------------------------------------------------------------
1905ss << "fle_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1906// -----------------------------------------------------------------------------
1907 return ss.str();
1908 }
1909);
1910
1911// FCLASS_D --------------------------------------------------------------------
1912static InstructionDefinition fclass_d_rd_rs1 (
1913 ISA32_RV32IMACFD,
1914 "fclass_d",
1915 (uint32_t) 0xe2001053,
1916 (uint32_t) 0xfff0707f,
1917 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1918 {
1919
1920// -----------------------------------------------------------------------------
1921
1922// -----------------------------------------------------------------------------
1923
1924// -----------------------------------------------------------------------------
1925etiss_uint8 rd = 0;
1926static BitArrayRange R_rd_0(11, 7);
1927rd += R_rd_0.read(ba) << 0;
1928etiss_uint8 rs1 = 0;
1929static BitArrayRange R_rs1_0(19, 15);
1930rs1 += R_rs1_0.read(ba) << 0;
1931
1932// -----------------------------------------------------------------------------
1933
1934 {
1935 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1936
1937 cp.code() = std::string("//FCLASS_D\n");
1938
1939// -----------------------------------------------------------------------------
1940cp.code() += "etiss_coverage_count(1, 139);\n";
1941{ // block
1942cp.code() += "etiss_coverage_count(1, 1169);\n";
1943cp.code() += "{ // block\n";
1944cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1945cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1946cp.code() += "} // block\n";
1947} // block
1948{ // block
1949cp.code() += "etiss_coverage_count(1, 6054);\n";
1950cp.code() += "{ // block\n";
1951cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
1952cp.code() += "etiss_coverage_count(8, 6053, 6046, 6045, 6043, 6052, 6051, 6049, 6048);\n";
1953cp.code() += "} // block\n";
1954} // block
1955cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1956cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1957// -----------------------------------------------------------------------------
1958 cp.getAffectedRegisters().add("instructionPointer", 32);
1959 }
1960
1961 return true;
1962 },
1963 0,
1964 [] (BitArray & ba, Instruction & instr)
1965 {
1966// -----------------------------------------------------------------------------
1967etiss_uint8 rd = 0;
1968static BitArrayRange R_rd_0(11, 7);
1969rd += R_rd_0.read(ba) << 0;
1970etiss_uint8 rs1 = 0;
1971static BitArrayRange R_rs1_0(19, 15);
1972rs1 += R_rs1_0.read(ba) << 0;
1973
1974// -----------------------------------------------------------------------------
1975
1976 std::stringstream ss;
1977// -----------------------------------------------------------------------------
1978ss << "fclass_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
1979// -----------------------------------------------------------------------------
1980 return ss.str();
1981 }
1982);
1983
1984// FCVT_W_D --------------------------------------------------------------------
1985static InstructionDefinition fcvt_w_d_rd_rm_rs1 (
1986 ISA32_RV32IMACFD,
1987 "fcvt_w_d",
1988 (uint32_t) 0xc2000053,
1989 (uint32_t) 0xfff0007f,
1990 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1991 {
1992
1993// -----------------------------------------------------------------------------
1994
1995// -----------------------------------------------------------------------------
1996
1997// -----------------------------------------------------------------------------
1998etiss_uint8 rd = 0;
1999static BitArrayRange R_rd_0(11, 7);
2000rd += R_rd_0.read(ba) << 0;
2001etiss_uint8 rm = 0;
2002static BitArrayRange R_rm_0(14, 12);
2003rm += R_rm_0.read(ba) << 0;
2004etiss_uint8 rs1 = 0;
2005static BitArrayRange R_rs1_0(19, 15);
2006rs1 += R_rs1_0.read(ba) << 0;
2007
2008// -----------------------------------------------------------------------------
2009
2010 {
2011 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2012
2013 cp.code() = std::string("//FCVT_W_D\n");
2014
2015// -----------------------------------------------------------------------------
2016cp.code() += "etiss_coverage_count(1, 140);\n";
2017{ // block
2018cp.code() += "etiss_coverage_count(1, 1169);\n";
2019cp.code() += "{ // block\n";
2020cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2021cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2022cp.code() += "} // block\n";
2023} // block
2024{ // block
2025cp.code() += "etiss_coverage_count(1, 6112);\n";
2026cp.code() += "{ // block\n";
2027cp.code() += "etiss_int32 res = 0LL;\n";
2028cp.code() += "etiss_coverage_count(2, 6057, 6056);\n";
2029cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0LL, " + std::to_string(rm) + "ULL);\n";
2030cp.code() += "etiss_coverage_count(7, 6069, 6062, 6068, 6065, 6064, 6066, 6067);\n";
2031cp.code() += "etiss_coverage_count(1, 6083);\n";
2032if ((rd % 32ULL) != 0LL) { // conditional
2033cp.code() += "etiss_coverage_count(5, 6089, 6086, 6084, 6087, 6088);\n";
2034cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2035cp.code() += "etiss_coverage_count(5, 6096, 6094, 6093, 6091, 6095);\n";
2036} // conditional
2037cp.code() += "etiss_uint32 flags = fget_flags();\n";
2038cp.code() += "etiss_coverage_count(2, 6099, 6098);\n";
2039cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2040cp.code() += "etiss_coverage_count(9, 6111, 6100, 6110, 6104, 6101, 6105, 6108, 6106, 6109);\n";
2041cp.code() += "} // block\n";
2042} // block
2043cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2044cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2045// -----------------------------------------------------------------------------
2046 cp.getAffectedRegisters().add("instructionPointer", 32);
2047 }
2048
2049 return true;
2050 },
2051 0,
2052 [] (BitArray & ba, Instruction & instr)
2053 {
2054// -----------------------------------------------------------------------------
2055etiss_uint8 rd = 0;
2056static BitArrayRange R_rd_0(11, 7);
2057rd += R_rd_0.read(ba) << 0;
2058etiss_uint8 rm = 0;
2059static BitArrayRange R_rm_0(14, 12);
2060rm += R_rm_0.read(ba) << 0;
2061etiss_uint8 rs1 = 0;
2062static BitArrayRange R_rs1_0(19, 15);
2063rs1 += R_rs1_0.read(ba) << 0;
2064
2065// -----------------------------------------------------------------------------
2066
2067 std::stringstream ss;
2068// -----------------------------------------------------------------------------
2069ss << "fcvt_w_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2070// -----------------------------------------------------------------------------
2071 return ss.str();
2072 }
2073);
2074
2075// FCVT_WU_D -------------------------------------------------------------------
2076static InstructionDefinition fcvt_wu_d_rd_rm_rs1 (
2077 ISA32_RV32IMACFD,
2078 "fcvt_wu_d",
2079 (uint32_t) 0xc2100053,
2080 (uint32_t) 0xfff0007f,
2081 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2082 {
2083
2084// -----------------------------------------------------------------------------
2085
2086// -----------------------------------------------------------------------------
2087
2088// -----------------------------------------------------------------------------
2089etiss_uint8 rd = 0;
2090static BitArrayRange R_rd_0(11, 7);
2091rd += R_rd_0.read(ba) << 0;
2092etiss_uint8 rm = 0;
2093static BitArrayRange R_rm_0(14, 12);
2094rm += R_rm_0.read(ba) << 0;
2095etiss_uint8 rs1 = 0;
2096static BitArrayRange R_rs1_0(19, 15);
2097rs1 += R_rs1_0.read(ba) << 0;
2098
2099// -----------------------------------------------------------------------------
2100
2101 {
2102 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2103
2104 cp.code() = std::string("//FCVT_WU_D\n");
2105
2106// -----------------------------------------------------------------------------
2107cp.code() += "etiss_coverage_count(1, 141);\n";
2108{ // block
2109cp.code() += "etiss_coverage_count(1, 1169);\n";
2110cp.code() += "{ // block\n";
2111cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2112cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2113cp.code() += "} // block\n";
2114} // block
2115{ // block
2116cp.code() += "etiss_coverage_count(1, 6173);\n";
2117cp.code() += "{ // block\n";
2118cp.code() += "etiss_uint32 res = 0LL;\n";
2119cp.code() += "etiss_coverage_count(2, 6115, 6114);\n";
2120cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n";
2121cp.code() += "etiss_coverage_count(7, 6127, 6120, 6126, 6123, 6122, 6124, 6125);\n";
2122cp.code() += "etiss_coverage_count(1, 6141);\n";
2123if ((rd % 32ULL) != 0LL) { // conditional
2124cp.code() += "etiss_coverage_count(5, 6147, 6144, 6142, 6145, 6146);\n";
2125cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n";
2126cp.code() += "etiss_coverage_count(7, 6157, 6152, 6151, 6149, 6156, 6154, 6153);\n";
2127} // conditional
2128cp.code() += "etiss_uint32 flags = fget_flags();\n";
2129cp.code() += "etiss_coverage_count(2, 6160, 6159);\n";
2130cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2131cp.code() += "etiss_coverage_count(9, 6172, 6161, 6171, 6165, 6162, 6166, 6169, 6167, 6170);\n";
2132cp.code() += "} // block\n";
2133} // block
2134cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2135cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2136// -----------------------------------------------------------------------------
2137 cp.getAffectedRegisters().add("instructionPointer", 32);
2138 }
2139
2140 return true;
2141 },
2142 0,
2143 [] (BitArray & ba, Instruction & instr)
2144 {
2145// -----------------------------------------------------------------------------
2146etiss_uint8 rd = 0;
2147static BitArrayRange R_rd_0(11, 7);
2148rd += R_rd_0.read(ba) << 0;
2149etiss_uint8 rm = 0;
2150static BitArrayRange R_rm_0(14, 12);
2151rm += R_rm_0.read(ba) << 0;
2152etiss_uint8 rs1 = 0;
2153static BitArrayRange R_rs1_0(19, 15);
2154rs1 += R_rs1_0.read(ba) << 0;
2155
2156// -----------------------------------------------------------------------------
2157
2158 std::stringstream ss;
2159// -----------------------------------------------------------------------------
2160ss << "fcvt_wu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2161// -----------------------------------------------------------------------------
2162 return ss.str();
2163 }
2164);
2165
2166// FCVT_D_W --------------------------------------------------------------------
2167static InstructionDefinition fcvt_d_w_rd_rm_rs1 (
2168 ISA32_RV32IMACFD,
2169 "fcvt_d_w",
2170 (uint32_t) 0xd2000053,
2171 (uint32_t) 0xfff0007f,
2172 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2173 {
2174
2175// -----------------------------------------------------------------------------
2176
2177// -----------------------------------------------------------------------------
2178
2179// -----------------------------------------------------------------------------
2180etiss_uint8 rd = 0;
2181static BitArrayRange R_rd_0(11, 7);
2182rd += R_rd_0.read(ba) << 0;
2183etiss_uint8 rm = 0;
2184static BitArrayRange R_rm_0(14, 12);
2185rm += R_rm_0.read(ba) << 0;
2186etiss_uint8 rs1 = 0;
2187static BitArrayRange R_rs1_0(19, 15);
2188rs1 += R_rs1_0.read(ba) << 0;
2189
2190// -----------------------------------------------------------------------------
2191
2192 {
2193 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2194
2195 cp.code() = std::string("//FCVT_D_W\n");
2196
2197// -----------------------------------------------------------------------------
2198cp.code() += "etiss_coverage_count(1, 142);\n";
2199{ // block
2200cp.code() += "etiss_coverage_count(1, 1169);\n";
2201cp.code() += "{ // block\n";
2202cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2203cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2204cp.code() += "} // block\n";
2205} // block
2206{ // block
2207cp.code() += "etiss_coverage_count(1, 6206);\n";
2208cp.code() += "{ // block\n";
2209cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
2210cp.code() += "etiss_coverage_count(8, 6184, 6183, 6180, 6179, 6178, 6176, 6181, 6182);\n";
2211cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2212cp.code() += "etiss_coverage_count(4, 6193, 6191, 6190, 6192);\n";
2213cp.code() += "} // block\n";
2214} // block
2215cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2216cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2217// -----------------------------------------------------------------------------
2218 cp.getAffectedRegisters().add("instructionPointer", 32);
2219 }
2220
2221 return true;
2222 },
2223 0,
2224 [] (BitArray & ba, Instruction & instr)
2225 {
2226// -----------------------------------------------------------------------------
2227etiss_uint8 rd = 0;
2228static BitArrayRange R_rd_0(11, 7);
2229rd += R_rd_0.read(ba) << 0;
2230etiss_uint8 rm = 0;
2231static BitArrayRange R_rm_0(14, 12);
2232rm += R_rm_0.read(ba) << 0;
2233etiss_uint8 rs1 = 0;
2234static BitArrayRange R_rs1_0(19, 15);
2235rs1 += R_rs1_0.read(ba) << 0;
2236
2237// -----------------------------------------------------------------------------
2238
2239 std::stringstream ss;
2240// -----------------------------------------------------------------------------
2241ss << "fcvt_d_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2242// -----------------------------------------------------------------------------
2243 return ss.str();
2244 }
2245);
2246
2247// FCVT_D_WU -------------------------------------------------------------------
2248static InstructionDefinition fcvt_d_wu_rd_rm_rs1 (
2249 ISA32_RV32IMACFD,
2250 "fcvt_d_wu",
2251 (uint32_t) 0xd2100053,
2252 (uint32_t) 0xfff0007f,
2253 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2254 {
2255
2256// -----------------------------------------------------------------------------
2257
2258// -----------------------------------------------------------------------------
2259
2260// -----------------------------------------------------------------------------
2261etiss_uint8 rd = 0;
2262static BitArrayRange R_rd_0(11, 7);
2263rd += R_rd_0.read(ba) << 0;
2264etiss_uint8 rm = 0;
2265static BitArrayRange R_rm_0(14, 12);
2266rm += R_rm_0.read(ba) << 0;
2267etiss_uint8 rs1 = 0;
2268static BitArrayRange R_rs1_0(19, 15);
2269rs1 += R_rs1_0.read(ba) << 0;
2270
2271// -----------------------------------------------------------------------------
2272
2273 {
2274 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2275
2276 cp.code() = std::string("//FCVT_D_WU\n");
2277
2278// -----------------------------------------------------------------------------
2279cp.code() += "etiss_coverage_count(1, 143);\n";
2280{ // block
2281cp.code() += "etiss_coverage_count(1, 1169);\n";
2282cp.code() += "{ // block\n";
2283cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2284cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2285cp.code() += "} // block\n";
2286} // block
2287{ // block
2288cp.code() += "etiss_coverage_count(1, 6239);\n";
2289cp.code() += "{ // block\n";
2290cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2291cp.code() += "etiss_coverage_count(8, 6217, 6216, 6213, 6212, 6211, 6209, 6214, 6215);\n";
2292cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
2293cp.code() += "etiss_coverage_count(4, 6226, 6224, 6223, 6225);\n";
2294cp.code() += "} // block\n";
2295} // block
2296cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2297cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2298// -----------------------------------------------------------------------------
2299 cp.getAffectedRegisters().add("instructionPointer", 32);
2300 }
2301
2302 return true;
2303 },
2304 0,
2305 [] (BitArray & ba, Instruction & instr)
2306 {
2307// -----------------------------------------------------------------------------
2308etiss_uint8 rd = 0;
2309static BitArrayRange R_rd_0(11, 7);
2310rd += R_rd_0.read(ba) << 0;
2311etiss_uint8 rm = 0;
2312static BitArrayRange R_rm_0(14, 12);
2313rm += R_rm_0.read(ba) << 0;
2314etiss_uint8 rs1 = 0;
2315static BitArrayRange R_rs1_0(19, 15);
2316rs1 += R_rs1_0.read(ba) << 0;
2317
2318// -----------------------------------------------------------------------------
2319
2320 std::stringstream ss;
2321// -----------------------------------------------------------------------------
2322ss << "fcvt_d_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2323// -----------------------------------------------------------------------------
2324 return ss.str();
2325 }
2326);
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
fclass_d_rd_rs1
static InstructionDefinition fclass_d_rd_rs1(ISA32_RV32IMACFD, "fclass_d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_D\n");cp.code()+="etiss_coverage_count(1, 139);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6054);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(8, 6053, 6046, 6045, 6043, 6052, 6051, 6049, 6048);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnjx_d_rd_rs1_rs2
static InstructionDefinition fsgnjx_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjx_d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_D\n");cp.code()+="etiss_coverage_count(1, 131);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5691);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) & 9223372036854775808ULL);\n";cp.code()+="etiss_coverage_count(10, 5669, 5668, 5656, 5654, 5653, 5666, 5661, 5659, 5658, 5667);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5678, 5676, 5675, 5677);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjn_d_rd_rs1_rs2
static InstructionDefinition fsgnjn_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjn_d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_D\n");cp.code()+="etiss_coverage_count(1, 130);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5650);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL))) << 63) | ((((((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="etiss_coverage_count(13, 5628, 5627, 5620, 5619, 5616, 5615, 5617, 5618, 5626, 5623, 5622, 5624, 5625);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5637, 5635, 5634, 5636);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_w_d_rd_rm_rs1
static InstructionDefinition fcvt_w_d_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_w_d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_D\n");cp.code()+="etiss_coverage_count(1, 140);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6112);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6057, 6056);\n";cp.code()+="res = fcvt_64_32(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6069, 6062, 6068, 6065, 6064, 6066, 6067);\n";cp.code()+="etiss_coverage_count(1, 6083);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6089, 6086, 6084, 6087, 6088);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6096, 6094, 6093, 6091, 6095);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6099, 6098);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6111, 6100, 6110, 6104, 6101, 6105, 6108, 6106, 6109);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmin_d_rd_rs1_rs2
static InstructionDefinition fmin_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fmin_d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_D\n");cp.code()+="etiss_coverage_count(1, 132);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5742);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 0LL);\n";cp.code()+="etiss_coverage_count(9, 5705, 5704, 5697, 5695, 5694, 5702, 5700, 5699, 5703);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5714, 5712, 5711, 5713);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5729, 5728);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5741, 5730, 5740, 5734, 5731, 5735, 5738, 5736, 5739);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fdiv_d_rd_rm_rs1_rs2
static InstructionDefinition fdiv_d_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fdiv_d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_D\n");cp.code()+="etiss_coverage_count(1, 127);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5528);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5491, 5490, 5482, 5480, 5479, 5487, 5485, 5484, 5489, 5488);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5500, 5498, 5497, 5499);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5515, 5514);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5527, 5516, 5526, 5520, 5517, 5521, 5524, 5522, 5525);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmax_d_rd_rs1_rs2
static InstructionDefinition fmax_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fmax_d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_D\n");cp.code()+="etiss_coverage_count(1, 133);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5793);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), 1ULL);\n";cp.code()+="etiss_coverage_count(9, 5756, 5755, 5748, 5746, 5745, 5753, 5751, 5750, 5754);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5765, 5763, 5762, 5764);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5780, 5779);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5792, 5781, 5791, 5785, 5782, 5786, 5789, 5787, 5790);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_s_d_rd_rm_rs1
static InstructionDefinition fcvt_s_d_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_D\n");cp.code()+="etiss_coverage_count(1, 134);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5812);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(5, 5800, 5799, 5797, 5796, 5798);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL + res;\n";cp.code()+="etiss_coverage_count(5, 5811, 5803, 5802, 5810, 5809);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
feq_d_rd_rs1_rs2
static InstructionDefinition feq_d_rd_rs1_rs2(ISA32_RV32IMACFD, "feq_d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_D\n");cp.code()+="etiss_coverage_count(1, 136);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5909);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5846, 5845);\n";cp.code()+="res = fcmp_d(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 0LL);\n";cp.code()+="etiss_coverage_count(8, 5860, 5851, 5859, 5854, 5853, 5857, 5856, 5858);\n";cp.code()+="etiss_coverage_count(1, 5880);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5886, 5883, 5881, 5884, 5885);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5893, 5891, 5890, 5888, 5892);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5896, 5895);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5908, 5897, 5907, 5901, 5898, 5902, 5905, 5903, 5906);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fle_d_rd_rs1_rs2
static InstructionDefinition fle_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fle_d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_D\n");cp.code()+="etiss_coverage_count(1, 138);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6041);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5978, 5977);\n";cp.code()+="res = fcmp_d(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 1ULL);\n";cp.code()+="etiss_coverage_count(8, 5992, 5983, 5991, 5986, 5985, 5989, 5988, 5990);\n";cp.code()+="etiss_coverage_count(1, 6012);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6018, 6015, 6013, 6016, 6017);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 6025, 6023, 6022, 6020, 6024);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6028, 6027);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6040, 6029, 6039, 6033, 6030, 6034, 6037, 6035, 6038);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsub_d_rd_rm_rs1_rs2
static InstructionDefinition fsub_d_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fsub_d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_D\n");cp.code()+="etiss_coverage_count(1, 125);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5424);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5387, 5386, 5378, 5376, 5375, 5383, 5381, 5380, 5385, 5384);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5396, 5394, 5393, 5395);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5411, 5410);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5423, 5412, 5422, 5416, 5413, 5417, 5420, 5418, 5421);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fnmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmadd_d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_D\n");cp.code()+="etiss_coverage_count(1, 122);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5262);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5225, 5224, 5210, 5208, 5207, 5215, 5213, 5212, 5220, 5218, 5217, 5221, 5223, 5222);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5234, 5232, 5231, 5233);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5249, 5248);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5261, 5250, 5260, 5254, 5251, 5255, 5258, 5256, 5259);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fnmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmsub_d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_D\n");cp.code()+="etiss_coverage_count(1, 123);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5320);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5283, 5282, 5268, 5266, 5265, 5273, 5271, 5270, 5278, 5276, 5275, 5279, 5281, 5280);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5292, 5290, 5289, 5291);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5307, 5306);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5319, 5308, 5318, 5312, 5309, 5313, 5316, 5314, 5317);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmul_d_rd_rm_rs1_rs2
static InstructionDefinition fmul_d_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fmul_d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_D\n");cp.code()+="etiss_coverage_count(1, 126);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5476);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5439, 5438, 5430, 5428, 5427, 5435, 5433, 5432, 5437, 5436);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5448, 5446, 5445, 5447);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5463, 5462);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5475, 5464, 5474, 5468, 5465, 5469, 5472, 5470, 5473);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmsub_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmsub_d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_D\n");cp.code()+="etiss_coverage_count(1, 121);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5204);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5167, 5166, 5152, 5150, 5149, 5157, 5155, 5154, 5162, 5160, 5159, 5163, 5165, 5164);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5176, 5174, 5173, 5175);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5191, 5190);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5203, 5192, 5202, 5196, 5193, 5197, 5200, 5198, 5201);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fsgnj_d_rd_rs1_rs2
static InstructionDefinition fsgnj_d_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnj_d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_D\n");cp.code()+="etiss_coverage_count(1, 129);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5612);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]) >> (63ULL)) & 1ULL)) << 63) | ((((((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]) >> (0LL)) & 9223372036854775807ULL)));\n";cp.code()+="etiss_coverage_count(12, 5590, 5589, 5582, 5579, 5578, 5580, 5581, 5588, 5585, 5584, 5586, 5587);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5599, 5597, 5596, 5598);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_d_s_rd_rm_rs1
static InstructionDefinition fcvt_d_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_d_s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_S\n");cp.code()+="etiss_coverage_count(1, 135);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5843);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 5820, 5819, 5817, 5816, 5815, 5818);\n";{ cp.code()+="etiss_coverage_count(1, 5830);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5829, 5827, 5826, 5828);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_w_rd_rm_rs1
static InstructionDefinition fcvt_d_w_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_d_w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_W\n");cp.code()+="etiss_coverage_count(1, 142);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6206);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6184, 6183, 6180, 6179, 6178, 6176, 6181, 6182);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6193, 6191, 6190, 6192);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fld_rd_rs1_imm
static InstructionDefinition fld_rd_rs1_imm(ISA32_RV32IMACFD, "fld",(uint32_t) 0x003007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="etiss_coverage_count(1, 118);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5067);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5038, 5037, 5033, 5032, 5030, 5036, 5034);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 5045, 5044, 5042, 5041);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5054, 5052, 5051, 5053);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fsd_imm_rs1_rs2
static InstructionDefinition fsd_imm_rs1_rs2(ISA32_RV32IMACFD, "fsd",(uint32_t) 0x003027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="etiss_coverage_count(1, 119);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5088);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 5078, 5077, 5073, 5072, 5070, 5076, 5074);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5087, 5081, 5080, 5086, 5084, 5083);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsqrt_d_rd_rm_rs1
static InstructionDefinition fsqrt_d_rd_rm_rs1(ISA32_RV32IMACFD, "fsqrt_d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_D\n");cp.code()+="etiss_coverage_count(1, 128);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5575);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(7, 5538, 5537, 5534, 5532, 5531, 5536, 5535);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5547, 5545, 5544, 5546);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5562, 5561);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5574, 5563, 5573, 5567, 5564, 5568, 5571, 5569, 5572);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmadd_d_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmadd_d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_D\n");cp.code()+="etiss_coverage_count(1, 120);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5146);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 5109, 5108, 5094, 5092, 5091, 5099, 5097, 5096, 5104, 5102, 5101, 5105, 5107, 5106);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5118, 5116, 5115, 5117);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5133, 5132);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5145, 5134, 5144, 5138, 5135, 5139, 5142, 5140, 5143);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fcvt_wu_d_rd_rm_rs1
static InstructionDefinition fcvt_wu_d_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_wu_d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_D\n");cp.code()+="etiss_coverage_count(1, 141);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6173);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 6115, 6114);\n";cp.code()+="res = fcvt_64_32(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 6127, 6120, 6126, 6123, 6122, 6124, 6125);\n";cp.code()+="etiss_coverage_count(1, 6141);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6147, 6144, 6142, 6145, 6146);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(7, 6157, 6152, 6151, 6149, 6156, 6154, 6153);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 6160, 6159);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 6172, 6161, 6171, 6165, 6162, 6166, 6169, 6167, 6170);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
flt_d_rd_rs1_rs2
static InstructionDefinition flt_d_rd_rs1_rs2(ISA32_RV32IMACFD, "flt_d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_D\n");cp.code()+="etiss_coverage_count(1, 137);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5975);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 5912, 5911);\n";cp.code()+="res = fcmp_d(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL], ((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL], 2ULL);\n";cp.code()+="etiss_coverage_count(8, 5926, 5917, 5925, 5920, 5919, 5923, 5922, 5924);\n";cp.code()+="etiss_coverage_count(1, 5946);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 5952, 5949, 5947, 5950, 5951);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 5959, 5957, 5956, 5954, 5958);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5962, 5961);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5974, 5963, 5973, 5967, 5964, 5968, 5971, 5969, 5972);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_d_wu_rd_rm_rs1
static InstructionDefinition fcvt_d_wu_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_d_wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_WU\n");cp.code()+="etiss_coverage_count(1, 143);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6239);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 6217, 6216, 6213, 6212, 6211, 6209, 6214, 6215);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6226, 6224, 6223, 6225);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fadd_d_rd_rm_rs1_rs2
static InstructionDefinition fadd_d_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fadd_d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_D\n");cp.code()+="etiss_coverage_count(1, 124);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5372);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(10, 5335, 5334, 5326, 5324, 5323, 5331, 5329, 5328, 5333, 5332);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 5344, 5342, 5341, 5343);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 5359, 5358);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 5371, 5360, 5370, 5364, 5361, 5365, 5368, 5366, 5369);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition types.h:90
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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