ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
etiss
ArchImpl
RV32IMACFD
RV32IMACFD.h
Go to the documentation of this file.
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#ifndef ETISS_RV32IMACFDArch_RV32IMACFD_H_
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#define ETISS_RV32IMACFDArch_RV32IMACFD_H_
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#include <stdio.h>
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#include "etiss/jit/CPU.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#pragma pack(push, 1)
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struct
RV32IMACFD
{
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ETISS_CPU
cpu
;
// original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
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etiss_uint32
ZERO
;
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etiss_uint32
RA
;
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etiss_uint32
SP
;
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etiss_uint32
GP
;
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etiss_uint32
TP
;
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etiss_uint32
T0
;
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etiss_uint32
T1
;
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etiss_uint32
T2
;
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etiss_uint32
S0
;
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etiss_uint32
S1
;
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etiss_uint32
A0
;
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etiss_uint32
A1
;
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etiss_uint32
A2
;
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etiss_uint32
A3
;
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etiss_uint32
A4
;
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etiss_uint32
A5
;
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etiss_uint32
A6
;
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etiss_uint32
A7
;
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etiss_uint32
S2
;
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etiss_uint32
S3
;
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etiss_uint32
S4
;
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etiss_uint32
S5
;
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etiss_uint32
S6
;
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etiss_uint32
S7
;
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etiss_uint32
S8
;
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etiss_uint32
S9
;
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etiss_uint32
S10
;
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etiss_uint32
S11
;
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etiss_uint32
T3
;
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etiss_uint32
T4
;
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etiss_uint32
T5
;
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etiss_uint32
T6
;
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etiss_uint32
*
X
[32];
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etiss_uint32
ins_X
[32];
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etiss_uint32
FENCE
[8];
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etiss_uint8
RES
[8];
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etiss_uint8
PRIV
;
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etiss_uint32
DPC
;
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etiss_uint32
FCSR
;
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etiss_uint32
MSTATUS
;
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etiss_uint32
MIE
;
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etiss_uint32
MIP
;
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etiss_uint32
*
CSR
[4096];
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etiss_uint32
ins_CSR
[4096];
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etiss_uint64
F
[32];
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etiss_uint32
RES_ADDR
;
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};
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#pragma pack(pop)
// undo changes
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typedef
struct
RV32IMACFD
RV32IMACFD
;
// convenient use of X instead of struct X in generated C code
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#ifdef __cplusplus
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}
// extern "C"
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#endif
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#endif
etiss_uint64
uint64_t etiss_uint64
Definition:
types.h:96
etiss_uint32
uint32_t etiss_uint32
Definition:
types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition:
types.h:87
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition:
CPU.h:89
RV32IMACFD
Generated on Thu, 24 Oct 2024 10:16:12 +0200.
Definition:
RV32IMACFD.h:16
RV32IMACFD::MIP
etiss_uint32 MIP
Definition:
RV32IMACFD.h:59
RV32IMACFD::MSTATUS
etiss_uint32 MSTATUS
Definition:
RV32IMACFD.h:57
RV32IMACFD::RES_ADDR
etiss_uint32 RES_ADDR
Definition:
RV32IMACFD.h:63
RV32IMACFD::S11
etiss_uint32 S11
Definition:
RV32IMACFD.h:45
RV32IMACFD::A5
etiss_uint32 A5
Definition:
RV32IMACFD.h:33
RV32IMACFD::S4
etiss_uint32 S4
Definition:
RV32IMACFD.h:38
RV32IMACFD::X
etiss_uint32 * X[32]
Definition:
RV32IMACFD.h:50
RV32IMACFD::A7
etiss_uint32 A7
Definition:
RV32IMACFD.h:35
RV32IMACFD::T1
etiss_uint32 T1
Definition:
RV32IMACFD.h:24
RV32IMACFD::T4
etiss_uint32 T4
Definition:
RV32IMACFD.h:47
RV32IMACFD::S0
etiss_uint32 S0
Definition:
RV32IMACFD.h:26
RV32IMACFD::F
etiss_uint64 F[32]
Definition:
RV32IMACFD.h:62
RV32IMACFD::CSR
etiss_uint32 * CSR[4096]
Definition:
RV32IMACFD.h:60
RV32IMACFD::SP
etiss_uint32 SP
Definition:
RV32IMACFD.h:20
RV32IMACFD::S1
etiss_uint32 S1
Definition:
RV32IMACFD.h:27
RV32IMACFD::A3
etiss_uint32 A3
Definition:
RV32IMACFD.h:31
RV32IMACFD::ins_CSR
etiss_uint32 ins_CSR[4096]
Definition:
RV32IMACFD.h:61
RV32IMACFD::A2
etiss_uint32 A2
Definition:
RV32IMACFD.h:30
RV32IMACFD::T5
etiss_uint32 T5
Definition:
RV32IMACFD.h:48
RV32IMACFD::S5
etiss_uint32 S5
Definition:
RV32IMACFD.h:39
RV32IMACFD::ZERO
etiss_uint32 ZERO
Definition:
RV32IMACFD.h:18
RV32IMACFD::S8
etiss_uint32 S8
Definition:
RV32IMACFD.h:42
RV32IMACFD::TP
etiss_uint32 TP
Definition:
RV32IMACFD.h:22
RV32IMACFD::A1
etiss_uint32 A1
Definition:
RV32IMACFD.h:29
RV32IMACFD::cpu
ETISS_CPU cpu
Definition:
RV32IMACFD.h:17
RV32IMACFD::ins_X
etiss_uint32 ins_X[32]
Definition:
RV32IMACFD.h:51
RV32IMACFD::PRIV
etiss_uint8 PRIV
Definition:
RV32IMACFD.h:54
RV32IMACFD::A4
etiss_uint32 A4
Definition:
RV32IMACFD.h:32
RV32IMACFD::MIE
etiss_uint32 MIE
Definition:
RV32IMACFD.h:58
RV32IMACFD::T3
etiss_uint32 T3
Definition:
RV32IMACFD.h:46
RV32IMACFD::S10
etiss_uint32 S10
Definition:
RV32IMACFD.h:44
RV32IMACFD::S7
etiss_uint32 S7
Definition:
RV32IMACFD.h:41
RV32IMACFD::FCSR
etiss_uint32 FCSR
Definition:
RV32IMACFD.h:56
RV32IMACFD::T6
etiss_uint32 T6
Definition:
RV32IMACFD.h:49
RV32IMACFD::S3
etiss_uint32 S3
Definition:
RV32IMACFD.h:37
RV32IMACFD::S6
etiss_uint32 S6
Definition:
RV32IMACFD.h:40
RV32IMACFD::DPC
etiss_uint32 DPC
Definition:
RV32IMACFD.h:55
RV32IMACFD::S9
etiss_uint32 S9
Definition:
RV32IMACFD.h:43
RV32IMACFD::T0
etiss_uint32 T0
Definition:
RV32IMACFD.h:23
RV32IMACFD::RA
etiss_uint32 RA
Definition:
RV32IMACFD.h:19
RV32IMACFD::RES
etiss_uint8 RES[8]
Definition:
RV32IMACFD.h:53
RV32IMACFD::GP
etiss_uint32 GP
Definition:
RV32IMACFD.h:21
RV32IMACFD::T2
etiss_uint32 T2
Definition:
RV32IMACFD.h:25
RV32IMACFD::A0
etiss_uint32 A0
Definition:
RV32IMACFD.h:28
RV32IMACFD::A6
etiss_uint32 A6
Definition:
RV32IMACFD.h:34
RV32IMACFD::FENCE
etiss_uint32 FENCE[8]
Definition:
RV32IMACFD.h:52
RV32IMACFD::S2
etiss_uint32 S2
Definition:
RV32IMACFD.h:36
Generated on Thu Oct 24 2024 09:39:43 for ETISS 0.8.0 by
1.9.1