ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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etiss
ArchImpl
RV32IMACFD
RV32IMACFD.h
Go to the documentation of this file.
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#ifndef ETISS_RV32IMACFDArch_RV32IMACFD_H_
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#define ETISS_RV32IMACFDArch_RV32IMACFD_H_
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#include <stdio.h>
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#include "etiss/jit/CPU.h"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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#pragma pack(push, 1)
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struct
RV32IMACFD
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{
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ETISS_CPU
cpu
;
// original cpu struct must be defined as the first field of the new structure.
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// This allows to cast X * to ETISS_CPU * and vice versa
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etiss_uint32
ZERO
;
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etiss_uint32
RA
;
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etiss_uint32
SP
;
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etiss_uint32
GP
;
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etiss_uint32
TP
;
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etiss_uint32
T0
;
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etiss_uint32
T1
;
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etiss_uint32
T2
;
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etiss_uint32
S0
;
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etiss_uint32
S1
;
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etiss_uint32
A0
;
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etiss_uint32
A1
;
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etiss_uint32
A2
;
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etiss_uint32
A3
;
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etiss_uint32
A4
;
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etiss_uint32
A5
;
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etiss_uint32
A6
;
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etiss_uint32
A7
;
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etiss_uint32
S2
;
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etiss_uint32
S3
;
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etiss_uint32
S4
;
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etiss_uint32
S5
;
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etiss_uint32
S6
;
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etiss_uint32
S7
;
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etiss_uint32
S8
;
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etiss_uint32
S9
;
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etiss_uint32
S10
;
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etiss_uint32
S11
;
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etiss_uint32
T3
;
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etiss_uint32
T4
;
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etiss_uint32
T5
;
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etiss_uint32
T6
;
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etiss_uint32
*
X
[32];
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etiss_uint32
ins_X
[32];
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etiss_uint32
FENCE
[8];
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etiss_uint8
RES
[8];
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etiss_uint8
PRIV
;
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etiss_uint32
DPC
;
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etiss_uint32
FCSR
;
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etiss_uint32
FFLAGS
;
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etiss_uint32
FRM
;
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etiss_uint32
MSTATUS
;
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etiss_uint32
MIE
;
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etiss_uint32
MIP
;
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etiss_uint32
CYCLE
;
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etiss_uint32
CYCLEH
;
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etiss_uint32
MCYCLE
;
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etiss_uint32
MCYCLEH
;
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etiss_uint32
TIME
;
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etiss_uint32
TIMEH
;
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etiss_uint32
INSTRET
;
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etiss_uint32
INSTRETH
;
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etiss_uint32
MINSTRET
;
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etiss_uint32
MINSTRETH
;
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etiss_uint32
MVENDORID
;
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etiss_uint32
MARCHID
;
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etiss_uint32
MIMPID
;
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etiss_uint32
MHARTID
;
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etiss_uint32
MISA
;
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etiss_uint32
MEDELEG
;
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etiss_uint32
MIDELEG
;
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etiss_uint32
MTVEC
;
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etiss_uint32
MCOUNTEREN
;
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etiss_uint32
MSCRATCH
;
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etiss_uint32
MEPC
;
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etiss_uint32
MCAUSE
;
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etiss_uint32
MTVAL
;
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etiss_uint32
*
CSR
[4096];
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etiss_uint32
ins_CSR
[4096];
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etiss_uint64
FT0
;
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etiss_uint64
FT1
;
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etiss_uint64
FT2
;
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etiss_uint64
FT3
;
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etiss_uint64
FT4
;
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etiss_uint64
FT5
;
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etiss_uint64
FT6
;
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etiss_uint64
FT7
;
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etiss_uint64
FS0
;
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etiss_uint64
FS1
;
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etiss_uint64
FA0
;
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etiss_uint64
FA1
;
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etiss_uint64
FA2
;
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etiss_uint64
FA3
;
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etiss_uint64
FA4
;
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etiss_uint64
FA5
;
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etiss_uint64
FA6
;
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etiss_uint64
FA7
;
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etiss_uint64
FS2
;
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etiss_uint64
FS3
;
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etiss_uint64
FS4
;
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etiss_uint64
FS5
;
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etiss_uint64
FS6
;
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etiss_uint64
FS7
;
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etiss_uint64
FS8
;
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etiss_uint64
FS9
;
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etiss_uint64
FS10
;
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etiss_uint64
FS11
;
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etiss_uint64
FT8
;
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etiss_uint64
FT9
;
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etiss_uint64
FT10
;
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etiss_uint64
FT11
;
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etiss_uint64
*
F
[32];
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etiss_uint64
ins_F
[32];
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etiss_uint32
RES_ADDR
;
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};
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#pragma pack(pop)
// undo changes
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// convenient use of X instead of struct X in generated C code
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typedef
struct
RV32IMACFD
RV32IMACFD
;
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#ifdef __cplusplus
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}
// extern "C"
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#endif
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#endif
etiss_uint64
uint64_t etiss_uint64
Definition
types.h:58
etiss_uint32
uint32_t etiss_uint32
Definition
types.h:55
etiss_uint8
uint8_t etiss_uint8
Definition
types.h:49
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition
CPU.h:51
RV32IMACFD
Generated on Fri, 19 Jun 2026 08:11:15 +0000.
Definition
RV32IMACFD.h:18
RV32IMACFD::MTVEC
etiss_uint32 MTVEC
Definition
RV32IMACFD.h:82
RV32IMACFD::MIP
etiss_uint32 MIP
Definition
RV32IMACFD.h:64
RV32IMACFD::FT5
etiss_uint64 FT5
Definition
RV32IMACFD.h:95
RV32IMACFD::MISA
etiss_uint32 MISA
Definition
RV32IMACFD.h:79
RV32IMACFD::FS3
etiss_uint64 FS3
Definition
RV32IMACFD.h:109
RV32IMACFD::MSTATUS
etiss_uint32 MSTATUS
Definition
RV32IMACFD.h:62
RV32IMACFD::FT11
etiss_uint64 FT11
Definition
RV32IMACFD.h:121
RV32IMACFD::FS0
etiss_uint64 FS0
Definition
RV32IMACFD.h:98
RV32IMACFD::MCYCLEH
etiss_uint32 MCYCLEH
Definition
RV32IMACFD.h:68
RV32IMACFD::FT4
etiss_uint64 FT4
Definition
RV32IMACFD.h:94
RV32IMACFD::RES_ADDR
etiss_uint32 RES_ADDR
Definition
RV32IMACFD.h:124
RV32IMACFD::S11
etiss_uint32 S11
Definition
RV32IMACFD.h:48
RV32IMACFD::A5
etiss_uint32 A5
Definition
RV32IMACFD.h:36
RV32IMACFD::FT2
etiss_uint64 FT2
Definition
RV32IMACFD.h:92
RV32IMACFD::S4
etiss_uint32 S4
Definition
RV32IMACFD.h:41
RV32IMACFD::MVENDORID
etiss_uint32 MVENDORID
Definition
RV32IMACFD.h:75
RV32IMACFD::FS9
etiss_uint64 FS9
Definition
RV32IMACFD.h:115
RV32IMACFD::FA5
etiss_uint64 FA5
Definition
RV32IMACFD.h:105
RV32IMACFD::MEPC
etiss_uint32 MEPC
Definition
RV32IMACFD.h:85
RV32IMACFD::FA0
etiss_uint64 FA0
Definition
RV32IMACFD.h:100
RV32IMACFD::X
etiss_uint32 * X[32]
Definition
RV32IMACFD.h:53
RV32IMACFD::MARCHID
etiss_uint32 MARCHID
Definition
RV32IMACFD.h:76
RV32IMACFD::A7
etiss_uint32 A7
Definition
RV32IMACFD.h:38
RV32IMACFD::T1
etiss_uint32 T1
Definition
RV32IMACFD.h:27
RV32IMACFD::T4
etiss_uint32 T4
Definition
RV32IMACFD.h:50
RV32IMACFD::S0
etiss_uint32 S0
Definition
RV32IMACFD.h:29
RV32IMACFD::CSR
etiss_uint32 * CSR[4096]
Definition
RV32IMACFD.h:88
RV32IMACFD::SP
etiss_uint32 SP
Definition
RV32IMACFD.h:23
RV32IMACFD::FA1
etiss_uint64 FA1
Definition
RV32IMACFD.h:101
RV32IMACFD::FRM
etiss_uint32 FRM
Definition
RV32IMACFD.h:61
RV32IMACFD::FS11
etiss_uint64 FS11
Definition
RV32IMACFD.h:117
RV32IMACFD::FS2
etiss_uint64 FS2
Definition
RV32IMACFD.h:108
RV32IMACFD::FS10
etiss_uint64 FS10
Definition
RV32IMACFD.h:116
RV32IMACFD::FA7
etiss_uint64 FA7
Definition
RV32IMACFD.h:107
RV32IMACFD::FT8
etiss_uint64 FT8
Definition
RV32IMACFD.h:118
RV32IMACFD::FFLAGS
etiss_uint32 FFLAGS
Definition
RV32IMACFD.h:60
RV32IMACFD::CYCLE
etiss_uint32 CYCLE
Definition
RV32IMACFD.h:65
RV32IMACFD::S1
etiss_uint32 S1
Definition
RV32IMACFD.h:30
RV32IMACFD::TIME
etiss_uint32 TIME
Definition
RV32IMACFD.h:69
RV32IMACFD::TIMEH
etiss_uint32 TIMEH
Definition
RV32IMACFD.h:70
RV32IMACFD::A3
etiss_uint32 A3
Definition
RV32IMACFD.h:34
RV32IMACFD::FA2
etiss_uint64 FA2
Definition
RV32IMACFD.h:102
RV32IMACFD::ins_CSR
etiss_uint32 ins_CSR[4096]
Definition
RV32IMACFD.h:89
RV32IMACFD::INSTRETH
etiss_uint32 INSTRETH
Definition
RV32IMACFD.h:72
RV32IMACFD::FS4
etiss_uint64 FS4
Definition
RV32IMACFD.h:110
RV32IMACFD::A2
etiss_uint32 A2
Definition
RV32IMACFD.h:33
RV32IMACFD::FT3
etiss_uint64 FT3
Definition
RV32IMACFD.h:93
RV32IMACFD::MCAUSE
etiss_uint32 MCAUSE
Definition
RV32IMACFD.h:86
RV32IMACFD::T5
etiss_uint32 T5
Definition
RV32IMACFD.h:51
RV32IMACFD::MCYCLE
etiss_uint32 MCYCLE
Definition
RV32IMACFD.h:67
RV32IMACFD::S5
etiss_uint32 S5
Definition
RV32IMACFD.h:42
RV32IMACFD::ZERO
etiss_uint32 ZERO
Definition
RV32IMACFD.h:21
RV32IMACFD::S8
etiss_uint32 S8
Definition
RV32IMACFD.h:45
RV32IMACFD::FT7
etiss_uint64 FT7
Definition
RV32IMACFD.h:97
RV32IMACFD::TP
etiss_uint32 TP
Definition
RV32IMACFD.h:25
RV32IMACFD::MSCRATCH
etiss_uint32 MSCRATCH
Definition
RV32IMACFD.h:84
RV32IMACFD::A1
etiss_uint32 A1
Definition
RV32IMACFD.h:32
RV32IMACFD::cpu
ETISS_CPU cpu
Definition
RV32IMACFD.h:19
RV32IMACFD::ins_X
etiss_uint32 ins_X[32]
Definition
RV32IMACFD.h:54
RV32IMACFD::ins_F
etiss_uint64 ins_F[32]
Definition
RV32IMACFD.h:123
RV32IMACFD::MINSTRETH
etiss_uint32 MINSTRETH
Definition
RV32IMACFD.h:74
RV32IMACFD::PRIV
etiss_uint8 PRIV
Definition
RV32IMACFD.h:57
RV32IMACFD::A4
etiss_uint32 A4
Definition
RV32IMACFD.h:35
RV32IMACFD::FS5
etiss_uint64 FS5
Definition
RV32IMACFD.h:111
RV32IMACFD::MIE
etiss_uint32 MIE
Definition
RV32IMACFD.h:63
RV32IMACFD::T3
etiss_uint32 T3
Definition
RV32IMACFD.h:49
RV32IMACFD::FT1
etiss_uint64 FT1
Definition
RV32IMACFD.h:91
RV32IMACFD::S10
etiss_uint32 S10
Definition
RV32IMACFD.h:47
RV32IMACFD::FS8
etiss_uint64 FS8
Definition
RV32IMACFD.h:114
RV32IMACFD::FT10
etiss_uint64 FT10
Definition
RV32IMACFD.h:120
RV32IMACFD::S7
etiss_uint32 S7
Definition
RV32IMACFD.h:44
RV32IMACFD::FCSR
etiss_uint32 FCSR
Definition
RV32IMACFD.h:59
RV32IMACFD::CYCLEH
etiss_uint32 CYCLEH
Definition
RV32IMACFD.h:66
RV32IMACFD::T6
etiss_uint32 T6
Definition
RV32IMACFD.h:52
RV32IMACFD::S3
etiss_uint32 S3
Definition
RV32IMACFD.h:40
RV32IMACFD::S6
etiss_uint32 S6
Definition
RV32IMACFD.h:43
RV32IMACFD::MHARTID
etiss_uint32 MHARTID
Definition
RV32IMACFD.h:78
RV32IMACFD::FA6
etiss_uint64 FA6
Definition
RV32IMACFD.h:106
RV32IMACFD::FA4
etiss_uint64 FA4
Definition
RV32IMACFD.h:104
RV32IMACFD::MINSTRET
etiss_uint32 MINSTRET
Definition
RV32IMACFD.h:73
RV32IMACFD::MEDELEG
etiss_uint32 MEDELEG
Definition
RV32IMACFD.h:80
RV32IMACFD::DPC
etiss_uint32 DPC
Definition
RV32IMACFD.h:58
RV32IMACFD::S9
etiss_uint32 S9
Definition
RV32IMACFD.h:46
RV32IMACFD::FT6
etiss_uint64 FT6
Definition
RV32IMACFD.h:96
RV32IMACFD::T0
etiss_uint32 T0
Definition
RV32IMACFD.h:26
RV32IMACFD::RA
etiss_uint32 RA
Definition
RV32IMACFD.h:22
RV32IMACFD::RES
etiss_uint8 RES[8]
Definition
RV32IMACFD.h:56
RV32IMACFD::GP
etiss_uint32 GP
Definition
RV32IMACFD.h:24
RV32IMACFD::MCOUNTEREN
etiss_uint32 MCOUNTEREN
Definition
RV32IMACFD.h:83
RV32IMACFD::FS1
etiss_uint64 FS1
Definition
RV32IMACFD.h:99
RV32IMACFD::T2
etiss_uint32 T2
Definition
RV32IMACFD.h:28
RV32IMACFD::A0
etiss_uint32 A0
Definition
RV32IMACFD.h:31
RV32IMACFD::MIMPID
etiss_uint32 MIMPID
Definition
RV32IMACFD.h:77
RV32IMACFD::A6
etiss_uint32 A6
Definition
RV32IMACFD.h:37
RV32IMACFD::MIDELEG
etiss_uint32 MIDELEG
Definition
RV32IMACFD.h:81
RV32IMACFD::MTVAL
etiss_uint32 MTVAL
Definition
RV32IMACFD.h:87
RV32IMACFD::INSTRET
etiss_uint32 INSTRET
Definition
RV32IMACFD.h:71
RV32IMACFD::FT9
etiss_uint64 FT9
Definition
RV32IMACFD.h:119
RV32IMACFD::FT0
etiss_uint64 FT0
Definition
RV32IMACFD.h:90
RV32IMACFD::FS7
etiss_uint64 FS7
Definition
RV32IMACFD.h:113
RV32IMACFD::FENCE
etiss_uint32 FENCE[8]
Definition
RV32IMACFD.h:55
RV32IMACFD::FA3
etiss_uint64 FA3
Definition
RV32IMACFD.h:103
RV32IMACFD::FS6
etiss_uint64 FS6
Definition
RV32IMACFD.h:112
RV32IMACFD::F
etiss_uint64 * F[32]
Definition
RV32IMACFD.h:122
RV32IMACFD::S2
etiss_uint32 S2
Definition
RV32IMACFD.h:39
Generated on Fri Jun 19 2026 09:37:30 for ETISS 0.11.2 by
1.9.8