ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV64IMACFD_tum_rvmInstr.cpp
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1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// MUL -------------------------------------------------------------------------
16static InstructionDefinition mul_rd_rs1_rs2 (
17 ISA32_RV64IMACFD,
18 "mul",
19 (uint32_t) 0x2000033,
20 (uint32_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rs1 = 0;
33static BitArrayRange R_rs1_0(19, 15);
34rs1 += R_rs1_0.read(ba) << 0;
35etiss_uint8 rs2 = 0;
36static BitArrayRange R_rs2_0(24, 20);
37rs2 += R_rs2_0.read(ba) << 0;
38
39// -----------------------------------------------------------------------------
40
41 {
42 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43
44 cp.code() = std::string("//MUL\n");
45
46// -----------------------------------------------------------------------------
47cp.code() += "etiss_coverage_count(1, 240);\n";
48{ // block
49cp.code() += "etiss_coverage_count(1, 1169);\n";
50cp.code() += "{ // block\n";
51cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53cp.code() += "} // block\n";
54} // block
55{ // block
56cp.code() += "etiss_coverage_count(1, 7655);\n";
57cp.code() += "{ // block\n";
58cp.code() += "etiss_coverage_count(1, 7623);\n";
59if ((rd % 32ULL) != 0LL) { // conditional
60cp.code() += "etiss_coverage_count(5, 7629, 7626, 7624, 7627, 7628);\n";
61{ // block
62cp.code() += "etiss_coverage_count(1, 7654);\n";
63cp.code() += "{ // block\n";
64cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
65cp.code() += "etiss_coverage_count(10, 7644, 7643, 7636, 7635, 7634, 7632, 7642, 7641, 7640, 7638);\n";
66cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
67cp.code() += "etiss_coverage_count(6, 7653, 7649, 7648, 7646, 7652, 7650);\n";
68cp.code() += "} // block\n";
69} // block
70} // conditional
71cp.code() += "} // block\n";
72} // block
73cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75// -----------------------------------------------------------------------------
76 cp.getAffectedRegisters().add("instructionPointer", 32);
77 }
78
79 return true;
80 },
81 0,
82 [] (BitArray & ba, Instruction & instr)
83 {
84// -----------------------------------------------------------------------------
85etiss_uint8 rd = 0;
86static BitArrayRange R_rd_0(11, 7);
87rd += R_rd_0.read(ba) << 0;
88etiss_uint8 rs1 = 0;
89static BitArrayRange R_rs1_0(19, 15);
90rs1 += R_rs1_0.read(ba) << 0;
91etiss_uint8 rs2 = 0;
92static BitArrayRange R_rs2_0(24, 20);
93rs2 += R_rs2_0.read(ba) << 0;
94
95// -----------------------------------------------------------------------------
96
97 std::stringstream ss;
98// -----------------------------------------------------------------------------
99ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
100// -----------------------------------------------------------------------------
101 return ss.str();
102 }
103);
104
105// MULH ------------------------------------------------------------------------
106static InstructionDefinition mulh_rd_rs1_rs2 (
107 ISA32_RV64IMACFD,
108 "mulh",
109 (uint32_t) 0x2001033,
110 (uint32_t) 0xfe00707f,
111 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
112 {
113
114// -----------------------------------------------------------------------------
115
116// -----------------------------------------------------------------------------
117
118// -----------------------------------------------------------------------------
119etiss_uint8 rd = 0;
120static BitArrayRange R_rd_0(11, 7);
121rd += R_rd_0.read(ba) << 0;
122etiss_uint8 rs1 = 0;
123static BitArrayRange R_rs1_0(19, 15);
124rs1 += R_rs1_0.read(ba) << 0;
125etiss_uint8 rs2 = 0;
126static BitArrayRange R_rs2_0(24, 20);
127rs2 += R_rs2_0.read(ba) << 0;
128
129// -----------------------------------------------------------------------------
130
131 {
132 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
133
134 cp.code() = std::string("//MULH\n");
135
136// -----------------------------------------------------------------------------
137cp.code() += "etiss_coverage_count(1, 241);\n";
138{ // block
139cp.code() += "etiss_coverage_count(1, 1169);\n";
140cp.code() += "{ // block\n";
141cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
142cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
143cp.code() += "} // block\n";
144} // block
145{ // block
146cp.code() += "etiss_coverage_count(1, 7683);\n";
147cp.code() += "{ // block\n";
148cp.code() += "etiss_coverage_count(1, 7656);\n";
149if ((rd % 32ULL) != 0LL) { // conditional
150cp.code() += "etiss_coverage_count(5, 7662, 7659, 7657, 7660, 7661);\n";
151{ // block
152cp.code() += "etiss_coverage_count(1, 7682);\n";
153cp.code() += "{ // block\n";
154cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
155cp.code() += "etiss_coverage_count(13, 7681, 7667, 7666, 7664, 7680, 7673, 7672, 7671, 7669, 7679, 7678, 7677, 7675);\n";
156cp.code() += "} // block\n";
157} // block
158} // conditional
159cp.code() += "} // block\n";
160} // block
161cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
162cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
163// -----------------------------------------------------------------------------
164 cp.getAffectedRegisters().add("instructionPointer", 32);
165 }
166
167 return true;
168 },
169 0,
170 [] (BitArray & ba, Instruction & instr)
171 {
172// -----------------------------------------------------------------------------
173etiss_uint8 rd = 0;
174static BitArrayRange R_rd_0(11, 7);
175rd += R_rd_0.read(ba) << 0;
176etiss_uint8 rs1 = 0;
177static BitArrayRange R_rs1_0(19, 15);
178rs1 += R_rs1_0.read(ba) << 0;
179etiss_uint8 rs2 = 0;
180static BitArrayRange R_rs2_0(24, 20);
181rs2 += R_rs2_0.read(ba) << 0;
182
183// -----------------------------------------------------------------------------
184
185 std::stringstream ss;
186// -----------------------------------------------------------------------------
187ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
188// -----------------------------------------------------------------------------
189 return ss.str();
190 }
191);
192
193// MULHSU ----------------------------------------------------------------------
194static InstructionDefinition mulhsu_rd_rs1_rs2 (
195 ISA32_RV64IMACFD,
196 "mulhsu",
197 (uint32_t) 0x2002033,
198 (uint32_t) 0xfe00707f,
199 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
200 {
201
202// -----------------------------------------------------------------------------
203
204// -----------------------------------------------------------------------------
205
206// -----------------------------------------------------------------------------
207etiss_uint8 rd = 0;
208static BitArrayRange R_rd_0(11, 7);
209rd += R_rd_0.read(ba) << 0;
210etiss_uint8 rs1 = 0;
211static BitArrayRange R_rs1_0(19, 15);
212rs1 += R_rs1_0.read(ba) << 0;
213etiss_uint8 rs2 = 0;
214static BitArrayRange R_rs2_0(24, 20);
215rs2 += R_rs2_0.read(ba) << 0;
216
217// -----------------------------------------------------------------------------
218
219 {
220 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
221
222 cp.code() = std::string("//MULHSU\n");
223
224// -----------------------------------------------------------------------------
225cp.code() += "etiss_coverage_count(1, 242);\n";
226{ // block
227cp.code() += "etiss_coverage_count(1, 1169);\n";
228cp.code() += "{ // block\n";
229cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
230cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
231cp.code() += "} // block\n";
232} // block
233{ // block
234cp.code() += "etiss_coverage_count(1, 7710);\n";
235cp.code() += "{ // block\n";
236cp.code() += "etiss_coverage_count(1, 7684);\n";
237if ((rd % 32ULL) != 0LL) { // conditional
238cp.code() += "etiss_coverage_count(5, 7690, 7687, 7685, 7688, 7689);\n";
239{ // block
240cp.code() += "etiss_coverage_count(1, 7709);\n";
241cp.code() += "{ // block\n";
242cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
243cp.code() += "etiss_coverage_count(12, 7708, 7695, 7694, 7692, 7707, 7701, 7700, 7699, 7697, 7706, 7705, 7703);\n";
244cp.code() += "} // block\n";
245} // block
246} // conditional
247cp.code() += "} // block\n";
248} // block
249cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
250cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
251// -----------------------------------------------------------------------------
252 cp.getAffectedRegisters().add("instructionPointer", 32);
253 }
254
255 return true;
256 },
257 0,
258 [] (BitArray & ba, Instruction & instr)
259 {
260// -----------------------------------------------------------------------------
261etiss_uint8 rd = 0;
262static BitArrayRange R_rd_0(11, 7);
263rd += R_rd_0.read(ba) << 0;
264etiss_uint8 rs1 = 0;
265static BitArrayRange R_rs1_0(19, 15);
266rs1 += R_rs1_0.read(ba) << 0;
267etiss_uint8 rs2 = 0;
268static BitArrayRange R_rs2_0(24, 20);
269rs2 += R_rs2_0.read(ba) << 0;
270
271// -----------------------------------------------------------------------------
272
273 std::stringstream ss;
274// -----------------------------------------------------------------------------
275ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
276// -----------------------------------------------------------------------------
277 return ss.str();
278 }
279);
280
281// MULHU -----------------------------------------------------------------------
282static InstructionDefinition mulhu_rd_rs1_rs2 (
283 ISA32_RV64IMACFD,
284 "mulhu",
285 (uint32_t) 0x2003033,
286 (uint32_t) 0xfe00707f,
287 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
288 {
289
290// -----------------------------------------------------------------------------
291
292// -----------------------------------------------------------------------------
293
294// -----------------------------------------------------------------------------
295etiss_uint8 rd = 0;
296static BitArrayRange R_rd_0(11, 7);
297rd += R_rd_0.read(ba) << 0;
298etiss_uint8 rs1 = 0;
299static BitArrayRange R_rs1_0(19, 15);
300rs1 += R_rs1_0.read(ba) << 0;
301etiss_uint8 rs2 = 0;
302static BitArrayRange R_rs2_0(24, 20);
303rs2 += R_rs2_0.read(ba) << 0;
304
305// -----------------------------------------------------------------------------
306
307 {
308 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
309
310 cp.code() = std::string("//MULHU\n");
311
312// -----------------------------------------------------------------------------
313cp.code() += "etiss_coverage_count(1, 243);\n";
314{ // block
315cp.code() += "etiss_coverage_count(1, 1169);\n";
316cp.code() += "{ // block\n";
317cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
318cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
319cp.code() += "} // block\n";
320} // block
321{ // block
322cp.code() += "etiss_coverage_count(1, 7736);\n";
323cp.code() += "{ // block\n";
324cp.code() += "etiss_coverage_count(1, 7711);\n";
325if ((rd % 32ULL) != 0LL) { // conditional
326cp.code() += "etiss_coverage_count(5, 7717, 7714, 7712, 7715, 7716);\n";
327{ // block
328cp.code() += "etiss_coverage_count(1, 7735);\n";
329cp.code() += "{ // block\n";
330cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
331cp.code() += "etiss_coverage_count(11, 7734, 7722, 7721, 7719, 7733, 7727, 7726, 7724, 7732, 7731, 7729);\n";
332cp.code() += "} // block\n";
333} // block
334} // conditional
335cp.code() += "} // block\n";
336} // block
337cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
338cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
339// -----------------------------------------------------------------------------
340 cp.getAffectedRegisters().add("instructionPointer", 32);
341 }
342
343 return true;
344 },
345 0,
346 [] (BitArray & ba, Instruction & instr)
347 {
348// -----------------------------------------------------------------------------
349etiss_uint8 rd = 0;
350static BitArrayRange R_rd_0(11, 7);
351rd += R_rd_0.read(ba) << 0;
352etiss_uint8 rs1 = 0;
353static BitArrayRange R_rs1_0(19, 15);
354rs1 += R_rs1_0.read(ba) << 0;
355etiss_uint8 rs2 = 0;
356static BitArrayRange R_rs2_0(24, 20);
357rs2 += R_rs2_0.read(ba) << 0;
358
359// -----------------------------------------------------------------------------
360
361 std::stringstream ss;
362// -----------------------------------------------------------------------------
363ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
364// -----------------------------------------------------------------------------
365 return ss.str();
366 }
367);
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV64IMACFD, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");cp.code()+="etiss_coverage_count(1, 240);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7655);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7623);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7629, 7626, 7624, 7627, 7628);\n";{ cp.code()+="etiss_coverage_count(1, 7654);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 7644, 7643, 7636, 7635, 7634, 7632, 7642, 7641, 7640, 7638);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 7653, 7649, 7648, 7646, 7652, 7650);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");cp.code()+="etiss_coverage_count(1, 243);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7736);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7711);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7717, 7714, 7712, 7715, 7716);\n";{ cp.code()+="etiss_coverage_count(1, 7735);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(11, 7734, 7722, 7721, 7719, 7733, 7727, 7726, 7724, 7732, 7731, 7729);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");cp.code()+="etiss_coverage_count(1, 242);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7710);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7684);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7690, 7687, 7685, 7688, 7689);\n";{ cp.code()+="etiss_coverage_count(1, 7709);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 7708, 7695, 7694, 7692, 7707, 7701, 7700, 7699, 7697, 7706, 7705, 7703);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV64IMACFD, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");cp.code()+="etiss_coverage_count(1, 241);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7683);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7656);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7662, 7659, 7657, 7660, 7661);\n";{ cp.code()+="etiss_coverage_count(1, 7682);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(13, 7681, 7667, 7666, 7664, 7680, 7673, 7672, 7671, 7669, 7679, 7678, 7677, 7675);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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