ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_tum_rvmInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// MUL -------------------------------------------------------------------------
16static InstructionDefinition mul_rd_rs1_rs2 (
17 ISA32_RV64IMACFD,
18 "mul",
19 (uint64_t) 0x2000033,
20 (uint64_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint8 rs2 = 0;
37static BitArrayRange R_rs2_0(24, 20);
38rs2 += R_rs2_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//MUL\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 240);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1189);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
54cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 9457);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_coverage_count(1, 9425);\n";
61if ((rd % 32ULL) != 0LL) { // conditional
62cp.code() += "etiss_coverage_count(5, 9431, 9428, 9426, 9429, 9430);\n";
63{ // block
64cp.code() += "etiss_coverage_count(1, 9456);\n";
65cp.code() += "{ // block\n";
66cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
67cp.code() += "etiss_coverage_count(10, 9446, 9445, 9438, 9437, 9436, 9434, 9444, 9443, 9442, 9440);\n";
68cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
69cp.code() += "etiss_coverage_count(6, 9455, 9451, 9450, 9448, 9454, 9452);\n";
70cp.code() += "} // block\n";
71} // block
72} // conditional
73cp.code() += "} // block\n";
74} // block
75cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
76cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
77// -----------------------------------------------------------------------------
78 cp.getAffectedRegisters().add("instructionPointer", 32);
79 }
80
81 return true;
82 },
83 0,
84 [] (BitArray & ba, Instruction & instr)
85 {
86// -----------------------------------------------------------------------------
87etiss_uint8 rd = 0;
88static BitArrayRange R_rd_0(11, 7);
89rd += R_rd_0.read(ba) << 0;
90etiss_uint8 rs1 = 0;
91static BitArrayRange R_rs1_0(19, 15);
92rs1 += R_rs1_0.read(ba) << 0;
93etiss_uint8 rs2 = 0;
94static BitArrayRange R_rs2_0(24, 20);
95rs2 += R_rs2_0.read(ba) << 0;
96
97// -----------------------------------------------------------------------------
98
99 std::stringstream ss;
100// -----------------------------------------------------------------------------
101ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
102// -----------------------------------------------------------------------------
103 return ss.str();
104 }
105);
106
107// MULH ------------------------------------------------------------------------
108static InstructionDefinition mulh_rd_rs1_rs2 (
109 ISA32_RV64IMACFD,
110 "mulh",
111 (uint64_t) 0x2001033,
112 (uint64_t) 0xfe00707f,
113 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
114 {
115
116// -----------------------------------------------------------------------------
117
118// -----------------------------------------------------------------------------
119
120// -----------------------------------------------------------------------------
121// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
122etiss_uint8 rd = 0;
123static BitArrayRange R_rd_0(11, 7);
124rd += R_rd_0.read(ba) << 0;
125etiss_uint8 rs1 = 0;
126static BitArrayRange R_rs1_0(19, 15);
127rs1 += R_rs1_0.read(ba) << 0;
128etiss_uint8 rs2 = 0;
129static BitArrayRange R_rs2_0(24, 20);
130rs2 += R_rs2_0.read(ba) << 0;
131
132// NOLINTEND(clang-diagnostic-unused-but-set-variable)
133// -----------------------------------------------------------------------------
134
135 {
136 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
137
138 cp.code() = std::string("//MULH\n");
139
140// -----------------------------------------------------------------------------
141cp.code() += "etiss_coverage_count(1, 241);\n";
142{ // block
143cp.code() += "etiss_coverage_count(1, 1189);\n";
144cp.code() += "{ // block\n";
145cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
146cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
147cp.code() += "} // block\n";
148} // block
149{ // block
150cp.code() += "etiss_coverage_count(1, 9485);\n";
151cp.code() += "{ // block\n";
152cp.code() += "etiss_coverage_count(1, 9458);\n";
153if ((rd % 32ULL) != 0LL) { // conditional
154cp.code() += "etiss_coverage_count(5, 9464, 9461, 9459, 9462, 9463);\n";
155{ // block
156cp.code() += "etiss_coverage_count(1, 9484);\n";
157cp.code() += "{ // block\n";
158cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
159cp.code() += "etiss_coverage_count(13, 9483, 9469, 9468, 9466, 9482, 9475, 9474, 9473, 9471, 9481, 9480, 9479, 9477);\n";
160cp.code() += "} // block\n";
161} // block
162} // conditional
163cp.code() += "} // block\n";
164} // block
165cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
166cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
167// -----------------------------------------------------------------------------
168 cp.getAffectedRegisters().add("instructionPointer", 32);
169 }
170
171 return true;
172 },
173 0,
174 [] (BitArray & ba, Instruction & instr)
175 {
176// -----------------------------------------------------------------------------
177etiss_uint8 rd = 0;
178static BitArrayRange R_rd_0(11, 7);
179rd += R_rd_0.read(ba) << 0;
180etiss_uint8 rs1 = 0;
181static BitArrayRange R_rs1_0(19, 15);
182rs1 += R_rs1_0.read(ba) << 0;
183etiss_uint8 rs2 = 0;
184static BitArrayRange R_rs2_0(24, 20);
185rs2 += R_rs2_0.read(ba) << 0;
186
187// -----------------------------------------------------------------------------
188
189 std::stringstream ss;
190// -----------------------------------------------------------------------------
191ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
192// -----------------------------------------------------------------------------
193 return ss.str();
194 }
195);
196
197// MULHSU ----------------------------------------------------------------------
198static InstructionDefinition mulhsu_rd_rs1_rs2 (
199 ISA32_RV64IMACFD,
200 "mulhsu",
201 (uint64_t) 0x2002033,
202 (uint64_t) 0xfe00707f,
203 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
204 {
205
206// -----------------------------------------------------------------------------
207
208// -----------------------------------------------------------------------------
209
210// -----------------------------------------------------------------------------
211// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
212etiss_uint8 rd = 0;
213static BitArrayRange R_rd_0(11, 7);
214rd += R_rd_0.read(ba) << 0;
215etiss_uint8 rs1 = 0;
216static BitArrayRange R_rs1_0(19, 15);
217rs1 += R_rs1_0.read(ba) << 0;
218etiss_uint8 rs2 = 0;
219static BitArrayRange R_rs2_0(24, 20);
220rs2 += R_rs2_0.read(ba) << 0;
221
222// NOLINTEND(clang-diagnostic-unused-but-set-variable)
223// -----------------------------------------------------------------------------
224
225 {
226 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
227
228 cp.code() = std::string("//MULHSU\n");
229
230// -----------------------------------------------------------------------------
231cp.code() += "etiss_coverage_count(1, 242);\n";
232{ // block
233cp.code() += "etiss_coverage_count(1, 1189);\n";
234cp.code() += "{ // block\n";
235cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
236cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
237cp.code() += "} // block\n";
238} // block
239{ // block
240cp.code() += "etiss_coverage_count(1, 9512);\n";
241cp.code() += "{ // block\n";
242cp.code() += "etiss_coverage_count(1, 9486);\n";
243if ((rd % 32ULL) != 0LL) { // conditional
244cp.code() += "etiss_coverage_count(5, 9492, 9489, 9487, 9490, 9491);\n";
245{ // block
246cp.code() += "etiss_coverage_count(1, 9511);\n";
247cp.code() += "{ // block\n";
248cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
249cp.code() += "etiss_coverage_count(12, 9510, 9497, 9496, 9494, 9509, 9503, 9502, 9501, 9499, 9508, 9507, 9505);\n";
250cp.code() += "} // block\n";
251} // block
252} // conditional
253cp.code() += "} // block\n";
254} // block
255cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
256cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
257// -----------------------------------------------------------------------------
258 cp.getAffectedRegisters().add("instructionPointer", 32);
259 }
260
261 return true;
262 },
263 0,
264 [] (BitArray & ba, Instruction & instr)
265 {
266// -----------------------------------------------------------------------------
267etiss_uint8 rd = 0;
268static BitArrayRange R_rd_0(11, 7);
269rd += R_rd_0.read(ba) << 0;
270etiss_uint8 rs1 = 0;
271static BitArrayRange R_rs1_0(19, 15);
272rs1 += R_rs1_0.read(ba) << 0;
273etiss_uint8 rs2 = 0;
274static BitArrayRange R_rs2_0(24, 20);
275rs2 += R_rs2_0.read(ba) << 0;
276
277// -----------------------------------------------------------------------------
278
279 std::stringstream ss;
280// -----------------------------------------------------------------------------
281ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
282// -----------------------------------------------------------------------------
283 return ss.str();
284 }
285);
286
287// MULHU -----------------------------------------------------------------------
288static InstructionDefinition mulhu_rd_rs1_rs2 (
289 ISA32_RV64IMACFD,
290 "mulhu",
291 (uint64_t) 0x2003033,
292 (uint64_t) 0xfe00707f,
293 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
294 {
295
296// -----------------------------------------------------------------------------
297
298// -----------------------------------------------------------------------------
299
300// -----------------------------------------------------------------------------
301// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
302etiss_uint8 rd = 0;
303static BitArrayRange R_rd_0(11, 7);
304rd += R_rd_0.read(ba) << 0;
305etiss_uint8 rs1 = 0;
306static BitArrayRange R_rs1_0(19, 15);
307rs1 += R_rs1_0.read(ba) << 0;
308etiss_uint8 rs2 = 0;
309static BitArrayRange R_rs2_0(24, 20);
310rs2 += R_rs2_0.read(ba) << 0;
311
312// NOLINTEND(clang-diagnostic-unused-but-set-variable)
313// -----------------------------------------------------------------------------
314
315 {
316 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
317
318 cp.code() = std::string("//MULHU\n");
319
320// -----------------------------------------------------------------------------
321cp.code() += "etiss_coverage_count(1, 243);\n";
322{ // block
323cp.code() += "etiss_coverage_count(1, 1189);\n";
324cp.code() += "{ // block\n";
325cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint64)((ic.current_address_ + 4))) + "ULL;\n";
326cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
327cp.code() += "} // block\n";
328} // block
329{ // block
330cp.code() += "etiss_coverage_count(1, 9538);\n";
331cp.code() += "{ // block\n";
332cp.code() += "etiss_coverage_count(1, 9513);\n";
333if ((rd % 32ULL) != 0LL) { // conditional
334cp.code() += "etiss_coverage_count(5, 9519, 9516, 9514, 9517, 9518);\n";
335{ // block
336cp.code() += "etiss_coverage_count(1, 9537);\n";
337cp.code() += "{ // block\n";
338cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
339cp.code() += "etiss_coverage_count(11, 9536, 9524, 9523, 9521, 9535, 9529, 9528, 9526, 9534, 9533, 9531);\n";
340cp.code() += "} // block\n";
341} // block
342} // conditional
343cp.code() += "} // block\n";
344} // block
345cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
346cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
347// -----------------------------------------------------------------------------
348 cp.getAffectedRegisters().add("instructionPointer", 32);
349 }
350
351 return true;
352 },
353 0,
354 [] (BitArray & ba, Instruction & instr)
355 {
356// -----------------------------------------------------------------------------
357etiss_uint8 rd = 0;
358static BitArrayRange R_rd_0(11, 7);
359rd += R_rd_0.read(ba) << 0;
360etiss_uint8 rs1 = 0;
361static BitArrayRange R_rs1_0(19, 15);
362rs1 += R_rs1_0.read(ba) << 0;
363etiss_uint8 rs2 = 0;
364static BitArrayRange R_rs2_0(24, 20);
365rs2 += R_rs2_0.read(ba) << 0;
366
367// -----------------------------------------------------------------------------
368
369 std::stringstream ss;
370// -----------------------------------------------------------------------------
371ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
372// -----------------------------------------------------------------------------
373 return ss.str();
374 }
375);
376// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhu",(uint64_t) 0x2003033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");cp.code()+="etiss_coverage_count(1, 243);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9538);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 9513);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9519, 9516, 9514, 9517, 9518);\n";{ cp.code()+="etiss_coverage_count(1, 9537);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(11, 9536, 9524, 9523, 9521, 9535, 9529, 9528, 9526, 9534, 9533, 9531);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV64IMACFD, "mulh",(uint64_t) 0x2001033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");cp.code()+="etiss_coverage_count(1, 241);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9485);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 9458);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9464, 9461, 9459, 9462, 9463);\n";{ cp.code()+="etiss_coverage_count(1, 9484);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(13, 9483, 9469, 9468, 9466, 9482, 9475, 9474, 9473, 9471, 9481, 9480, 9479, 9477);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhsu",(uint64_t) 0x2002033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");cp.code()+="etiss_coverage_count(1, 242);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9512);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 9486);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9492, 9489, 9487, 9490, 9491);\n";{ cp.code()+="etiss_coverage_count(1, 9511);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(12, 9510, 9497, 9496, 9494, 9509, 9503, 9502, 9501, 9499, 9508, 9507, 9505);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV64IMACFD, "mul",(uint64_t) 0x2000033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");cp.code()+="etiss_coverage_count(1, 240);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9457);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 9425);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9431, 9428, 9426, 9429, 9430);\n";{ cp.code()+="etiss_coverage_count(1, 9456);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 9446, 9445, 9438, 9437, 9436, 9434, 9444, 9443, 9442, 9440);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 9455, 9451, 9450, 9448, 9454, 9452);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint64
uint64_t etiss_uint64
Definition types.h:58
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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