ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_tum_rvmInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // MUL -------------------------------------------------------------------------
16 static InstructionDefinition mul_rd_rs1_rs2 (
17  ISA32_RV64IMACFD,
18  "mul",
19  (uint32_t) 0x2000033,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//MUL\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 if ((rd % 32ULL) != 0LL) { // conditional
55 { // block
56 cp.code() += "{ // block\n";
57 cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
58 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
59 cp.code() += "} // block\n";
60 } // block
61 } // conditional
62 cp.code() += "} // block\n";
63 } // block
64 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
65 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
66 // -----------------------------------------------------------------------------
67  cp.getAffectedRegisters().add("instructionPointer", 32);
68  }
69 
70  return true;
71  },
72  0,
73  [] (BitArray & ba, Instruction & instr)
74  {
75 // -----------------------------------------------------------------------------
76 etiss_uint8 rd = 0;
77 static BitArrayRange R_rd_0(11, 7);
78 rd += R_rd_0.read(ba) << 0;
79 etiss_uint8 rs1 = 0;
80 static BitArrayRange R_rs1_0(19, 15);
81 rs1 += R_rs1_0.read(ba) << 0;
82 etiss_uint8 rs2 = 0;
83 static BitArrayRange R_rs2_0(24, 20);
84 rs2 += R_rs2_0.read(ba) << 0;
85 
86 // -----------------------------------------------------------------------------
87 
88  std::stringstream ss;
89 // -----------------------------------------------------------------------------
90 ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
91 // -----------------------------------------------------------------------------
92  return ss.str();
93  }
94 );
95 
96 // MULH ------------------------------------------------------------------------
97 static InstructionDefinition mulh_rd_rs1_rs2 (
98  ISA32_RV64IMACFD,
99  "mulh",
100  (uint32_t) 0x2001033,
101  (uint32_t) 0xfe00707f,
102  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
103  {
104 
105 // -----------------------------------------------------------------------------
106 
107 // -----------------------------------------------------------------------------
108 
109 // -----------------------------------------------------------------------------
110 etiss_uint8 rd = 0;
111 static BitArrayRange R_rd_0(11, 7);
112 rd += R_rd_0.read(ba) << 0;
113 etiss_uint8 rs1 = 0;
114 static BitArrayRange R_rs1_0(19, 15);
115 rs1 += R_rs1_0.read(ba) << 0;
116 etiss_uint8 rs2 = 0;
117 static BitArrayRange R_rs2_0(24, 20);
118 rs2 += R_rs2_0.read(ba) << 0;
119 
120 // -----------------------------------------------------------------------------
121 
122  {
123  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
124 
125  cp.code() = std::string("//MULH\n");
126 
127 // -----------------------------------------------------------------------------
128 { // block
129 cp.code() += "{ // block\n";
130 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
131 cp.code() += "} // block\n";
132 } // block
133 { // block
134 cp.code() += "{ // block\n";
135 if ((rd % 32ULL) != 0LL) { // conditional
136 { // block
137 cp.code() += "{ // block\n";
138 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
139 cp.code() += "} // block\n";
140 } // block
141 } // conditional
142 cp.code() += "} // block\n";
143 } // block
144 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
145 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
146 // -----------------------------------------------------------------------------
147  cp.getAffectedRegisters().add("instructionPointer", 32);
148  }
149 
150  return true;
151  },
152  0,
153  [] (BitArray & ba, Instruction & instr)
154  {
155 // -----------------------------------------------------------------------------
156 etiss_uint8 rd = 0;
157 static BitArrayRange R_rd_0(11, 7);
158 rd += R_rd_0.read(ba) << 0;
159 etiss_uint8 rs1 = 0;
160 static BitArrayRange R_rs1_0(19, 15);
161 rs1 += R_rs1_0.read(ba) << 0;
162 etiss_uint8 rs2 = 0;
163 static BitArrayRange R_rs2_0(24, 20);
164 rs2 += R_rs2_0.read(ba) << 0;
165 
166 // -----------------------------------------------------------------------------
167 
168  std::stringstream ss;
169 // -----------------------------------------------------------------------------
170 ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
171 // -----------------------------------------------------------------------------
172  return ss.str();
173  }
174 );
175 
176 // MULHSU ----------------------------------------------------------------------
177 static InstructionDefinition mulhsu_rd_rs1_rs2 (
178  ISA32_RV64IMACFD,
179  "mulhsu",
180  (uint32_t) 0x2002033,
181  (uint32_t) 0xfe00707f,
182  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
183  {
184 
185 // -----------------------------------------------------------------------------
186 
187 // -----------------------------------------------------------------------------
188 
189 // -----------------------------------------------------------------------------
190 etiss_uint8 rd = 0;
191 static BitArrayRange R_rd_0(11, 7);
192 rd += R_rd_0.read(ba) << 0;
193 etiss_uint8 rs1 = 0;
194 static BitArrayRange R_rs1_0(19, 15);
195 rs1 += R_rs1_0.read(ba) << 0;
196 etiss_uint8 rs2 = 0;
197 static BitArrayRange R_rs2_0(24, 20);
198 rs2 += R_rs2_0.read(ba) << 0;
199 
200 // -----------------------------------------------------------------------------
201 
202  {
203  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
204 
205  cp.code() = std::string("//MULHSU\n");
206 
207 // -----------------------------------------------------------------------------
208 { // block
209 cp.code() += "{ // block\n";
210 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
211 cp.code() += "} // block\n";
212 } // block
213 { // block
214 cp.code() += "{ // block\n";
215 if ((rd % 32ULL) != 0LL) { // conditional
216 { // block
217 cp.code() += "{ // block\n";
218 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
219 cp.code() += "} // block\n";
220 } // block
221 } // conditional
222 cp.code() += "} // block\n";
223 } // block
224 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
225 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
226 // -----------------------------------------------------------------------------
227  cp.getAffectedRegisters().add("instructionPointer", 32);
228  }
229 
230  return true;
231  },
232  0,
233  [] (BitArray & ba, Instruction & instr)
234  {
235 // -----------------------------------------------------------------------------
236 etiss_uint8 rd = 0;
237 static BitArrayRange R_rd_0(11, 7);
238 rd += R_rd_0.read(ba) << 0;
239 etiss_uint8 rs1 = 0;
240 static BitArrayRange R_rs1_0(19, 15);
241 rs1 += R_rs1_0.read(ba) << 0;
242 etiss_uint8 rs2 = 0;
243 static BitArrayRange R_rs2_0(24, 20);
244 rs2 += R_rs2_0.read(ba) << 0;
245 
246 // -----------------------------------------------------------------------------
247 
248  std::stringstream ss;
249 // -----------------------------------------------------------------------------
250 ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
251 // -----------------------------------------------------------------------------
252  return ss.str();
253  }
254 );
255 
256 // MULHU -----------------------------------------------------------------------
257 static InstructionDefinition mulhu_rd_rs1_rs2 (
258  ISA32_RV64IMACFD,
259  "mulhu",
260  (uint32_t) 0x2003033,
261  (uint32_t) 0xfe00707f,
262  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
263  {
264 
265 // -----------------------------------------------------------------------------
266 
267 // -----------------------------------------------------------------------------
268 
269 // -----------------------------------------------------------------------------
270 etiss_uint8 rd = 0;
271 static BitArrayRange R_rd_0(11, 7);
272 rd += R_rd_0.read(ba) << 0;
273 etiss_uint8 rs1 = 0;
274 static BitArrayRange R_rs1_0(19, 15);
275 rs1 += R_rs1_0.read(ba) << 0;
276 etiss_uint8 rs2 = 0;
277 static BitArrayRange R_rs2_0(24, 20);
278 rs2 += R_rs2_0.read(ba) << 0;
279 
280 // -----------------------------------------------------------------------------
281 
282  {
283  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
284 
285  cp.code() = std::string("//MULHU\n");
286 
287 // -----------------------------------------------------------------------------
288 { // block
289 cp.code() += "{ // block\n";
290 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
291 cp.code() += "} // block\n";
292 } // block
293 { // block
294 cp.code() += "{ // block\n";
295 if ((rd % 32ULL) != 0LL) { // conditional
296 { // block
297 cp.code() += "{ // block\n";
298 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
299 cp.code() += "} // block\n";
300 } // block
301 } // conditional
302 cp.code() += "} // block\n";
303 } // block
304 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
305 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
306 // -----------------------------------------------------------------------------
307  cp.getAffectedRegisters().add("instructionPointer", 32);
308  }
309 
310  return true;
311  },
312  0,
313  [] (BitArray & ba, Instruction & instr)
314  {
315 // -----------------------------------------------------------------------------
316 etiss_uint8 rd = 0;
317 static BitArrayRange R_rd_0(11, 7);
318 rd += R_rd_0.read(ba) << 0;
319 etiss_uint8 rs1 = 0;
320 static BitArrayRange R_rs1_0(19, 15);
321 rs1 += R_rs1_0.read(ba) << 0;
322 etiss_uint8 rs2 = 0;
323 static BitArrayRange R_rs2_0(24, 20);
324 rs2 += R_rs2_0.read(ba) << 0;
325 
326 // -----------------------------------------------------------------------------
327 
328  std::stringstream ss;
329 // -----------------------------------------------------------------------------
330 ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
331 // -----------------------------------------------------------------------------
332  return ss.str();
333  }
334 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV64IMACFD, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV64IMACFD, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV64IMACFD, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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