ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_tum_rvaInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LRW -------------------------------------------------------------------------
16 static InstructionDefinition lrw_rd_rs1_rl_aq (
17  ISA32_RV64IMACFD,
18  "lrw",
19  (uint32_t) 0x1000202f,
20  (uint32_t) 0xf9f0707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rl = 0;
36 static BitArrayRange R_rl_0(25, 25);
37 rl += R_rl_0.read(ba) << 0;
38 etiss_uint8 aq = 0;
39 static BitArrayRange R_aq_0(26, 26);
40 aq += R_aq_0.read(ba) << 0;
41 
42 // -----------------------------------------------------------------------------
43 
44  {
45  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
46 
47  cp.code() = std::string("//LRW\n");
48 
49 // -----------------------------------------------------------------------------
50 cp.code() += "etiss_coverage_count(1, 181);\n";
51 { // block
52 cp.code() += "etiss_coverage_count(1, 1169);\n";
53 cp.code() += "{ // block\n";
54 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
55 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
56 cp.code() += "} // block\n";
57 } // block
58 { // block
59 cp.code() += "etiss_coverage_count(1, 6444);\n";
60 cp.code() += "{ // block\n";
61 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
62 cp.code() += "etiss_coverage_count(4, 6422, 6421, 6420, 6418);\n";
63 cp.code() += "etiss_uint32 mem_val_0;\n";
64 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
65 cp.code() += "if (cpu->exception) { // conditional\n";
66 { // procedure
67 cp.code() += "{ // procedure\n";
68 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
69 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
70 cp.code() += "} // procedure\n";
71 } // procedure
72 cp.code() += "} // conditional\n";
73 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
74 cp.code() += "etiss_coverage_count(4, 6429, 6428, 6426, 6425);\n";
75 cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
76 cp.code() += "etiss_coverage_count(3, 6432, 6430, 6431);\n";
77 cp.code() += "etiss_coverage_count(1, 6433);\n";
78 if (rd) { // conditional
79 cp.code() += "etiss_coverage_count(1, 6434);\n";
80 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
81 cp.code() += "etiss_coverage_count(6, 6443, 6439, 6438, 6436, 6442, 6440);\n";
82 } // conditional
83 cp.code() += "} // block\n";
84 } // block
85 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
86 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
87 // -----------------------------------------------------------------------------
88  cp.getAffectedRegisters().add("instructionPointer", 32);
89  }
90  {
91  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
92 
93  cp.code() = std::string("//LRW\n");
94 
95 // -----------------------------------------------------------------------------
96 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
97 // -----------------------------------------------------------------------------
98  }
99 
100  return true;
101  },
102  0,
103  [] (BitArray & ba, Instruction & instr)
104  {
105 // -----------------------------------------------------------------------------
106 etiss_uint8 rd = 0;
107 static BitArrayRange R_rd_0(11, 7);
108 rd += R_rd_0.read(ba) << 0;
109 etiss_uint8 rs1 = 0;
110 static BitArrayRange R_rs1_0(19, 15);
111 rs1 += R_rs1_0.read(ba) << 0;
112 etiss_uint8 rl = 0;
113 static BitArrayRange R_rl_0(25, 25);
114 rl += R_rl_0.read(ba) << 0;
115 etiss_uint8 aq = 0;
116 static BitArrayRange R_aq_0(26, 26);
117 aq += R_aq_0.read(ba) << 0;
118 
119 // -----------------------------------------------------------------------------
120 
121  std::stringstream ss;
122 // -----------------------------------------------------------------------------
123 ss << "lrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
124 // -----------------------------------------------------------------------------
125  return ss.str();
126  }
127 );
128 
129 // SCW -------------------------------------------------------------------------
130 static InstructionDefinition scw_rd_rs1_rs2_rl_aq (
131  ISA32_RV64IMACFD,
132  "scw",
133  (uint32_t) 0x1800202f,
134  (uint32_t) 0xf800707f,
135  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
136  {
137 
138 // -----------------------------------------------------------------------------
139 
140 // -----------------------------------------------------------------------------
141 
142 // -----------------------------------------------------------------------------
143 etiss_uint8 rd = 0;
144 static BitArrayRange R_rd_0(11, 7);
145 rd += R_rd_0.read(ba) << 0;
146 etiss_uint8 rs1 = 0;
147 static BitArrayRange R_rs1_0(19, 15);
148 rs1 += R_rs1_0.read(ba) << 0;
149 etiss_uint8 rs2 = 0;
150 static BitArrayRange R_rs2_0(24, 20);
151 rs2 += R_rs2_0.read(ba) << 0;
152 etiss_uint8 rl = 0;
153 static BitArrayRange R_rl_0(25, 25);
154 rl += R_rl_0.read(ba) << 0;
155 etiss_uint8 aq = 0;
156 static BitArrayRange R_aq_0(26, 26);
157 aq += R_aq_0.read(ba) << 0;
158 
159 // -----------------------------------------------------------------------------
160 
161  {
162  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
163 
164  cp.code() = std::string("//SCW\n");
165 
166 // -----------------------------------------------------------------------------
167 cp.code() += "etiss_coverage_count(1, 182);\n";
168 { // block
169 cp.code() += "etiss_coverage_count(1, 1169);\n";
170 cp.code() += "{ // block\n";
171 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
172 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
173 cp.code() += "} // block\n";
174 } // block
175 { // block
176 cp.code() += "etiss_coverage_count(1, 6482);\n";
177 cp.code() += "{ // block\n";
178 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
179 cp.code() += "etiss_coverage_count(4, 6451, 6450, 6449, 6447);\n";
180 cp.code() += "etiss_coverage_count(1, 6452);\n";
181 cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
182 cp.code() += "etiss_coverage_count(3, 6455, 6453, 6454);\n";
183 cp.code() += "etiss_uint32 mem_val_0;\n";
184 cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
185 cp.code() += "etiss_coverage_count(7, 6466, 6458, 6457, 6465, 6463, 6462, 6460);\n";
186 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
187 cp.code() += "if (cpu->exception) { // conditional\n";
188 { // procedure
189 cp.code() += "{ // procedure\n";
190 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
191 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
192 cp.code() += "} // procedure\n";
193 } // procedure
194 cp.code() += "} // conditional\n";
195 cp.code() += "} // conditional\n";
196 cp.code() += "etiss_coverage_count(1, 6467);\n";
197 if (rd) { // conditional
198 cp.code() += "etiss_coverage_count(1, 6468);\n";
199 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
200 cp.code() += "etiss_coverage_count(7, 6477, 6473, 6472, 6470, 6476, 6474, 6475);\n";
201 } // conditional
202 cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";
203 cp.code() += "etiss_coverage_count(2, 6481, 6478);\n";
204 cp.code() += "} // block\n";
205 } // block
206 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
207 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
208 // -----------------------------------------------------------------------------
209  cp.getAffectedRegisters().add("instructionPointer", 32);
210  }
211  {
212  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
213 
214  cp.code() = std::string("//SCW\n");
215 
216 // -----------------------------------------------------------------------------
217 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
218 // -----------------------------------------------------------------------------
219  }
220 
221  return true;
222  },
223  0,
224  [] (BitArray & ba, Instruction & instr)
225  {
226 // -----------------------------------------------------------------------------
227 etiss_uint8 rd = 0;
228 static BitArrayRange R_rd_0(11, 7);
229 rd += R_rd_0.read(ba) << 0;
230 etiss_uint8 rs1 = 0;
231 static BitArrayRange R_rs1_0(19, 15);
232 rs1 += R_rs1_0.read(ba) << 0;
233 etiss_uint8 rs2 = 0;
234 static BitArrayRange R_rs2_0(24, 20);
235 rs2 += R_rs2_0.read(ba) << 0;
236 etiss_uint8 rl = 0;
237 static BitArrayRange R_rl_0(25, 25);
238 rl += R_rl_0.read(ba) << 0;
239 etiss_uint8 aq = 0;
240 static BitArrayRange R_aq_0(26, 26);
241 aq += R_aq_0.read(ba) << 0;
242 
243 // -----------------------------------------------------------------------------
244 
245  std::stringstream ss;
246 // -----------------------------------------------------------------------------
247 ss << "scw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
248 // -----------------------------------------------------------------------------
249  return ss.str();
250  }
251 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
scw_rd_rs1_rs2_rl_aq
static InstructionDefinition scw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "scw",(uint32_t) 0x1800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SCW\n");cp.code()+="etiss_coverage_count(1, 182);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6482);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6451, 6450, 6449, 6447);\n";cp.code()+="etiss_coverage_count(1, 6452);\n";cp.code()+="if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";cp.code()+="etiss_coverage_count(3, 6455, 6453, 6454);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 6466, 6458, 6457, 6465, 6463, 6462, 6460);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // conditional\n";cp.code()+="etiss_coverage_count(1, 6467);\n";if(rd) { cp.code()+="etiss_coverage_count(1, 6468);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";cp.code()+="etiss_coverage_count(7, 6477, 6473, 6472, 6470, 6476, 6474, 6475);\n";} cp.code()+="((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";cp.code()+="etiss_coverage_count(2, 6481, 6478);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SCW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "scw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
lrw_rd_rs1_rl_aq
static InstructionDefinition lrw_rd_rs1_rl_aq(ISA32_RV64IMACFD, "lrw",(uint32_t) 0x1000202f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LRW\n");cp.code()+="etiss_coverage_count(1, 181);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6444);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6422, 6421, 6420, 6418);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6429, 6428, 6426, 6425);\n";cp.code()+="((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";cp.code()+="etiss_coverage_count(3, 6432, 6430, 6431);\n";cp.code()+="etiss_coverage_count(1, 6433);\n";if(rd) { cp.code()+="etiss_coverage_count(1, 6434);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 6443, 6439, 6438, 6436, 6442, 6440);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LRW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "lrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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