11 using namespace etiss;
31 rd += R_rd_0.
read(ba) << 0;
34 rs1 += R_rs1_0.
read(ba) << 0;
37 rl += R_rl_0.
read(ba) << 0;
40 aq += R_aq_0.
read(ba) << 0;
47 cp.
code() = std::string(
"//LRD\n");
51 cp.
code() +=
"{ // block\n";
53 cp.
code() +=
"} // block\n";
56 cp.
code() +=
"{ // block\n";
57 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
58 cp.
code() +=
"etiss_uint64 mem_val_0;\n";
59 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
60 cp.
code() +=
"if (cpu->exception) { // conditional\n";
62 cp.
code() +=
"{ // procedure\n";
63 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
65 cp.
code() +=
"} // procedure\n";
67 cp.
code() +=
"} // conditional\n";
68 cp.
code() +=
"etiss_int64 res = (etiss_int64)(mem_val_0);\n";
69 cp.
code() +=
"((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";
71 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res);\n";
73 cp.
code() +=
"} // block\n";
76 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
83 cp.
code() = std::string(
"//LRD\n");
86 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
98 rd += R_rd_0.read(ba) << 0;
101 rs1 += R_rs1_0.read(ba) << 0;
104 rl += R_rl_0.read(ba) << 0;
107 aq += R_aq_0.read(ba) << 0;
111 std::stringstream ss;
113 ss <<
"lrd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
135 rd += R_rd_0.
read(ba) << 0;
138 rs1 += R_rs1_0.
read(ba) << 0;
141 rs2 += R_rs2_0.
read(ba) << 0;
144 rl += R_rl_0.
read(ba) << 0;
147 aq += R_aq_0.
read(ba) << 0;
154 cp.
code() = std::string(
"//SCD\n");
158 cp.
code() +=
"{ // block\n";
160 cp.
code() +=
"} // block\n";
163 cp.
code() +=
"{ // block\n";
164 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
165 cp.
code() +=
"if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
166 cp.
code() +=
"etiss_uint64 mem_val_0;\n";
167 cp.
code() +=
"mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
168 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
169 cp.
code() +=
"if (cpu->exception) { // conditional\n";
171 cp.
code() +=
"{ // procedure\n";
172 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
174 cp.
code() +=
"} // procedure\n";
176 cp.
code() +=
"} // conditional\n";
177 cp.
code() +=
"} // conditional\n";
179 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";
181 cp.
code() +=
"((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";
182 cp.
code() +=
"} // block\n";
185 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
192 cp.
code() = std::string(
"//SCD\n");
195 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
207 rd += R_rd_0.read(ba) << 0;
210 rs1 += R_rs1_0.read(ba) << 0;
213 rs2 += R_rs2_0.read(ba) << 0;
216 rl += R_rl_0.read(ba) << 0;
219 aq += R_aq_0.read(ba) << 0;
223 std::stringstream ss;
225 ss <<
"scd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition lrd_rd_rs1_rl_aq(ISA32_RV64IMACFD, "lrd",(uint32_t) 0x1000302f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LRD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = (etiss_int64)(mem_val_0);\n";cp.code()+="((RV64IMACFD*)cpu)->RES_ADDR = offs;\n";if(rd) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LRD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "lrd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition scd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "scd",(uint32_t) 0x1800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SCD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // conditional\n";if(rd) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n";} cp.code()+="((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SCD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "scd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static __inline__ uint32_t
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.