ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_ZifenceiInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// FENCE_I ---------------------------------------------------------------------
18 "fence_i",
19 (uint32_t) 0x00100f,
20 (uint32_t) 0x00707f,
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint16 imm = 0;
37static BitArrayRange R_imm_0(31, 20);
38imm += R_imm_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
45
46 cp.code() = std::string("//FENCE_I\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
50cp.code() += "etiss_coverage_count(1, 148);\n";
51{ // block
52cp.code() += "etiss_coverage_count(1, 1169);\n";
53cp.code() += "{ // block\n";
54cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
55cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
56cp.code() += "} // block\n";
57} // block
58cp.code() += "((RV64IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
59cp.code() += "etiss_coverage_count(3, 6360, 6358, 6359);\n";
60cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
61cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
62// -----------------------------------------------------------------------------
63 cp.getAffectedRegisters().add("instructionPointer", 32);
64 }
65 {
67
68 cp.code() = std::string("//FENCE_I\n");
69
70// -----------------------------------------------------------------------------
71cp.code() += "return cpu->exception;\n";
72// -----------------------------------------------------------------------------
73 }
74
75 return true;
76 },
77 0,
78 [] (BitArray & ba, Instruction & instr)
79 {
80// -----------------------------------------------------------------------------
81etiss_uint8 rd = 0;
82static BitArrayRange R_rd_0(11, 7);
83rd += R_rd_0.read(ba) << 0;
84etiss_uint8 rs1 = 0;
85static BitArrayRange R_rs1_0(19, 15);
86rs1 += R_rs1_0.read(ba) << 0;
87etiss_uint16 imm = 0;
88static BitArrayRange R_imm_0(31, 20);
89imm += R_imm_0.read(ba) << 0;
90
91// -----------------------------------------------------------------------------
92
93 std::stringstream ss;
94// -----------------------------------------------------------------------------
95ss << "fence_i" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
96// -----------------------------------------------------------------------------
97 return ss.str();
98 }
99);
100// clang-format on
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition fence_i_rd_rs1_imm(ISA32_RV64IMACFD, "fence_i",(uint32_t) 0x00100f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE_I\n");cp.code()+="cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";cp.code()+="etiss_coverage_count(1, 148);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="((RV64IMACFD*)cpu)->FENCE[1ULL] = "+std::to_string(imm)+"ULL;\n";cp.code()+="etiss_coverage_count(3, 6360, 6358, 6359);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FENCE_I\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence_i"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
uint8_t etiss_uint8
Definition types.h:49
uint16_t etiss_uint16
Definition types.h:52
Contains a small code snipped.
Definition CodePart.h:348
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:364
std::string & code()
Definition CodePart.h:378
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
A set of CodeParts.
Definition CodePart.h:399
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
stores a bit vector
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.
forwards: include/jit/*
Definition Benchmark.h:17